JPS62185372A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS62185372A JPS62185372A JP61027420A JP2742086A JPS62185372A JP S62185372 A JPS62185372 A JP S62185372A JP 61027420 A JP61027420 A JP 61027420A JP 2742086 A JP2742086 A JP 2742086A JP S62185372 A JPS62185372 A JP S62185372A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- type
- forming
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 230000015556 catabolic process Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 238000001947 vapour-phase growth Methods 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000000605 extraction Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000002253 acid Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0886—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は半導体装置及びその製造方法に関し、特に高耐
圧のＤＭＯ３ｌ−ランジスタに使用されるものである。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a semiconductor device and a method for manufacturing the same, and is particularly used for a high-voltage DMO3l-transistor.
（従来の技術）
周知の如く、例えばＤＭＯ８＋−ランジスクのオン抵抗
を下げる方法としては、１〜ランジスタの各構成部の抵
抗を下げる方法が取られている。しかしながら、トラン
ジスタの降伏電圧を高めるためには、１〜ランジスタを
構成するＰＮ接合のうち少なくとも１つの降伏電圧を高
くしなければならない。ところで、ブレーナ技術を用い
て形成されるＰＮ接合では、その端部での曲率と不Ｉ１
１！１ｔｌＪ分布により降伏電圧が決定する。しかるに
、この降伏電圧を高めるには、深い不純物拡散を行なう
と同時に拡散を行われる側の濃度を小さくしたり、又は
ドレイン電極と接続する高濃度の拡散層とＰＮ接合の距
離をとらなければならず、いずれの場合もオン抵抗を小
さくするのとは逆の操作を行なうことになる。(Prior Art) As is well known, a method for lowering the on-resistance of, for example, a DMO8+- transistor is to lower the resistance of each component of the transistor. However, in order to increase the breakdown voltage of the transistor, it is necessary to increase the breakdown voltage of at least one of the PN junctions forming the transistor. By the way, in a PN junction formed using the Brainer technology, the curvature and the irregularity at the end are
The breakdown voltage is determined by the 1!1tlJ distribution. However, in order to increase this breakdown voltage, it is necessary to perform deep impurity diffusion and at the same time reduce the concentration on the diffusion side, or to increase the distance between the high concentration diffusion layer connected to the drain electrode and the PN junction. First, in either case, the operation opposite to that for reducing the on-resistance is performed.
（発明が解決しようとする問題点）
しかしながら、従来のＤＭＯＳトランジスタにおいては
、電流の流れる部分が、高耐圧化に伴う高抵抗の半導体
層の形成により必要以上に多い。(Problems to be Solved by the Invention) However, in the conventional DMOS transistor, the number of parts through which current flows is larger than necessary due to the formation of a high-resistance semiconductor layer due to the increase in breakdown voltage.
従って、オン抵抗が必要以上に高くなる。Therefore, the on-resistance becomes higher than necessary.
本発明は上記事情に鑑みてなされたもので、従来と比ベ
オン抵抗を減少できる半導体装置及びその製造方法を提
供することを目的とする。The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce the Veon resistance compared to the conventional semiconductor device.
［発明の構成］
（問題点を解決するための手段）
本願第１の発明は、第１導電型の半導体基板と、この半
導体基板の一生面に形成された第２導電型の高不純物濃
度の埋込み層と、この埋込み層に囲まれるように形成さ
れた第２導電型の低不純物濃度の第１半導体層と、この
第１半導体層の表面に形成された耐圧補正用の第１導電
型の第２半導体層と、この第２半導体層に形成された半
導体素子からなり、前記半導体素子の領域直下に位置す
る前記半導体基板部分を前記埋込み層側に突出させ、前
記埋込み層の表面と第２半導体層の底面間の距離を全て
の！！域で略一定とすることにより、オン抵抗の低減を
図ったものである。[Structure of the Invention] (Means for Solving the Problems) The first invention of the present application includes a semiconductor substrate of a first conductivity type and a high impurity concentration of a second conductivity type formed on the whole surface of the semiconductor substrate. a buried layer, a first semiconductor layer of a second conductivity type with a low impurity concentration formed so as to be surrounded by the buried layer, and a first semiconductor layer of a first conductivity type for breakdown voltage correction formed on the surface of the first semiconductor layer. The semiconductor substrate includes a second semiconductor layer and a semiconductor element formed in the second semiconductor layer, and the semiconductor substrate portion located directly under the semiconductor element is made to protrude toward the buried layer, and the surface of the buried layer and the second The distance between the bottom surfaces of the semiconductor layers is all! ! The on-resistance is reduced by making it substantially constant within the range.
本願第２の発明は、第１導電型の半導体基板の一生面に
マスク材を用いて該マスク材の幅の１．／２よりも浅い
深さの溝を形成するとともに、前記マスク材下の前記基
板にマスク材側に突出する突起を形成する工程と、前記
溝から露出する前記基板表面に第２導電型の高年１ＩＴ
ｌ物Ｗｉ度の埋込み層を形成する工程と、気相成長を行
ない前記溝内に第１導電型の低不純物濃度の第１半導体
層を形成する工程と、この第１半導体層の表面に底面か
ら前記埋込み層の表面までの距離が略一定の耐圧補正用
の第１導電型の第２半導体層を形成する工程と、この第
２半導体層に半導体素子を形成する工程とを具備し、オ
ン抵抗の減少を図ったものである。The second invention of the present application uses a mask material on the whole surface of a semiconductor substrate of a first conductivity type, and uses a mask material with a width of 1. forming a groove with a depth shallower than /2, and forming a protrusion protruding toward the mask material side on the substrate under the mask material; 1 IT year
a step of forming a buried layer of low impurity concentration, a step of forming a first semiconductor layer of a first conductivity type with a low impurity concentration in the trench by vapor phase growth, and a step of forming a bottom surface on the surface of the first semiconductor layer. the step of forming a second semiconductor layer of the first conductivity type for withstand voltage correction having a substantially constant distance from This is intended to reduce resistance.
（作用）
本発明によれば、ＤＭＯＳトランジスタの電流経路に相
当する半導体基板の所定の部分に突起を形成することに
より、実質上の高抵抗層（ＶＧ層）を低減でき、もって
オン抵抗が低減できる。(Function) According to the present invention, by forming a protrusion on a predetermined portion of the semiconductor substrate corresponding to the current path of a DMOS transistor, the substantial high resistance layer (VG layer) can be reduced, thereby reducing the on-resistance. can.
（実施例）
以下、本発明の一実施例を第１図（ａ）〜（ｅ）及び第
２図を参照して説明する。(Example) Hereinafter, an example of the present invention will be described with reference to FIGS. 1(a) to (e) and FIG. 2.
まず、例えばＰ−型のシリコン基板１上の所定の位置に
、マスク材としての幅（Ｗ）５０譚のシ、 リコン酸
化膜（Ｓ ｉ ０２ ｇりパターン２を形成したく第１
図（ａ）図示）。つづいて、このパターン２を用いて前
記基板１を弗硝酸又はＫＯＨ等により選択的にエツチン
グし、深さくＤ）３０ＩＲの溝３を形成した。ここで、
溝３を形成する際にＷ＜２０となるようにすることによ
り、前記パターン２の中心Ｐの直下に位置する前記基板
１に上方に突出する理想的な突起４が形成された（第１
図（ｂ）及び第２図図示）。なお、Ｗ＞２Ｄの条件で溝
を形成すると、十分な高さくＨ）の突起が形成されず、
オン抵抗の低減が十分でない。次いで、前記パターン２
を除去した後、溝３から露出する前記基板１の表面にｎ
型不純物を導入し、Ｎ＋型の埋込み層（ドレイン引出し
ｒＩＡ域）５を形成した（第１図（Ｃ）図示）。更に、
エピタキシャル成長を行なうことにより、前記埋込み層
５上にドレイン領域としてのＮ−型の第１半導体層（Ｖ
Ｇ層）６を形成した。なお、前記突起４はこのＶＧｌｉ
６の深さの半分程までに達することになる。しかる後、
ｎ型不純物の拡散により前記ＶＧ層６の表面に中央部が
開孔したＰ型の第２半導体！（ガードリング）７を形成
した（第１図（ｄ）図示）。ここで、同図（ｄ）におい
て、前記突起４の存在により、前記埋込み［５の表面と
ガードリングツ底面間の距１１１１ｉＬは全ての領域で
等しくなった。First, at a predetermined position on, for example, a P-type silicon substrate 1, a silicon oxide film (Si02g) pattern 2 having a width (W) of 50 mm as a mask material is formed.
Figure (a) shown). Subsequently, using this pattern 2, the substrate 1 was selectively etched with fluoronitric acid or KOH to form a groove 3 having a depth of D) 30IR. here,
By setting W<20 when forming the groove 3, an ideal protrusion 4 protruding upward was formed on the substrate 1 located directly below the center P of the pattern 2 (first
Figure (b) and Figure 2 (illustration). Note that if the groove is formed under the condition of W>2D, the protrusion H) will not be formed with sufficient height,
On-resistance reduction is not sufficient. Next, the pattern 2
After removing n, the surface of the substrate 1 exposed from the groove 3 is
A type impurity was introduced to form an N+ type buried layer (drain extraction rIA region) 5 (as shown in FIG. 1C). Furthermore,
By performing epitaxial growth, an N- type first semiconductor layer (V
G layer) 6 was formed. Note that the protrusion 4 is connected to this VGli
It will reach about half of the depth of 6. After that,
A P-type second semiconductor in which a hole is opened in the center on the surface of the VG layer 6 due to diffusion of n-type impurities! (Guard ring) 7 was formed (as shown in FIG. 1(d)). Here, in the same figure (d), due to the presence of the protrusion 4, the distance 1111iL between the surface of the embedding [5] and the bottom surface of the guard ring became equal in all regions.
以下、周知の技術を用いる。即ち、まず前記ガードリン
ク７の内周縁側にＶＧ層６にまたがるようにｐ型不純物
拡散を行ない、リング状の第３半導体層（バックゲート
領域）８を形成する。つづいて、前記基板１上にバック
ゲート領域８のリング内周縁部に沿ってゲート酸化膜（
図示せず）を介して多結晶シリコンからなるリング状の
ゲート電慟９を形成した。次いで、このグー１− ｉｆ
ｆｆｉ ９をマスクとしてセルファラインによりｎ型
不純物を前記バックグー１〜領［８の表面に導入し、Ｎ
＋型のソース領域１０を形成するとともに、前記基板１
、埋込み層５及びＶＧ１６にまたがるようにドレイン電
極の取出しためのＮ＋拡散層１１を形成した。次いで、
前記バツクゲート領域８の表面にガードリング７にまた
がるＰ“型のバックゲートのコンタクト領域１２を形成
し、ＤＭＯＳトランジスタを製造した（第１図（ｅ）図
示）。Hereinafter, a well-known technique will be used. That is, first, a p-type impurity is diffused to the inner peripheral edge side of the guard link 7 so as to straddle the VG layer 6, thereby forming a ring-shaped third semiconductor layer (back gate region) 8. Subsequently, a gate oxide film (
A ring-shaped gate electrode 9 made of polycrystalline silicon was formed via a polycrystalline silicon (not shown). Next, this goo 1-if
Using ffi 9 as a mask, n-type impurities were introduced into the surfaces of the background regions 1 to 8 using Selfa Line, and
While forming a + type source region 10, the substrate 1
, an N+ diffusion layer 11 for taking out the drain electrode was formed so as to span the buried layer 5 and the VG 16. Then,
A P" type back gate contact region 12 spanning the guard ring 7 was formed on the surface of the back gate region 8, and a DMOS transistor was manufactured (as shown in FIG. 1(e)).
上記実施例によれば、埋込み層５を形成するための溝３
を形成する際、第２図に示す如くマスク材としての５１
０２膜パターン２の幅Ｗを、）苫３の深さＤに対しＷ
＜ ２ Ｄなる条件で行なうため、高さ１」がＶＧ層６
の深さの半分程までに達した突起４が基板１の所定の位
＠（ＤＭＯＳトランジスタの電流の経路）に形成され、
ＶＧ層６、ガードリンク７の形成後、埋込み層５の表面
とガードリンク７の底面間の距離しを等しくできる。従
って、実買上のＶＧ層６は突起４の高さの平均分削減さ
れると考えられ、オン抵抗を従来よりも低減できる。事
実、低減率は従来のトランジスタと比べ２０〜３０％で
あった。According to the above embodiment, the groove 3 for forming the buried layer 5
51 as a mask material as shown in FIG.
02 The width W of the film pattern 2 is W relative to the depth D of the toma 3.
< 2D, so the height 1" is the VG layer 6.
A protrusion 4 reaching about half the depth of is formed at a predetermined position on the substrate 1 (the current path of the DMOS transistor),
After forming the VG layer 6 and the guard link 7, the distance between the surface of the buried layer 5 and the bottom surface of the guard link 7 can be made equal. Therefore, it is thought that the actual VG layer 6 is reduced by the average height of the protrusions 4, and the on-resistance can be reduced compared to the conventional one. In fact, the reduction rate was 20-30% compared to conventional transistors.
また、上記実施例に係るＤＭＯＳトランジスタは、第１
図（ｅ）に示す如く、Ｐ４″型のシリコン基板１の表面
にＮ＋型の埋込み層（ドレイン引出し領域）５を設け、
この埋込み１Ｉｉ５上に該埋込み層５に囲まれるように
Ｎ＋型のＶＧ層６を設け、更にこのＶＧ層６の表面にＰ
型のガードリング７を設け、かつ前記ガードリンク７の
中央の開口部直下に位置する基板部分に埋込み層５の表
面とガードリング７の底面との距離しが等しくなるよう
な突起４を設けた構造となっている。従って、前述した
と同様、オン抵抗の減少が可能となる。Further, the DMOS transistor according to the above embodiment has a first
As shown in Figure (e), an N+ type buried layer (drain extraction region) 5 is provided on the surface of a P4'' type silicon substrate 1,
An N+ type VG layer 6 is provided on this buried layer 1Ii5 so as to be surrounded by the buried layer 5, and a P layer is further provided on the surface of this VG layer 6.
A molded guard ring 7 is provided, and a protrusion 4 is provided in a portion of the substrate located directly below the central opening of the guard link 7 so that the distance between the surface of the buried layer 5 and the bottom surface of the guard ring 7 is equal. It has a structure. Therefore, as described above, it is possible to reduce the on-resistance.
［発明の効果］
以上詳述した如く本発明によれば、従来と比ベオン抵抗
を減少できる高信頼性のＤＭｏＳトランジスタなどの半
導体装置及びその製造方法を提供できる。[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide a highly reliable semiconductor device such as a DMoS transistor, which can reduce the Veon resistance compared to the conventional device, and a method for manufacturing the same.
第１図（ａ）〜（ｅ＞は本発明の一実施例に係るＤ Ｍ
ＯＳ ＋−ランジスタの製造方法を工程順に示す断面
図、第２図は本発明に係るＤＭＯ８１〜ランジスタの要
旨を説明するための断面図である。
１・・・Ｐ４型のシリコン基板、２・・・ＳｉＯ２膜パ
ターン（マスク材）、３・・・溝、４・・・突起、５・
・・Ｎ＋型の埋込み層（ドレイン引出し’ａｌａ） 、
６・・・ＶＧ層（第１半導体層）、７・・・ガードリン
グ（第２半導体層）、８・・・バックグー１−領域、９
・・・ゲート電極、１０・・・Ｎ“型のソース領域、１
１・・・Ｎ＋型の拡散層、１２ａ、１２ｂ・・・Ｐ＋型
のソースバックゲートのコンタクト。FIGS. 1(a) to (e) show D M according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a method for manufacturing an OS+- transistor in order of steps, and FIG. 2 is a cross-sectional view for explaining the gist of the DMO 81 to transistor according to the present invention. DESCRIPTION OF SYMBOLS 1... P4 type silicon substrate, 2... SiO2 film pattern (mask material), 3... Groove, 4... Protrusion, 5...
・・N+ type buried layer (drain extraction 'ala),
6...VG layer (first semiconductor layer), 7...Guard ring (second semiconductor layer), 8...Background 1-region, 9
...Gate electrode, 10...N" type source region, 1
1...N+ type diffusion layer, 12a, 12b...P+ type source back gate contact.
Claims (2)
主面に設けられた第２導電型の高不純物濃度の埋込み層
と、この埋込み層に囲まれるように形成された第２導電
型の低不純物濃度の第１半導体層と、この第１半導体層
の表面に形成された耐圧補正用の第１導電型の第２半導
体層と、この第２半導体層に形成された半導体素子とか
らなり、前記半導体素子の領域直下に位置する前記半導
体基板部分が前記埋込み層側に突出し、前記埋込み層の
表面と前記第２半導体層の底面間の距離が全ての領域で
略一定になつていることを特徴とする半導体装置。(1) A semiconductor substrate of a first conductivity type, a buried layer with a high impurity concentration of a second conductivity type provided on one main surface of the semiconductor substrate, and a second conductivity type formed so as to be surrounded by the buried layer. a first semiconductor layer of a type having a low impurity concentration, a second semiconductor layer of a first conductivity type for breakdown voltage correction formed on the surface of the first semiconductor layer, and a semiconductor element formed in the second semiconductor layer. The semiconductor substrate portion located directly below the region of the semiconductor element protrudes toward the buried layer, and the distance between the surface of the buried layer and the bottom surface of the second semiconductor layer is approximately constant in all regions. A semiconductor device characterized by:
いて該マスク材の幅の１／２よりも浅い深さの溝を形成
するとともに、前記マスク材下の前記基板にマスク材側
に突出する突起を形成する工程と、前記溝から露出する
前記基板表面に第２導電型の高不純物濃度の埋込み層を
形成する工程と、気相成長を行ない前記溝内に第１導電
型の低不純物濃度の第１半導体層を形成する工程と、こ
の第１半導体層の表面に底面から前記埋込み層の表面ま
での距離が略一定の耐圧補正用の第１導電型の第２半導
体層を形成する工程と、これらの第２半導体層に半導体
素子を形成する工程とを具備することを特徴とする半導
体装置の製造方法。(2) Forming a groove with a depth shallower than 1/2 of the width of the mask material using a mask material on one principal surface of the semiconductor substrate of the first conductivity type, and forming a groove in the substrate below the mask material using the mask material. a step of forming a protrusion protruding toward the material side; a step of forming a buried layer of a second conductivity type with a high impurity concentration on the surface of the substrate exposed from the groove; and a step of forming a first conductivity type in the groove by vapor phase growth. forming a first semiconductor layer of a type with a low impurity concentration; and a second semiconductor of a first conductivity type for voltage proof correction with a substantially constant distance from the bottom surface to the surface of the buried layer on the surface of the first semiconductor layer. A method for manufacturing a semiconductor device, comprising the steps of forming a layer and forming a semiconductor element on these second semiconductor layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61027420A JPS62185372A (en) | 1986-02-10 | 1986-02-10 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61027420A JPS62185372A (en) | 1986-02-10 | 1986-02-10 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62185372A true JPS62185372A (en) | 1987-08-13 |
Family
ID=12220603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61027420A Pending JPS62185372A (en) | 1986-02-10 | 1986-02-10 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62185372A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0657940A3 (en) * | 1993-12-08 | 1995-12-06 | At & T Corp | Dielectrically isolated semiconductor devices having improved characteristics. |
-
1986
- 1986-02-10 JP JP61027420A patent/JPS62185372A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0657940A3 (en) * | 1993-12-08 | 1995-12-06 | At & T Corp | Dielectrically isolated semiconductor devices having improved characteristics. |
| US5557125A (en) * | 1993-12-08 | 1996-09-17 | Lucent Technologies Inc. | Dielectrically isolated semiconductor devices having improved characteristics |
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