JPS62179760A - Manufacture of photoelectric conversion device - Google Patents
Manufacture of photoelectric conversion deviceInfo
- Publication number
- JPS62179760A JPS62179760A JP61023282A JP2328286A JPS62179760A JP S62179760 A JPS62179760 A JP S62179760A JP 61023282 A JP61023282 A JP 61023282A JP 2328286 A JP2328286 A JP 2328286A JP S62179760 A JPS62179760 A JP S62179760A
- Authority
- JP
- Japan
- Prior art keywords
- region
- electrode
- photoelectric conversion
- self
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 29
- 239000004065 semiconductor Substances 0.000 claims description 19
- 230000000873 masking effect Effects 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052710 silicon Inorganic materials 0.000 abstract description 9
- 239000010703 silicon Substances 0.000 abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 210000004027 cell Anatomy 0.000 description 26
- 238000003384 imaging method Methods 0.000 description 12
- 230000010354 integration Effects 0.000 description 7
- 239000002184 metal Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- -1 5i3Na Inorganic materials 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 210000003850 cellular structure Anatomy 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14681—Bipolar transistor imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14806—Structural or functional details thereof
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Light Receiving Elements (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は光電変換装置の製造方法に係り、特に半導体ト
ランジスタの制御電極領域に絶縁膜を介して電極を形成
してなる光電変換装置の製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a photoelectric conversion device, and particularly to a method for manufacturing a photoelectric conversion device in which an electrode is formed in a control electrode region of a semiconductor transistor with an insulating film interposed therebetween. Regarding the method.
[従来技術]
従来、半導体撮像装置においては、その駆動回路部の高
集積性に比べて、単体デバイスであるセンサ部のセルサ
イズは充分に小さいとは言えなかった6例えば、256
KDRAMのセルサイズは通常70ILm2程度である
のに対して、画素数500X500の半導体撮像装置で
は200〜300p、m2 と数倍大きな値である。セ
ルサイズの増大はチップ面積を増大させ、とれ数を減少
させる。また通常、半導体撮像装置はデジタル型論理回
路装置に比べて、光学的特性、アナログ型特性が要求さ
れるために製造歩留が極端に低くなる。これらの理由か
ら、センサ部のチップ単価はDRAM等と比べて高くな
る。[Prior Art] Conventionally, in semiconductor imaging devices, the cell size of the sensor section, which is a single device, has not been sufficiently small compared to the high integration of the drive circuit section6.
The cell size of a KDRAM is usually about 70 ILm2, whereas in a semiconductor imaging device with a pixel count of 500x500, the cell size is several times larger, 200 to 300p, m2. Increasing the cell size increases the chip area and reduces the number of cracks. Further, since semiconductor imaging devices are generally required to have optical characteristics and analog characteristics compared to digital logic circuit devices, the manufacturing yield is extremely low. For these reasons, the chip unit price of the sensor section is higher than that of DRAM and the like.
セルサイズを縮小させる方法には大別して、寸法を比例
縮小させるスケールダウン法、及びセル構成要素を減少
させるセル改善方法の2つがある。前者の方法は、微細
加工技術の進歩に伴なって寸法が縮小しつつあるが、そ
の縮小化率は0゜88倍/年程度とゆるやかであり、急
激な縮小化は望めない、すなわち、スケールダウンによ
り、チップ面積が縮小され、とれ数は増加するものの、
製造歩留は制御性が悪化して低下し、結果として、良品
チップ数は、ある加工寸法でピークを持つことになる。There are two main methods for reducing cell size: a scale-down method that proportionally reduces dimensions, and a cell improvement method that reduces cell components. The dimensions of the former method are decreasing with the progress of microfabrication technology, but the rate of decrease is slow at about 0°88 times per year, and rapid reduction cannot be expected. Although the chip area is reduced and the number of defects increases due to
The manufacturing yield decreases due to poor controllability, and as a result, the number of non-defective chips reaches a peak at a certain processing size.
後者の方法は急激な縮小化が可能であり、例えば、RA
Mの場合は当初6〜8トランジスタで構成されていたも
のが現在1トランジスタと1キヤパシタまで簡略化され
ている。The latter method allows rapid downscaling, for example, RA
In the case of M, what was initially composed of 6 to 8 transistors has now been simplified to 1 transistor and 1 capacitor.
半導体撮像装置に於ても、後者のセル改善方法が有効で
あり、例えばCCD型半導体撮像装置(以下、CCD型
と記す)では、MO3O3型半導体撮像装置下、MOS
型と記す)の単純性、高集積性を更に改善したものにな
っており、キャリヤ蓄積部のアイソレーションは機械的
な構造によらず、電気的に形成されたポテンシャルで行
っている。また転送部においても、MOS型のソース、
ドレイン領域は不要であり、その分高集積化が可能であ
る。このようにCCD型はMOS型と比べて、高集積化
が可能であるものの、現状では製造歩留的に不利な点が
残されている。即ち、CCD型では転送部に欠陥が存在
すれば、相当するlライン全ての画素情報が影響を受け
てしまい、また情報の転送に配線金属でなく基板内部を
使用しているために基板の欠陥が許容できない等の欠点
があり、製造歩留が低下し、コスト上昇を引き起す、従
ってccn型とMOS型が半導体撮像装置の分野でしの
ぎを削っているのが現状である。これらの問題点を解決
し、高集積化を達成させる半導体撮像装置としては、特
開昭60−12759の光電変換装置を用いたものがあ
る。The latter cell improvement method is also effective for semiconductor imaging devices. For example, in a CCD type semiconductor imaging device (hereinafter referred to as CCD type), MOS
It has further improved the simplicity and high integration of the previous model (denoted as "type"), and the isolation of the carrier storage section is performed by an electrically formed potential without relying on a mechanical structure. In addition, in the transfer section, a MOS type source,
A drain region is not required, so higher integration is possible. As described above, although the CCD type allows higher integration than the MOS type, it currently has disadvantages in terms of manufacturing yield. In other words, in the CCD type, if there is a defect in the transfer section, the pixel information of all the corresponding L lines will be affected, and since the inside of the board is used for information transfer instead of the wiring metal, defects in the board will affect the information. However, the current situation is that the CCN type and the MOS type are competing with each other in the field of semiconductor imaging devices. As a semiconductor imaging device that solves these problems and achieves high integration, there is a device using a photoelectric conversion device disclosed in Japanese Patent Application Laid-Open No. 12759/1983.
第2図(a)はこの光電変換装置の平面図。FIG. 2(a) is a plan view of this photoelectric conversion device.
第2図(b)は平面図(a)のA−A ”縦断面図であ
る。FIG. 2(b) is a vertical sectional view taken along line A-A'' of the plan view (a).
第2図(a)及び(b)において、n+シリコン基板1
2上に光センサセルが配列されており、各光センサセル
はSiO2,5i3Na 、又はポリシリコン等により
成る素子分離領域13にょって隣りの光センサセルから
電気的に絶縁されている。In FIGS. 2(a) and (b), n+ silicon substrate 1
Photosensor cells are arranged on 2, and each photosensor cell is electrically insulated from adjacent photosensor cells by an element isolation region 13 made of SiO2, 5i3Na, polysilicon, or the like.
各光センサセルは次のような構成を有する。Each optical sensor cell has the following configuration.
エピタキシャル技術等で形成される不純物濃度の低いn
−領域14上にはpタイプの不純物(たとえばポロン等
)をドーピングすることでp領域15が形成され、p領
域15には不純物拡散技術又はイオン注入技術等によっ
てn十領域16が形成されている。p領域15及びn十
領域16は、各々バイポーラトランジスタのベース及び
エミッタ領域をなす。Low impurity concentration n formed by epitaxial technology etc.
- A p region 15 is formed on the region 14 by doping with a p-type impurity (for example, poron, etc.), and an n0 region 16 is formed in the p region 15 by impurity diffusion technology, ion implantation technology, etc. . P region 15 and n+ region 16 form the base and emitter regions of the bipolar transistor, respectively.
このように各領域が形成されたp領域15及び素子分離
領域13上には酸化膜17が形成され、この酸化膜17
上に所定の面積を有する電極18が形成される。この電
極18は、酸化膜17を挟んでp領域15と対向し、電
極18にパルス電圧を印加することで浮遊状態にされた
p領域15の電位を制御する。An oxide film 17 is formed on the p region 15 and the element isolation region 13 in which each region is formed in this way.
An electrode 18 having a predetermined area is formed thereon. This electrode 18 faces p-region 15 with oxide film 17 in between, and applies a pulse voltage to electrode 18 to control the potential of p-region 15 in a floating state.
その他に、n十領域16に接続されたエミッタ電極19
.エミッタ電極19から信号を外部へ読み出す配線20
、電極18に接続された配線21、n+シリコン基板1
2の裏面に不純物濃度の高いn中領域22.及びバイポ
ーラトランジスタのコレクタに電位を与えるための電極
23がそれぞれ形成されている。In addition, an emitter electrode 19 connected to the n+ region 16
.. Wiring 20 for reading signals from the emitter electrode 19 to the outside
, wiring 21 connected to electrode 18, n+ silicon substrate 1
On the back surface of 22.2, there is an n medium region 22.2 with high impurity concentration. and an electrode 23 for applying a potential to the collector of the bipolar transistor.
以下、上記光電変換装置の動作について述べる。The operation of the photoelectric conversion device will be described below.
光24が入射されると、半導体内に光量に対応した電子
−正孔対が発生し、電子は正電位にバイアスされたn+
シリコン基板12側から流れ出してしまうが、正孔はp
領域15に蓄積される(蓄積動作)、蓄積された正孔に
よってベース電位は上昇する。エミッタ領域をなすn十
領域16と、コレクタであるn+シリコン基板12との
間に電圧を印加し、また電極18に正の電圧を印加する
ことによって、更にベース電位を上昇させる。この電位
変化をコレクタ電流として読み出すことで、入射光量に
対応した電気信号を得ることができる(読み出し動作)
、また、p領域15に蓄積された電荷を除去するには、
エミッタ電極19を接地し、電極18に正電圧のパルス
を印加すればよい、この正電圧を印加することによって
、p領域15はn中領域16に対して順方向にバイアス
され、蓄積された電荷が除去される(リフレッシュ動作
)。以後上述の蓄積、読み出し、リフレッシュという各
動作が繰り返される。When the light 24 is incident, electron-hole pairs corresponding to the amount of light are generated in the semiconductor, and the electrons are biased to a positive potential.
The holes flow out from the silicon substrate 12 side, but the holes are p
The base potential increases due to the accumulated holes that are accumulated in the region 15 (accumulation operation). The base potential is further increased by applying a voltage between the n+ region 16, which is the emitter region, and the n+ silicon substrate 12, which is the collector, and by applying a positive voltage to the electrode 18. By reading this potential change as a collector current, it is possible to obtain an electrical signal corresponding to the amount of incident light (readout operation)
, and to remove the charges accumulated in the p region 15,
It is sufficient to ground the emitter electrode 19 and apply a positive voltage pulse to the electrode 18. By applying this positive voltage, the p region 15 is forward biased with respect to the n middle region 16, and the accumulated charge is is removed (refresh operation). Thereafter, the above-described storage, readout, and refresh operations are repeated.
[発明が解決しようとする問題点]
しかしながら、上記光電変換装置を用いた画素数500
X500の半導体撮像装置においても、セルサイズはほ
ぼ200JLm2程度と大きく、高集積化には不充分で
あった。[Problems to be solved by the invention] However, the number of pixels using the above photoelectric conversion device is 500.
Even in the X500 semiconductor imaging device, the cell size was as large as approximately 200 JLm2, which was insufficient for high integration.
[問題点を解決するための手段]
上記の問題点は、半導体トランジスタの制御電極領域に
絶縁膜を介して電極を形成してなる光電変換装置の製造
方法において、
半導体基板にフィールド絶縁膜を形成する工程と、この
フィールド絶縁膜をマスクとしてセルファライン法によ
って制御電極領域を形成する工程と、この制御電極領域
上に絶縁膜を形成し、その上に電極を形成する工程と、
前記フィールド絶縁膜及び電極をマスクとしてセルファ
ライン法によって主電極領域を形成する工程とを有する
本発明の光電変換装置の製造方法によって解決される。[Means for solving the problem] The above problem is solved by forming a field insulating film on a semiconductor substrate in a method for manufacturing a photoelectric conversion device in which an electrode is formed in a control electrode region of a semiconductor transistor via an insulating film. a step of forming a control electrode region by a self-line method using the field insulating film as a mask; a step of forming an insulating film on the control electrode region and forming an electrode thereon;
The problem is solved by the method for manufacturing a photoelectric conversion device of the present invention, which includes a step of forming a main electrode region by a self-line method using the field insulating film and the electrode as a mask.
[作用]
本発明の光電変換装置の製造方法はセルファライン法を
用いて、制御電極領域と主電極領域とを形成することに
より、制御電極領域と主電極領域の位置精度を高め、余
裕をほぼ取らずに各領域を作成することができるので、
センサセルのセルサイズを縮小させることができる。[Function] The method for manufacturing a photoelectric conversion device of the present invention uses the self-line method to form the control electrode region and the main electrode region, thereby increasing the positional accuracy of the control electrode region and the main electrode region, and almost reducing the margin. Since you can create each area without taking
The cell size of the sensor cell can be reduced.
[実施例] 以下、本発明の実施例を図面を用いて詳細に説明する。[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.
第1図は本発明の光電変換装置の製造方法による半導体
撮像装置のセンサセルの説明図であり、(a)は平面図
、(b)は平面図(a)のA−A ’断面図である。な
お本実施例において、半導体トランジスタはバイポーラ
トランジスタであり、制御電極領域はベース領域、主電
極領域はエミッタ領域である。FIG. 1 is an explanatory diagram of a sensor cell of a semiconductor imaging device according to the method of manufacturing a photoelectric conversion device of the present invention, in which (a) is a plan view, and (b) is a cross-sectional view taken along line A-A' in the plan view (a). . In this embodiment, the semiconductor transistor is a bipolar transistor, the control electrode region is the base region, and the main electrode region is the emitter region.
第1図において、1はセンサセルであり、CZN (1
00)10Ω−cmシリコン基板2上に、LOCO3法
により、厚さlILmのフィールド酸化膜3を形成する
。必要に応じてこのフィールド酸化膜3の下にn+チャ
ネルストッパ5を形成する。n+チャネルストッパ5は
隣接するセンサセルからの正孔の流入を防ぐ役割りを果
す0次いで、前記フィールド酸化!!3をマスクとして
、セルファライン法により、不純物濃度IQ+67cm
3 、拡散深さ0.81Lmのベース領域をなすp領域
4を形成する。ここでは、基本寸法(最小加工寸法)は
後述するコンタクトホール11の一辺の長さであり、ア
クティブエリアであるp領域4の大きさは、基本寸法の
3×2倍の大きさである。更に厚さ500人の酸化膜等
の絶縁膜7を形成し、その上に厚さ4000人のポリシ
リコンの電極8を形成する。この電極8はp領域4に対
するゲート電極となる。前記電極8は、一部フイールド
酸化膜3の上にのっており、アライメントすれに対して
マージンを有している。次いでフィールド酸化膜3及び
電極8をマスクとして、イオン注入セルファライン法に
より、不純物濃度1019/cm3 、拡散深さ0 、
3 pmのエミッタ領域をなすn中領域6を形成する。In FIG. 1, 1 is a sensor cell, and CZN (1
00) A field oxide film 3 having a thickness of lILm is formed on a 10 Ω-cm silicon substrate 2 by the LOCO3 method. If necessary, an n+ channel stopper 5 is formed under this field oxide film 3. The n+ channel stopper 5 serves to prevent the inflow of holes from adjacent sensor cells. ! 3 as a mask, impurity concentration IQ + 67 cm by self-line method.
3. Form a p region 4 forming a base region with a diffusion depth of 0.81 Lm. Here, the basic dimension (minimum processing dimension) is the length of one side of contact hole 11, which will be described later, and the size of p region 4, which is the active area, is 3×2 times the basic dimension. Furthermore, an insulating film 7 such as an oxide film with a thickness of 500 ml is formed, and an electrode 8 of polysilicon with a thickness of 4000 ml is formed thereon. This electrode 8 becomes a gate electrode for p region 4. The electrode 8 partially rests on the field oxide film 3 and has a margin for misalignment. Next, using the field oxide film 3 and the electrode 8 as a mask, the ion implantation self-line method is used to form an impurity with an impurity concentration of 1019/cm3 and a diffusion depth of 0.
An n medium region 6 forming a 3 pm emitter region is formed.
シリコン基板2 + P領域4及びn中領域6により、
縦型バイポーラトランジスタが形成される。hrcはt
ooo程度である。次いで厚さ7000人のPSG層間
絶縁膜9を形成し、コンタクトホールllを開口し、厚
さ8000人の配線金属10を前記n中領域6に電気的
に接続させる。Silicon substrate 2 + P region 4 and n medium region 6,
A vertical bipolar transistor is formed. hrc is t
It's about ooo. Next, a PSG interlayer insulating film 9 with a thickness of 7,000 thick is formed, a contact hole 11 is opened, and a wiring metal 10 with a thickness of 8,000 thick is electrically connected to the n medium region 6.
本実施例によれば、セル面積は基本寸法2ILmでは、
1010X8=801L となり、基本寸法2gmであ
る256KDRAMのセル面積70ルm2と比べても遜
色のない値である。また従来の半導体撮像装置のセル面
積の200〜300ILm2 と比べるとほぼl/3の
大きさである。また、電極8及び配線金属10を除いた
開口率は51%であり、充分使用に耐える値である。According to this embodiment, the cell area has a basic dimension of 2ILm.
1010×8=801 L, which is comparable to the cell area of 70 m2 of 256K DRAM whose basic dimensions are 2 gm. Also, compared to the cell area of 200 to 300 ILm2 of a conventional semiconductor imaging device, the size is approximately 1/3. Further, the aperture ratio excluding the electrode 8 and the wiring metal 10 is 51%, which is a value that is sufficient for use.
本実施例はフィールド酸化H3の形成にLOCO3法を
使用しているために、平坦であり、後工程の微細加工が
容易である。また、p領域4.n十領域6の青領域形成
に、前記フィールド酸化11j3のセルファラインを使
用しているため、アライメントエラーを生ぜず、従って
前記バイポーラトランジスタの特性はばらつかず、安定
なものとなる。また、n十領域6を電極8のセルファラ
インにより形成しているため、必要最小限な面積でアク
ティブエリアをなすP領域4を形成でき、且つ余分なゲ
ートエミッタ寄生容量を生じることはない、また前記電
極8と、ベース領域をなすp領域4のトランジスタ活性
領域とが非常に近く形成できるために、余分なベース抵
抗に起因する各種寄生効果を抑えることができる。また
。In this example, since the LOCO3 method is used to form the field oxide H3, the surface is flat and microfabrication in the post-process is easy. Also, p region 4. Since the self-line of the field oxide 11j3 is used to form the blue region of the n+ region 6, alignment errors do not occur, and therefore the characteristics of the bipolar transistor do not vary and are stable. Furthermore, since the n+ region 6 is formed by the self-alignment of the electrode 8, the P region 4 forming the active area can be formed with the minimum necessary area, and no extra gate emitter parasitic capacitance is generated. Since the electrode 8 and the transistor active region of the p region 4 forming the base region can be formed very close to each other, various parasitic effects caused by excessive base resistance can be suppressed. Also.
アクティブエリア、即ちp領域4を最小限で形成できる
ために、ベース、コレクタ容量を小さくすることが可能
であり、素子特性が向上する。Since the active area, that is, the p-region 4 can be formed with a minimum amount, the base and collector capacitances can be reduced, and the device characteristics are improved.
本発明の他の実施例として、フィールド絶縁膜3形成に
LOCO3法を用いず、従来のホトエツチング法を使用
しても良く、平坦化には不利なものの、LOCO3法に
おけるバーズビーク等が存在せず、高精度なベース面積
及びエミッタ面積を得ることができる。本実施例を用い
れば、更にトランジスタ特性がばらつかず安定になる。As another embodiment of the present invention, a conventional photoetching method may be used instead of the LOCO3 method to form the field insulating film 3, and although it is disadvantageous for planarization, there is no bird's beak etc. in the LOCO3 method. Highly accurate base area and emitter area can be obtained. If this embodiment is used, the transistor characteristics will be more stable without variations.
また、他の実施例として、シリコン基板2に他の基板、
例えばエピタキシャル基板等を使用して、NMOS等を
同時に形成可能ならしめることもできる。In addition, as another embodiment, another substrate may be added to the silicon substrate 2,
For example, by using an epitaxial substrate or the like, it is also possible to simultaneously form NMOS and the like.
また、更に開口率を向上させたい場合には。Also, if you want to further improve the aperture ratio.
前記実施例に於て、センサセルを基本寸法の5×4倍よ
りも大きくすれば良い。その際、p領域4は、なるべく
センサセルのコーナーに近い部分に配置した方が、開口
率に対しては有利である。In the above embodiment, the sensor cell may be made larger than 5×4 times the basic size. In this case, it is advantageous for the aperture ratio to arrange the p region 4 as close to the corner of the sensor cell as possible.
また前記電極8及び配線金属lOの材質はポリシリコン
At 、A1合金、高融点金属、シリサイド等、任意の
材質で良い。絶縁膜7に関しても、酸化膜、窒化膜等、
任意で良い。Further, the material of the electrode 8 and the wiring metal IO may be any material such as polysilicon At, A1 alloy, high melting point metal, silicide, etc. Regarding the insulating film 7, oxide film, nitride film, etc.
It's optional.
[発明の効果1
以上詳細に説明したように、本発明の光電変換装置の製
造方法によれば、セルファライン法ヲ用いて、制御電極
領域と主電極領域とを形成することにより、制御電極領
域と主電極領域の位置精度を高め、余裕をほぼ取らずに
各領域を作成することができるので、センサセルのセル
サイズを縮小させることができ、歩留りが良く、安価な
光電変換装置を提供することができる0本発明は高集積
化の要求される半導体撮像装置等に好適に用いられる。[Advantageous Effects of the Invention 1] As explained in detail above, according to the method for manufacturing a photoelectric conversion device of the present invention, the control electrode region and the main electrode region are formed by using the self-line method. To provide an inexpensive photoelectric conversion device which can reduce the cell size of a sensor cell, has a high yield, and can improve the positional accuracy of main electrode regions and create each region with almost no margin. INDUSTRIAL APPLICABILITY The present invention is suitably used in semiconductor imaging devices and the like that require high integration.
第1図は本発明の光電変換装置の製造方法による半導体
撮像装置のセンサセルの説明図であり、(&)は平面図
、(b)は平面図(&)のA−A ’断面図である。
第2図(a)は光電変換装置の平面図、第2図(b)は
平面図゛(a)のA−A ’縦断面図である。
1・・・・拳・センサセル
2・・・拳・・シリコン基板
3・・・・・・フィールド酸化膜
4・拳・・・・p領域
5・・・・―・n+チャネルストッパ
6・・・争・・n十領域
7・・・・・・絶縁膜
8・II+1・・−電極
代理人 弁理士 山 下 積 平
第1図
第2図FIG. 1 is an explanatory diagram of a sensor cell of a semiconductor imaging device according to the method of manufacturing a photoelectric conversion device of the present invention, (&) is a plan view, and (b) is a cross-sectional view taken along line A-A' of the plan view (&). . FIG. 2(a) is a plan view of the photoelectric conversion device, and FIG. 2(b) is a vertical sectional view taken along the line AA' of the plan view (a). 1...Fist/Sensor cell 2...Fist...Silicon substrate 3...Field oxide film 4/Fist...P region 5...N+ channel stopper 6... Dispute...N10 area 7...Insulating film 8, II+1...-Electrode agent Patent attorney Seki Yamashita Figure 1 Figure 2
Claims (1)
極を形成してなる光電変換装置の製造方法において、 半導体基板にフィールド絶縁膜を形成する工程と、この
フィールド絶縁膜をマスクとしてセルフアライン法によ
って制御電極領域を形成する工程と、この制御電極領域
上に絶縁膜を形成し、その上に電極を形成する工程と、
前記フィールド絶縁膜及び電極をマスクとしてセルフア
ライン法によって主電極領域を形成する工程とを有する
光電変換装置の製造方法。[Claims] A method for manufacturing a photoelectric conversion device in which an electrode is formed in a control electrode region of a semiconductor transistor via an insulating film, comprising: forming a field insulating film on a semiconductor substrate; and masking the field insulating film. a step of forming a control electrode region by a self-alignment method; a step of forming an insulating film on the control electrode region and forming an electrode thereon;
A method for manufacturing a photoelectric conversion device, comprising the step of forming a main electrode region by a self-alignment method using the field insulating film and the electrode as a mask.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61023282A JPS62179760A (en) | 1986-02-04 | 1986-02-04 | Manufacture of photoelectric conversion device |
DE3750300T DE3750300T2 (en) | 1986-02-04 | 1987-01-30 | Photoelectric conversion element and method for its production. |
EP87300853A EP0232148B1 (en) | 1986-02-04 | 1987-01-30 | Photoelectric converting device and method for producing the same |
AT87300853T ATE109593T1 (en) | 1986-02-04 | 1987-01-30 | PHOTOELECTRIC CONVERSION ELEMENT AND PROCESS FOR ITS MANUFACTURE. |
US07/411,219 US5089425A (en) | 1986-02-04 | 1989-09-22 | Photoelectric converting device having an electrode formed across an insulating layer on a control electrode and method for producing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61023282A JPS62179760A (en) | 1986-02-04 | 1986-02-04 | Manufacture of photoelectric conversion device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62179760A true JPS62179760A (en) | 1987-08-06 |
Family
ID=12106244
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61023282A Pending JPS62179760A (en) | 1986-02-04 | 1986-02-04 | Manufacture of photoelectric conversion device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62179760A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6471185A (en) * | 1987-09-11 | 1989-03-16 | Canon Kk | Photoelectric conversion device |
US5663097A (en) * | 1991-06-21 | 1997-09-02 | Canon Kabushiki Kaisha | Method of fabricating a semiconductor device having an insulating side wall |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59130467A (en) * | 1983-11-28 | 1984-07-27 | Hitachi Ltd | Solid-state image pickup device |
JPS6012759A (en) * | 1983-07-02 | 1985-01-23 | Tadahiro Omi | Photoelectric conversion device |
-
1986
- 1986-02-04 JP JP61023282A patent/JPS62179760A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6012759A (en) * | 1983-07-02 | 1985-01-23 | Tadahiro Omi | Photoelectric conversion device |
JPS59130467A (en) * | 1983-11-28 | 1984-07-27 | Hitachi Ltd | Solid-state image pickup device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6471185A (en) * | 1987-09-11 | 1989-03-16 | Canon Kk | Photoelectric conversion device |
US5663097A (en) * | 1991-06-21 | 1997-09-02 | Canon Kabushiki Kaisha | Method of fabricating a semiconductor device having an insulating side wall |
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