JPS62178532U - - Google Patents

Info

Publication number
JPS62178532U
JPS62178532U JP6664486U JP6664486U JPS62178532U JP S62178532 U JPS62178532 U JP S62178532U JP 6664486 U JP6664486 U JP 6664486U JP 6664486 U JP6664486 U JP 6664486U JP S62178532 U JPS62178532 U JP S62178532U
Authority
JP
Japan
Prior art keywords
island
semiconductor chip
lead frame
back surface
resin adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6664486U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6664486U priority Critical patent/JPS62178532U/ja
Publication of JPS62178532U publication Critical patent/JPS62178532U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図から第４図までは本考案の実施例を示し
、第１図はアイランドの平面図、第２図は第１図
の―線視断面図、第３図は第２実施例のアイ
ランドの平面図、第４図は第３図の―線視断
面図、第５図は従来技術におけるアイランドの平
面図、第６図は第５図の―視断面図である。 １，２２……アイランド、２，２３……リード
部、３，２１……半導体チツプ、４ａ，４ｂ……
ガス抜き通路、５……樹脂接着剤、２５……ガス
、２６……ボイド。 Figures 1 to 4 show embodiments of the present invention, with Figure 1 being a plan view of the island, Figure 2 being a sectional view taken along the line - - of Figure 1, and Figure 3 being the island of the second embodiment. FIG. 4 is a plan view of the island in FIG. 3, FIG. 5 is a plan view of the island in the prior art, and FIG. 6 is a cross-sectional view of FIG. 1, 22... Island, 2, 23... Lead portion, 3, 21... Semiconductor chip, 4a, 4b...
Gas vent passage, 5...resin adhesive, 25...gas, 26...void.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体チツプをダイボンデイングするリードフ
レームのアイランドに、前記半導体チツプの裏面
を接合するペースト状の樹脂接着剤から発生する
ガスを抜くガス抜き通路を、アイランドの表面に
沿つて又はアイランド裏面に通じるように形成し
たことを特徴とする半導体用リードフレーム。 A gas vent path is provided on an island of a lead frame to which a semiconductor chip is die-bonded, to remove gas generated from a paste-like resin adhesive bonding the back surface of the semiconductor chip, along the surface of the island or leading to the back surface of the island. A lead frame for semiconductors characterized by a formed structure.
JP6664486U 1986-04-30 1986-04-30 Pending JPS62178532U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6664486U JPS62178532U (en) 1986-04-30 1986-04-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6664486U JPS62178532U (en) 1986-04-30 1986-04-30

Publications (1)

Publication Number Publication Date
JPS62178532U true JPS62178532U (en) 1987-11-12

Family

ID=30904842

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6664486U Pending JPS62178532U (en) 1986-04-30 1986-04-30

Country Status (1)

Country Link
JP (1) JPS62178532U (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013229561A (en) * 2012-03-30 2013-11-07 Mitsubishi Materials Corp Method for manufacturing joined body, method for manufacturing power module, substrate for power module, and power module
JP2014022576A (en) * 2012-07-18 2014-02-03 Nichia Chem Ind Ltd Semiconductor element mounting member and semiconductor device
JP2016184756A (en) * 2016-06-10 2016-10-20 日亜化学工業株式会社 Semiconductor element mounting member and semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54122088A (en) * 1978-03-15 1979-09-21 Mitsubishi Electric Corp Metal substrate for semiconductor-pellet mounting
JPS5852863A (en) * 1981-09-25 1983-03-29 Toshiba Corp Lead frame for semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54122088A (en) * 1978-03-15 1979-09-21 Mitsubishi Electric Corp Metal substrate for semiconductor-pellet mounting
JPS5852863A (en) * 1981-09-25 1983-03-29 Toshiba Corp Lead frame for semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013229561A (en) * 2012-03-30 2013-11-07 Mitsubishi Materials Corp Method for manufacturing joined body, method for manufacturing power module, substrate for power module, and power module
JP2014022576A (en) * 2012-07-18 2014-02-03 Nichia Chem Ind Ltd Semiconductor element mounting member and semiconductor device
JP2016184756A (en) * 2016-06-10 2016-10-20 日亜化学工業株式会社 Semiconductor element mounting member and semiconductor device

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