JPH01107157U - - Google Patents
Info
- Publication number
- JPH01107157U JPH01107157U JP1988002975U JP297588U JPH01107157U JP H01107157 U JPH01107157 U JP H01107157U JP 1988002975 U JP1988002975 U JP 1988002975U JP 297588 U JP297588 U JP 297588U JP H01107157 U JPH01107157 U JP H01107157U
- Authority
- JP
- Japan
- Prior art keywords
- hole
- thin film
- metal thin
- resin
- wall surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 4
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 239000000463 material Substances 0.000 claims 2
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第1図はこの考案の一実施例の樹脂封止形半導
体装置の断面図、第2図は従来の樹脂封止形半導
体装置に用いられるリードフレームの平面図、第
3図は第2図のリードフレームのメツキ工程を示
す断面図、第4図は従来の樹脂封止形半導体装置
の断面図である。
図において、4はダイパツト、5は貫通穴、1
5は貫通穴の壁面、16は金属薄膜、18は半導
体素子、19は半田、21は樹脂である。なお、
各図中同一符号は同一、または相当部分を示す。
FIG. 1 is a sectional view of a resin-sealed semiconductor device according to an embodiment of the invention, FIG. 2 is a plan view of a lead frame used in a conventional resin-sealed semiconductor device, and FIG. FIG. 4 is a cross-sectional view showing a lead frame plating process, and FIG. 4 is a cross-sectional view of a conventional resin-sealed semiconductor device. In the figure, 4 is a die part, 5 is a through hole, 1
5 is a wall surface of the through hole, 16 is a metal thin film, 18 is a semiconductor element, 19 is solder, and 21 is a resin. In addition,
The same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
面を除き前記ダイパツドの少なくとも一主面に形
成された金属薄膜と、この金属薄膜上に固着材を
介して固着された半導体素子とを、樹脂で一体的
にモールドしてなり、前記貫通穴の壁面は前記金
属薄膜に比べて前記固着材に漏れにくいことを特
徴とする樹脂封止形半導体装置。 A die pad having a through hole, a metal thin film formed on at least one main surface of the die pad excluding the wall surface of the through hole, and a semiconductor element fixed onto the metal thin film via a bonding material are integrated with a resin. 1. A resin-sealed semiconductor device, wherein the wall surface of the through hole is less likely to leak into the adhesive material than the metal thin film.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988002975U JPH0810207Y2 (en) | 1988-01-12 | 1988-01-12 | Resin-sealed semiconductor device |
US07/227,332 US4942454A (en) | 1987-08-05 | 1988-08-02 | Resin sealed semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988002975U JPH0810207Y2 (en) | 1988-01-12 | 1988-01-12 | Resin-sealed semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01107157U true JPH01107157U (en) | 1989-07-19 |
JPH0810207Y2 JPH0810207Y2 (en) | 1996-03-27 |
Family
ID=31204206
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1988002975U Expired - Lifetime JPH0810207Y2 (en) | 1987-08-05 | 1988-01-12 | Resin-sealed semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0810207Y2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0369148A (en) * | 1989-08-08 | 1991-03-25 | Ibiden Co Ltd | Board for mounting electronic component |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63150953A (en) * | 1986-12-15 | 1988-06-23 | Sumitomo Electric Ind Ltd | Lead frame for semiconductor device |
-
1988
- 1988-01-12 JP JP1988002975U patent/JPH0810207Y2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63150953A (en) * | 1986-12-15 | 1988-06-23 | Sumitomo Electric Ind Ltd | Lead frame for semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0369148A (en) * | 1989-08-08 | 1991-03-25 | Ibiden Co Ltd | Board for mounting electronic component |
Also Published As
Publication number | Publication date |
---|---|
JPH0810207Y2 (en) | 1996-03-27 |