JPS62172731A - Etching method - Google Patents
Etching methodInfo
- Publication number
- JPS62172731A JPS62172731A JP1415286A JP1415286A JPS62172731A JP S62172731 A JPS62172731 A JP S62172731A JP 1415286 A JP1415286 A JP 1415286A JP 1415286 A JP1415286 A JP 1415286A JP S62172731 A JPS62172731 A JP S62172731A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- conductive layer
- type conductive
- power source
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005530 etching Methods 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 27
- 239000010703 silicon Substances 0.000 claims abstract description 27
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 abstract description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 abstract description 8
- 239000010453 quartz Substances 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 229910052697 platinum Inorganic materials 0.000 abstract description 4
- 238000007654 immersion Methods 0.000 abstract 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 13
- 230000035945 sensitivity Effects 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 102100032435 BTB/POZ domain-containing adapter for CUL3-mediated RhoA degradation protein 2 Human genes 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 101000798415 Homo sapiens BTB/POZ domain-containing adapter for CUL3-mediated RhoA degradation protein 2 Proteins 0.000 description 1
- HEMINMLPKZELPP-UHFFFAOYSA-N Phosdiphen Chemical compound C=1C=C(Cl)C=C(Cl)C=1OP(=O)(OCC)OC1=CC=C(Cl)C=C1Cl HEMINMLPKZELPP-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002848 electrochemical method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- NBJBFKVCPBJQMR-APKOLTMOSA-N nff 1 Chemical compound C([C@H](NC(=O)[C@H](CCC(N)=O)NC(=O)[C@H](CCC(N)=O)NC(=O)[C@@H]1CCCN1C(=O)[C@H](CCCCN)NC(=O)[C@@H]1CCCN1C(=O)CC=1C2=CC=C(C=C2OC(=O)C=1)OC)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)NCC(=O)N[C@@H](CC(C)C)C(=O)N[C@@H](CCCCNC=1C(=CC(=CC=1)[N+]([O-])=O)[N+]([O-])=O)C(=O)NCC(O)=O)C1=CC=CC=C1 NBJBFKVCPBJQMR-APKOLTMOSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Pressure Sensors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はエツチング方法に関し、特にＮ型導電層とＰ型
導電層とからなるシリコンウェーハ〜のエツチング方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an etching method, and more particularly to a method for etching a silicon wafer comprising an N-type conductive layer and a P-type conductive layer.
従来、シリコンダイアフラムを形成するとき、水酸化カ
リウム溶液（ＫＯＨ，以下ＫＯＨと記す）やエチレンジ
アミン・ピロカテコール溶液（ＥＤＰ１以下ＥＤＰ
と記す）のような異方性エツチング液を用いて、エツチ
ング速度を制御することによりダイアフラムの厚さを制
御してい几。Conventionally, when forming a silicon diaphragm, potassium hydroxide solution (KOH, hereinafter referred to as KOH) or ethylenediamine-pyrocatechol solution (EDP1 or less) was used.
The thickness of the diaphragm is controlled by controlling the etching rate using an anisotropic etching solution such as
あるいは、高濃度ホウ素含有層でのエツチング速度の低
下を利用したり、ＰＮ接合ウェーノーを用い友電気化学
的なエツチング方法によりダイアフラム厚の制御が行わ
れていた。Alternatively, the diaphragm thickness has been controlled by utilizing the reduction in etching rate in a layer containing high concentration boron, or by electrochemical etching using a PN junction wafer.
例えば、アイ・イー・イー・イー・トランザクションズ
・オン・エレクトロン・デバイス（Ｉ ＥＥＥＴＲＡＮ
ＳＡＣＴＩＯＮ８ＯＮＥＬＥＣＴＲＯＮＤＥＶＩＣＥ−
８）第ＥＤ−３０巻、１９８３年７月、第７号に記載さ
れている報告もその一例である。For example, IEE TRANSACTIONS ON ELECTRON DEVICES (IEEETRAN)
SACTION8ONE ELECTRON DEVICE-
8) The report described in Vol. ED-30, July 1983, No. 7 is also an example.
シリコンダイアフラムは圧力センサや発振子に使われて
いる構造体である。圧力センナの圧力感度はダイアフラ
ムの厚さに密接に関連している６第２図は圧力センサの
断面図である。Silicon diaphragms are structures used in pressure sensors and oscillators. The pressure sensitivity of a pressure sensor is closely related to the thickness of the diaphragm.6 FIG. 2 is a cross-sectional view of the pressure sensor.
第２図に示すように、シリコンウェーハ７のダイアフラ
ム部の端部に拡散抵抗８を形成し、圧力を印加した時の
抵抗値変化で圧力の大きさを検出するものである。圧力
感度はダイアフラムの厚さの２乗に反比例する。即ち、
厚さが２倍になると感度は１／４に低下する。As shown in FIG. 2, a diffused resistor 8 is formed at the end of the diaphragm portion of the silicon wafer 7, and the magnitude of the pressure is detected by the change in resistance value when pressure is applied. Pressure sensitivity is inversely proportional to the square of the diaphragm thickness. That is,
When the thickness is doubled, the sensitivity decreases to 1/4.
従って、圧力感度ばらつきの小さい圧力センサを製造す
る為には、ダイアフラムの厚さを正確に制御しなければ
ならない。発振子の場合でも、同様に振動周波数を均一
にするために、ダイアフラムの厚さを正確に制御する必
要がある。Therefore, in order to manufacture a pressure sensor with small variations in pressure sensitivity, the thickness of the diaphragm must be accurately controlled. Similarly, in the case of an oscillator, it is necessary to precisely control the thickness of the diaphragm in order to make the vibration frequency uniform.
高濃度ホウ素含有層によるエツチング制御法は、５Ｘ１
０ ｃｍ 以上のホウ素濃度が必要であシ、その様な
高濃度の不純物を含むシリコンダイアフラム表面に、圧
力を検出する為の拡散抵抗を形成することは困難である
。The etching control method using a high-concentration boron-containing layer is 5X1
A boron concentration of 0 cm or more is required, and it is difficult to form a diffusion resistance for detecting pressure on the surface of a silicon diaphragm containing such a high concentration of impurities.
ＰＮ接合ウェーハを用いた電気化学的なエツチング方法
は低不純物濃度のＰＮ接合ウェーハな使えるので、シリ
コンダイアフラム表面に拡散抵抗や集積回路素子を形成
することができ、圧力センナの製造に適している。Since the electrochemical etching method using a PN junction wafer can be used with a PN junction wafer with a low impurity concentration, it is possible to form diffused resistors and integrated circuit elements on the surface of a silicon diaphragm, and is suitable for manufacturing pressure sensors.
第３図は従来のエツチング方法の一例のエツチング装置
の断面図である。FIG. 3 is a sectional view of an etching apparatus as an example of a conventional etching method.
第３図に示すように、石英ビー力１に異方性を有するエ
ツチング液２、例えば、ＫＯＨ，ＥＤＰ 。As shown in FIG. 3, an etching solution 2 having anisotropy in the quartz bead force 1, such as KOH or EDP.
ヒドラジン等を八れ、ヒータ３で９０〜１２０℃に加熱
する。白金電極４を定電圧電源９の陰極に接続し、エツ
チング液２の電位を基準電位に固定する。ＰＮ接合シリ
コンウエーノＳ５のエツチング面を所要のマスク１０で
覆い、Ｎ型導電層を定電圧電源９の陽極に接続する。Add hydrazine, etc., and heat to 90 to 120°C using heater 3. The platinum electrode 4 is connected to the cathode of a constant voltage power source 9, and the potential of the etching solution 2 is fixed at a reference potential. The etched surface of the PN junction silicon wafer S5 is covered with a required mask 10, and the N-type conductive layer is connected to the anode of the constant voltage power supply 9.
Ｐ型導電層が異方性エツチングされＮ型導電層に達する
と、陽極酸化によシＮ型導電層の表面に酸化膜が形成さ
れエツチングが停止する。しかしながら、エツチング停
止はウェーハ内の全チップで同時に起らず、Ｐ型導電層
のエツチングが速く進むウェーハ周辺部から起る。When the P-type conductive layer is anisotropically etched and reaches the N-type conductive layer, an oxide film is formed on the surface of the N-type conductive layer by anodic oxidation, and the etching is stopped. However, the etching stop does not occur simultaneously on all chips within the wafer, but occurs from the periphery of the wafer where the P-type conductive layer is etched faster.
そこで、エツチング停止が周辺部から中心部に向って同
心円状に進むにしたがって、Ｎ型導電層の露出するチッ
プ数が減少し、電流が少数チップに集中する様になる。Therefore, as the etching stop progresses concentrically from the periphery toward the center, the number of exposed chips of the N-type conductive layer decreases, and the current concentrates on a small number of chips.
上述した従来のエツチング方法は、ウェーハ中心部にお
いては、Ｐ型導電層でも陽極酸化が起シエッチングが停
止する。従って、ウェーハ中心部の方がダイアフラム厚
が厚くなり感度が低下するという問題点がある。In the conventional etching method described above, anodic oxidation occurs even in the P-type conductive layer at the center of the wafer, and etching stops. Therefore, there is a problem that the diaphragm is thicker at the center of the wafer and the sensitivity is lowered.
本発明の目的は、シリコンウェーハの全面でダイアフラ
ムの厚さを均一にできるエツチング方法を提供すること
にある。An object of the present invention is to provide an etching method that can make the thickness of a diaphragm uniform over the entire surface of a silicon wafer.
本発明のエツチング方法は、Ｎ型導電層とＰ型導電層と
からなるシリコンウェーハの前記Ｎｆｆ１導電層に正極
性の直流電圧を印加して前記Ｐ型導電層をエッチングに
より除去する電気化学的なエツチング方法において、前
記Ｐ型導電層のエツチングが終了する所定時間前から前
記正極性の直流電圧の値を順次低下させるように構成さ
れる。The etching method of the present invention is an electrochemical method in which a positive DC voltage is applied to the Nff1 conductive layer of a silicon wafer consisting of an N-type conductive layer and a P-type conductive layer to remove the P-type conductive layer by etching. The etching method is configured such that the value of the positive DC voltage is sequentially lowered from a predetermined time before the etching of the P-type conductive layer is completed.
印加電圧を定電圧ではなく、Ｐ型導電層のエツチングが
終了する所定時間前から順次減少させることによシ、ウ
ェーハ中心部の少数チップへの電流集中をなくシ、ウェ
ーハ面内で厚さの均一なシリコンダイアフラムが得られ
る。By decreasing the applied voltage sequentially from a predetermined time before the etching of the P-type conductive layer ends, instead of using a constant voltage, current concentration on a small number of chips at the center of the wafer can be eliminated, and the thickness can be reduced within the wafer surface. A uniform silicon diaphragm is obtained.
次に１本発明の実施例について図面を参照して説明する
。Next, an embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例のエツチング装置の断面図で
ある。FIG. 1 is a sectional view of an etching apparatus according to an embodiment of the present invention.
第１図において、石英と一カ１はエツチング液に侵され
ない様に高純度の透明石英がよい。エツチング液２はシ
リコンに対して異方性のあるＫＯＨやＥＤＰ やヒド
ラジンを用いる。ヒータ３でエツチング液を９０〜１８
０（沸点）℃に加熱する。白金電極４を可変電源６の陰
極側に接続し、エツチング液２を基準電位に固定する。In FIG. 1, the quartz plate 1 is preferably made of high-purity transparent quartz so as not to be affected by the etching solution. As the etching liquid 2, KOH, EDP, or hydrazine, which is anisotropic with respect to silicon, is used. Heater 3 heats the etching solution to 90-18
Heat to 0 (boiling point) °C. A platinum electrode 4 is connected to the cathode side of a variable power source 6, and the etching solution 2 is fixed at a reference potential.
ＰＮ接合シリコンウェーハ５はＮ型導電層側を可変電源
６の陽極側に接続する。The N-type conductive layer side of the PN junction silicon wafer 5 is connected to the anode side of the variable power source 6.
この時、ＰＮ接合シリコンウェーハ５のエツチング面は
所定のマスクｌＯで覆っておく。エツチング液２がＫＯ
Ｈの場合、マスク１０は窒化シリコン膜や金、クロムの
金属薄膜が必要であるが、ＥＤＰ やヒドラジンの場合
は酸化膜でよい。At this time, the etched surface of the PN junction silicon wafer 5 is covered with a predetermined mask IO. Etching solution 2 is KO
In the case of H, the mask 10 needs to be a silicon nitride film or a metal thin film of gold or chromium, but in the case of EDP or hydrazine, an oxide film may be used.
可変電源６から５■の電圧を印加しながら、エツチング
液に浸すと、Ｐ湯導電層のダイアフラム部が異方性エツ
チングされる。例えば、（１００）面シリコンウェーハ
を用いるとダイアフラム支持部の傾斜は５４．１と々る
。エツチングがＮ型導電層に達すると、ウェーハの外周
部から順にエツチングが停止する。When immersed in an etching solution while applying a voltage of 5 cm from the variable power source 6, the diaphragm portion of the P-water conductive layer is anisotropically etched. For example, when a (100) plane silicon wafer is used, the slope of the diaphragm support is 54.1. When the etching reaches the N-type conductive layer, the etching stops sequentially from the outer periphery of the wafer.
この時、可変電源６の出力電圧を時間と共に低下させる
。この方法は、例えば、プログラム可能電源を用い予め
電圧低下速度をプログラムで設定しておけばよい。At this time, the output voltage of the variable power supply 6 is lowered over time. In this method, for example, a programmable power supply may be used and the voltage drop rate may be set in advance by a program.
電圧の低下速度はシリコンウェーハ・のＰＪＩ導電層及
びＮ型導電層の比抵抗や厚さ、ダイアフラムの寸法等に
より異なる。−例を示すと、Ｐ湯導電層が３００関、厚
さ３５０μｍ、 Ｎ型導電層が３Ω個、厚さ２０μｍで
ダイアフラムの寸法が１−の時、電圧の低下速度は０．
２〜０．６Ｖ／−が適当である。The speed at which the voltage decreases varies depending on the specific resistance and thickness of the PJI conductive layer and the N-type conductive layer of the silicon wafer, the dimensions of the diaphragm, etc. - To give an example, when the P-type conductive layer is 300mm thick and 350μm thick, the N-type conductive layer is 3Ω and 20μm thick, and the diaphragm size is 1-, the rate of voltage drop is 0.
2 to 0.6 V/- is suitable.
エツチングはウェーハ外周部から中心部に向って同心円
状に進むが、電源電圧を低下させることにより少数チッ
プへの電流集中がなくなり、ウェーハ面内で均一な厚さ
を有するダイアフラムが得られる。この場合、電圧は最
終的に３Ｖｔで低下させる。Etching progresses concentrically from the outer periphery of the wafer toward the center, but by lowering the power supply voltage, current concentration on a small number of chips is eliminated, and a diaphragm having a uniform thickness within the wafer surface can be obtained. In this case, the voltage is finally lowered to 3Vt.
電圧を低下させる他の方法は、可変電源６の陽極とＰＮ
接合シリコンウェーハとの間に電流計を挿入し、電源電
流を測定しながら、計測値を可変電源６０制御部に入力
し計測値に合せて電源電圧を低下させる方式である。こ
の場合、制御はプログラムで設定することができる。Another way to reduce the voltage is to connect the anode of the variable power supply 6 and the PN
In this method, an ammeter is inserted between the bonded silicon wafer and the power supply current is measured, and the measured value is input to the control section of the variable power supply 60, and the power supply voltage is lowered in accordance with the measured value. In this case, the control can be set programmatically.
なお、電圧の低下速度は実施例に示した値に限定される
ものではなく、ＰＮ接合シリコンウェーハの特性やエツ
チング条件によ）他の値に設定してよい。又、初期の印
加電圧や最終の電圧も上記した実施例の値に限定される
ものではない。Note that the rate of voltage decrease is not limited to the values shown in the examples, and may be set to other values depending on the characteristics of the PN junction silicon wafer and etching conditions. Further, the initial applied voltage and final voltage are not limited to the values in the above embodiments.
以上説明したように本発明のエツチング方法によれば、
製造したシリコンダイアスラムの厚さがウェーハ面内で
均一となシ、従来の方法によるダイアフラムに比べてば
らつきが極めて改善されるので、シリコン圧力センナの
感度ばらつきを低減できるという効果がある。As explained above, according to the etching method of the present invention,
Since the thickness of the manufactured silicon diaphragm is uniform within the wafer surface, variations in variation are significantly improved compared to diaphragms produced by conventional methods, which has the effect of reducing variations in sensitivity of silicon pressure sensors.
第１図は本発明の一実施例のエツチング装置の断面図、
８２図は圧力センサの断面図、第３図は従来のエツチン
グ方法の一例のエツチング装置の断面図である。
１・・・・・・石英ピー力、２・・・・・・エツチング
液、３・・・・・・ヒータ、４・・・・・・白金電極、
５・・・・・・ＰＮ接合シリコンウェーハ、６・・・・
・・可変電源、７・・・・・・シリコンウェーハ、８・
・・・・・拡散抵抗、９・・・・・・定電圧電源。
１石突ヒ゛′−力 ２エヅナンブ）絖 ３ヒータ４伯
金を極 左 ＰＮ判ト合シリフ〉つ１−ハロ ゛司−変
電ジ原
沼１０
ｆＺ図FIG. 1 is a sectional view of an etching apparatus according to an embodiment of the present invention;
FIG. 82 is a sectional view of a pressure sensor, and FIG. 3 is a sectional view of an etching device as an example of a conventional etching method. 1...Quartz pea force, 2...Etching liquid, 3...Heater, 4...Platinum electrode,
5...PN junction silicon wafer, 6...
...Variable power supply, 7...Silicon wafer, 8.
...Diffused resistance, 9... Constant voltage power supply. 1st stone thrust force 2nd number) wire 3 heater 4 metal plate left PN size combined series 1-halo ゛゛ji-substation Jigenuma 10 fZ diagram
Claims (1)
前記Ｎ型導電層に正極性の直流電圧を印加して前記Ｐ型
導電層をエッチングにより除去する電気化学的なエッチ
ング方法において、前記Ｐ型導電層のエッチングが終了
する所定時間前から前記正極性の直流電圧の値を順次低
下させることを特徴とするエッチング方法。In an electrochemical etching method, the P-type conductive layer is removed by etching by applying a positive DC voltage to the N-type conductive layer of a silicon wafer consisting of an N-type conductive layer and a P-type conductive layer. An etching method characterized in that the value of the positive DC voltage is sequentially lowered from a predetermined time period before the etching of the mold conductive layer is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1415286A JPS62172731A (en) | 1986-01-24 | 1986-01-24 | Etching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1415286A JPS62172731A (en) | 1986-01-24 | 1986-01-24 | Etching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62172731A true JPS62172731A (en) | 1987-07-29 |
| JPH0528898B2 JPH0528898B2 (en) | 1993-04-27 |
Family
ID=11853176
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1415286A Granted JPS62172731A (en) | 1986-01-24 | 1986-01-24 | Etching method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62172731A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02290524A (en) * | 1989-01-30 | 1990-11-30 | Dresser Ind Inc | Semiconductor wafer, forming method of the same, transducer and manufacturing method of the same |
| US7749868B2 (en) | 2005-05-18 | 2010-07-06 | Panasonic Electric Works Co., Ltd. | Process of forming a curved profile on a semiconductor substrate |
| US8313632B2 (en) | 2005-05-18 | 2012-11-20 | Panasonic Corporation | Process of making an optical lens |
-
1986
- 1986-01-24 JP JP1415286A patent/JPS62172731A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02290524A (en) * | 1989-01-30 | 1990-11-30 | Dresser Ind Inc | Semiconductor wafer, forming method of the same, transducer and manufacturing method of the same |
| US7749868B2 (en) | 2005-05-18 | 2010-07-06 | Panasonic Electric Works Co., Ltd. | Process of forming a curved profile on a semiconductor substrate |
| US8313632B2 (en) | 2005-05-18 | 2012-11-20 | Panasonic Corporation | Process of making an optical lens |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0528898B2 (en) | 1993-04-27 |
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