JPS6261374A - Manufacture of silicon diaphragm - Google Patents
Manufacture of silicon diaphragmInfo
- Publication number
- JPS6261374A JPS6261374A JP20236885A JP20236885A JPS6261374A JP S6261374 A JPS6261374 A JP S6261374A JP 20236885 A JP20236885 A JP 20236885A JP 20236885 A JP20236885 A JP 20236885A JP S6261374 A JPS6261374 A JP S6261374A
- Authority
- JP
- Japan
- Prior art keywords
- diaphragm
- type
- layer
- silicon
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/07—Integrating an electronic processing unit with a micromechanical structure
- B81C2203/0707—Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
- B81C2203/0735—Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Weting (AREA)
- Pressure Sensors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はシリコンダイアフラムの形成方法に関し、特に
電気化学法を用いるシリコンダイアフラムの形成方法に
関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of forming a silicon diaphragm, and more particularly to a method of forming a silicon diaphragm using an electrochemical method.
従来、シリコンダイアフラムの形成にはエツチング時間
制御法、高濃度ボロン層によるエツチング停止法、電気
化学エツチング法などが用いられていた。例えば電気化
学エツチング法ではＰＮ接合基板のＮ型層に正極性電圧
を印加し、Ｐ型層のみをエツチングにより除去すること
により行われる（アイ・イー・イー・イー トランプク
シ、ンズオン エレクトロン デパイシズ（ＩＥＥＥ
ＴＲＡＮＳ−ＡＣＴＩＯＮＳ ＯＮ ＥＬＥＣＴＲＯＮ
ＤＥＶＩＣＥＳ、ＶＯＬ、ＥＤ−３０，７ｆＬ７ 。Conventionally, methods such as an etching time control method, an etching stop method using a high concentration boron layer, and an electrochemical etching method have been used to form a silicon diaphragm. For example, in the electrochemical etching method, a positive voltage is applied to the N-type layer of a PN junction substrate, and only the P-type layer is removed by etching.
TRANS-ACTIONS ON ELECTRON
DEVICES, VOL, ED-30, 7fL7.
ＪＵＬＹ １９８３））。JULY 1983)).
第２図に電気化学エツチング法に用いられた圧力センサ
用のＰＮ接合ウェー・−の構造断面を示す。FIG. 2 shows a structural cross section of a PN junction wafer for a pressure sensor used in the electrochemical etching method.
図において、Ｐ型基板１は面方位（１００）で比抵抗３
Ω・副、厚さ１７５μｍである。Ｎ型層２は比抵抗２３
Ω・α、厚さ２８．３μｍである。ピエゾ抵抗３はＰ型
でイオン注入や拡散技術により形成され、このピエゾ抵
抗３の直下のＰ型基板１の部分をエツチングにより薄膜
化することによシ行われる。In the figure, the P-type substrate 1 has a specific resistance of 3 in plane orientation (100).
The thickness is 175 μm. N-type layer 2 has a specific resistance of 23
Ω·α, thickness 28.3 μm. The piezoresistor 3 is of P type and is formed by ion implantation or diffusion techniques, and is etched by thinning the portion of the P type substrate 1 directly under the piezoresistor 3 by etching.
第３図にこの方法に使用するエツチング装置の模式図を
示す。図において、石英ビー力４に工。FIG. 3 shows a schematic diagram of the etching apparatus used in this method. In the figure, the quartz bead force is 4.
チング液５を満しζヒータ６で液５を加熱する。Fill with a quenching liquid 5 and heat the liquid 5 with a ζ heater 6.
エツチング液５はエチレンジアミンにピロカテコールと
水を加えたものである。シリコンウニ・・−のＮ型層７
０表面に金属膜８を蒸着し、この金属膜８を電極として
電源９の正電圧を接続する。この状態でシリコンウェノ
・−のＰ型基板１０をエッチングしてダイアフラムを形
成するものである。他方の電極に用いる白金を極１１は
電流計１２を介して接地されている。なお、エツチング
液の液温は１１５℃で印加筒、圧は０，６ｖである。Ｐ
型基板１０がエツチングされ、Ｎ型層７に達するとエツ
チングが自動的に停止して均一な膜厚を有するダイアフ
ラムが形成される。Etching solution 5 is a mixture of ethylenediamine, pyrocatechol, and water. N-type layer 7 of silicon sea urchin...
A metal film 8 is deposited on the 0 surface, and a positive voltage of a power source 9 is connected using this metal film 8 as an electrode. In this state, the silicon wafer P-type substrate 10 is etched to form a diaphragm. The platinum electrode 11 used as the other electrode is grounded via an ammeter 12. The temperature of the etching solution was 115°C, the pressure was 0.6V. P
The mold substrate 10 is etched, and when the N-type layer 7 is reached, the etching is automatically stopped and a diaphragm having a uniform thickness is formed.
ところで、ダイアフラム型シリコン圧力センサの感度は
ダイアフラム部分の膜厚の２乗に反比例する。従って感
度ばらつきの小さい圧力センサを製造するためには膜厚
を正確に制御しなくてはならない。電気化学エツチング
法によれは膜厚はエピタキシャル層の厚さのばらつき内
に制御できる。Incidentally, the sensitivity of a diaphragm type silicon pressure sensor is inversely proportional to the square of the film thickness of the diaphragm portion. Therefore, in order to manufacture a pressure sensor with small sensitivity variations, the film thickness must be accurately controlled. By electrochemical etching, the film thickness can be controlled within the variation of the epitaxial layer thickness.
しかしながらエピタキシャル層の厚さはゾロセス工程中
の熱処理により不純物が移動して変化するという問題が
ある。例えばピエゾ抵抗はゾロン等のイオンを注入し、
熱拡散により形成するが、この熱処理中に不純物が再分
布する。不純物の分布は不純物濃度と温度とにより決ま
り、例えば温度が１１４０℃の時シリコン中でメロンの
拡散係数は２Ｘ１０’Ｃμ杼〕でリンの拡散係数も２Ｘ
１０’〔ルＶｎ〕と同程度であるので、高濃度領域側か
ら低濃度領域側に不純物が移動する。第２図に示した例
の場合ではＰ型基板１の方がＮ型層２より高濃度である
のでゾロンがＮ型層２側に移動し、実質のエピタキシャ
ル層は薄くなる。従ってダイアフラムを電気化学法によ
りエツチングしたと趣、膜厚が設計値より薄くなる。ま
た、ピエゾ抵抗形成時以外にも熱工程が続けられる場合
がある。例えば集積化圧力センサでは信号処理回路がダ
イアフラム周辺部に形成され、ｎチャネルＭＯ８集積回
路を集積化する場合はＮ型エピタキシャル層に深いＰ形
つェルを形成する必要があるが、この時１２００℃程度
の高温が加えられるので不純物の移動によりエピタキシ
ャル層は薄くなる。However, there is a problem in that the thickness of the epitaxial layer changes due to movement of impurities due to heat treatment during the Zorocess process. For example, piezoresistors are made by implanting ions such as zolon,
It is formed by thermal diffusion, and impurities are redistributed during this heat treatment. The distribution of impurities is determined by the impurity concentration and temperature. For example, when the temperature is 1140°C, the diffusion coefficient of melon in silicon is 2X10'Cμ, and the diffusion coefficient of phosphorus is also 2X.
10' [Vn], impurities move from the high concentration region side to the low concentration region side. In the example shown in FIG. 2, since the concentration of P-type substrate 1 is higher than that of N-type layer 2, zolon moves toward N-type layer 2, and the actual epitaxial layer becomes thinner. Therefore, if the diaphragm is etched by an electrochemical method, the film thickness will be thinner than the designed value. Further, the thermal process may be continued even when piezoresistors are being formed. For example, in an integrated pressure sensor, the signal processing circuit is formed around the diaphragm, and when integrating an n-channel MO8 integrated circuit, it is necessary to form a deep P-type well in the N-type epitaxial layer. Since a high temperature of about °C is applied, the epitaxial layer becomes thinner due to the movement of impurities.
本発明の目的はこの問題点を解決ｌ〜たエピタキシャル
基板を用いてシリコンダイアフラムを形成する方法を提
供することにある。An object of the present invention is to provide a method for forming a silicon diaphragm using an epitaxial substrate that solves these problems.
本発明は、電気化学法によってダイアフラムを形成する
工程において、ＰＮ接合シリコン基板の各層の不純物濃
度を同一としたシリコンダイアフラムの形成方法でおる
。The present invention is a method of forming a silicon diaphragm in which the impurity concentration of each layer of a PN junction silicon substrate is made the same in the step of forming the diaphragm by an electrochemical method.
Ｐ型シリコン基板のゾロン濃度とＮ型エピタキシャル層
のリン濃度とを同一とすることにより、約１１４０℃の
温度で熱処理しても互いの不純物拡散が打消し合い実質
的エピタキシャル層の厚さが変ワラないシリコンダイア
フラムが得られる。By making the zolon concentration of the P-type silicon substrate and the phosphorus concentration of the N-type epitaxial layer the same, even when heat-treated at a temperature of about 1140°C, the impurity diffusion cancels each other out, and the actual thickness of the epitaxial layer changes. A silicon diaphragm with no cracks can be obtained.
以下に第１図に示す実施例によりシリコンダイアフラム
の形成方法を示す。第１図は集積化圧力センサの構造断
面図である。本発明に用いるＰＮＮ接合ウニ・−のＰ型
基板１は面方位（ｉｏｏ）で不純物濃度が例えばＩ Ｘ
１０ ’ ”ｃｍ−’とする。Ｎ型層２はエピタキシ
ャル層で不純物濃度をＰ型基板と同じく１×１０ｃＷＩ
とする。ピエゾ抵抗３はゾロンのイオン注入や熱拡
散により形成される。該圧力センサの周辺厚肉部にはＰ
型ウェル１３が形成され、ｎチャネルＭＯ８ＩＣや・ｔ
イボーラＩＣを集積化して信号処理に用いられるもので
ある。このＰＮＮ接合ウニノーは電気化学エツチング法
にて従来同様に処理してＰ型基板１をエツチングすると
、エツチングがＮ型層２に達したときに自動的にエツチ
ングが停止してダイアプラムが形成される。A method of forming a silicon diaphragm will be described below using an example shown in FIG. FIG. 1 is a cross-sectional view of the structure of an integrated pressure sensor. The P-type substrate 1 of the PNN junction sea urchin used in the present invention has a plane orientation (IOO) and an impurity concentration of, for example, IX
10'``cm-''.The N-type layer 2 is an epitaxial layer and has an impurity concentration of 1×10cWI, which is the same as that of the P-type substrate.
shall be. The piezoresistor 3 is formed by ion implantation or thermal diffusion of zolon. The peripheral thick wall part of the pressure sensor has P.
A type well 13 is formed, and an n-channel MO8IC or t
It integrates Ibora IC and is used for signal processing. When this PNN junction is etched by an electrochemical etching method in the same manner as in the prior art and the P type substrate 1 is etched, when the etching reaches the N type layer 2, the etching is automatically stopped and a diaphragm is formed.
この様に本発明では電気化学法によりシリコンをエツチ
ングしてダイアフラムを形成すると熱工程を加えても各
層の不純物濃度が同一のため、不純物の移動が互いに打
消し合い、実効的なエピタキシャル層の厚さが変わらな
い。本発明は実施例に示した不純物濃度の場合に限定さ
れるものでになく他の不純物濃度でも得られることは１
゛うまでもない。In this way, in the present invention, when a diaphragm is formed by etching silicon using an electrochemical method, the impurity concentration in each layer is the same even if a thermal process is applied, so the movement of impurities cancels each other out, and the effective thickness of the epitaxial layer is increased. It doesn't change. The present invention is not limited to the impurity concentrations shown in the examples, but can also be obtained with other impurity concentrations.
゛Of course.
したがって、本発明によれば、電気化学エツチング法を
用いて設計値どうりの均一な膜厚全有するシリコンダイ
アフラムを得ることができる効果を有するものである。Therefore, according to the present invention, it is possible to obtain a silicon diaphragm having a uniform thickness in accordance with the design value using the electrochemical etching method.
第１図は本発明の実施例を示すシリコン基板の構造断面
、第２図は従来のダイアプラム型圧力センサの構造断面
図、第３図はダイアフラムを形成する為のエツチング装
置でおる。
１・・・Ｐ型基板、２・・・Ｎ型層、３・・・ピエゾ抵
抗、４・・・石英ビー力、５・・・エツチング液、６・
−・ヒータ、７・・・Ｎ型層、８・・・金属膜、９・・
・電源、１０・・Ｐ型基板、ＩＪ・・・白金電極、１２
・・・電流計、Ｊ３・・・Ｐ型ウェル。FIG. 1 is a structural cross-sectional view of a silicon substrate showing an embodiment of the present invention, FIG. 2 is a structural cross-sectional view of a conventional diaphragm type pressure sensor, and FIG. 3 is an etching apparatus for forming a diaphragm. DESCRIPTION OF SYMBOLS 1... P type substrate, 2... N type layer, 3... Piezoresistance, 4... Quartz bead force, 5... Etching liquid, 6...
- Heater, 7 N-type layer, 8 Metal film, 9...
・Power supply, 10...P-type substrate, IJ...platinum electrode, 12
...Ammeter, J3...P-type well.
Claims (1)
ラムを形成する工程において、ＰＮ接合シリコン基板の
各層の不純物濃度を同一としたことを特徴とするシリコ
ンダイアフラムの形成方法。(1) A method for forming a silicon diaphragm, characterized in that the impurity concentration of each layer of a PN junction silicon substrate is made the same in the step of forming a silicon diaphragm using an electrochemical etching method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20236885A JPS6261374A (en) | 1985-09-11 | 1985-09-11 | Manufacture of silicon diaphragm |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20236885A JPS6261374A (en) | 1985-09-11 | 1985-09-11 | Manufacture of silicon diaphragm |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6261374A true JPS6261374A (en) | 1987-03-18 |
Family
ID=16456342
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20236885A Pending JPS6261374A (en) | 1985-09-11 | 1985-09-11 | Manufacture of silicon diaphragm |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6261374A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01222489A (en) * | 1988-03-01 | 1989-09-05 | Fujitsu Ltd | Manufacture of semiconductor device |
| US5225377A (en) * | 1991-05-03 | 1993-07-06 | Honeywell Inc. | Method for micromachining semiconductor material |
| EP0588371A2 (en) * | 1992-09-18 | 1994-03-23 | Nippondenso Co., Ltd. | Semiconductor dynamic sensor having a thin thickness structure and its production method |
| JPH0897439A (en) * | 1994-09-14 | 1996-04-12 | Delco Electron Corp | One-chip accumulation sensor |
| US5949118A (en) * | 1994-03-14 | 1999-09-07 | Nippondenso Co., Ltd. | Etching method for silicon substrates and semiconductor sensor |
| JP2001068686A (en) * | 1999-07-13 | 2001-03-16 | Robert Bosch Gmbh | Formation of diaphragm |
| US6284670B1 (en) | 1997-07-23 | 2001-09-04 | Denso Corporation | Method of etching silicon wafer and silicon wafer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5878470A (en) * | 1981-11-04 | 1983-05-12 | Mitsubishi Electric Corp | Detecting device for semiconductor pressure |
-
1985
- 1985-09-11 JP JP20236885A patent/JPS6261374A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5878470A (en) * | 1981-11-04 | 1983-05-12 | Mitsubishi Electric Corp | Detecting device for semiconductor pressure |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01222489A (en) * | 1988-03-01 | 1989-09-05 | Fujitsu Ltd | Manufacture of semiconductor device |
| US5225377A (en) * | 1991-05-03 | 1993-07-06 | Honeywell Inc. | Method for micromachining semiconductor material |
| EP0588371A2 (en) * | 1992-09-18 | 1994-03-23 | Nippondenso Co., Ltd. | Semiconductor dynamic sensor having a thin thickness structure and its production method |
| EP0588371A3 (en) * | 1992-09-18 | 1995-05-10 | Nippon Denso Co | Semiconductor dynamic sensor having a thin thickness structure and its production method. |
| US5643803A (en) * | 1992-09-18 | 1997-07-01 | Nippondenso Co., Ltd. | Production method of a semiconductor dynamic sensor |
| US5949118A (en) * | 1994-03-14 | 1999-09-07 | Nippondenso Co., Ltd. | Etching method for silicon substrates and semiconductor sensor |
| US6194236B1 (en) | 1994-03-14 | 2001-02-27 | Denso Corporation | Electrochemical etching method for silicon substrate having PN junction |
| JPH0897439A (en) * | 1994-09-14 | 1996-04-12 | Delco Electron Corp | One-chip accumulation sensor |
| US5719069A (en) * | 1994-09-14 | 1998-02-17 | Delco Electronics Corporation | One-chip integrated sensor process |
| US6284670B1 (en) | 1997-07-23 | 2001-09-04 | Denso Corporation | Method of etching silicon wafer and silicon wafer |
| JP2001068686A (en) * | 1999-07-13 | 2001-03-16 | Robert Bosch Gmbh | Formation of diaphragm |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4125820A (en) | Stress sensor apparatus | |
| JPH0453267B2 (en) | ||
| US3994009A (en) | Stress sensor diaphragms over recessed substrates | |
| US3853650A (en) | Stress sensor diaphragms over recessed substrates | |
| JPS59117271A (en) | Semiconductor device having pressure sensing element and manufacture thereof | |
| JPS6261374A (en) | Manufacture of silicon diaphragm | |
| US4033787A (en) | Fabrication of semiconductor devices utilizing ion implantation | |
| US4035823A (en) | Stress sensor apparatus | |
| US4054497A (en) | Method for electrolytically etching semiconductor material | |
| JPS6032993B2 (en) | Semiconductor stress sensor and its manufacturing method | |
| JPS6037177A (en) | Semiconductor pressure sensor | |
| JP3116384B2 (en) | Semiconductor strain sensor and manufacturing method thereof | |
| JPH01136378A (en) | Manufacture of pressure transducer | |
| JPH03208375A (en) | Semiconductor pressure sensor | |
| JPS62266876A (en) | Semiconductor pressure sensor | |
| JPH0645617A (en) | Manufacture of single-crystal thin-film member | |
| JPS6097676A (en) | Semiconductor pressure sensor and manufacture thereof | |
| JPS63100780A (en) | Manufacture of pressure sensor | |
| JPS61119080A (en) | Manufacture of semiconductor pressure sensor | |
| JPS5617076A (en) | Manufacture of semiconductor device | |
| JPS60211945A (en) | Method for formation of thin film | |
| JPS6356962A (en) | Manufacture of semiconductor pressure transducer | |
| JPH01251620A (en) | Manufacture of semiconductor device | |
| JPS63178567A (en) | Manufacture of semiconductor pressure sensor | |
| JPS62283679A (en) | Manufacture of semiconductor pressure sensor |