JPS62169525A - Pll circuit - Google Patents
Pll circuitInfo
- Publication number
- JPS62169525A JPS62169525A JP61010040A JP1004086A JPS62169525A JP S62169525 A JPS62169525 A JP S62169525A JP 61010040 A JP61010040 A JP 61010040A JP 1004086 A JP1004086 A JP 1004086A JP S62169525 A JPS62169525 A JP S62169525A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- output
- pll circuit
- controlled oscillator
- Prior art date
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Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はＰＬＬ回路に係り、特ｌこ入力信号と入力雑音
電力密度との比が低い場合でも、広範囲に亘って高速で
引き込むのに好適なＰＬＬ、回路に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a PLL circuit, and particularly to a PLL circuit suitable for drawing in a wide range at high speed even when the ratio of input signal to input noise power density is low. Regarding PLL and circuits.
従来のＰＬＬ回路は、広範囲に渡って速やかに引き込ま
せるために、第４図に示すように、掃引信号発生回路４
の掃引信号を位相比較器１゜低域通戸波器２および加算
回路５と共にループを構成する電圧制御発振器６の制御
信号に重畳し、ＰＬＬ回路のロック状態を検出する検出
回路５の出力により、非ロツク時に掃引信号発生回路４
の掃引を開始し、電圧制御発振器６の発振周波数を振り
、ロック時に掃引を停止するように構成されていた。し
かし、入力信号対入力雑音電力密度比が低く、従って、
ＰＬＬを安定にロックさせるため、ＰＬＬ回路の等価雑
音帯域を数十ｔｌｚと狭くしなければならない場合、低
域通過フィルタ２の時定数を大きくすると同時に、掃引
信号発生回路４の掃引速度も下げなくてはならず、結局
引き込み時間が短かく出来ないという問題があった。な
お、この種の回路として関連するものに特開昭６０−１
２０６２０号公報があげられる。The conventional PLL circuit uses a sweep signal generation circuit 4 as shown in FIG.
The sweep signal is superimposed on the control signal of the voltage controlled oscillator 6, which forms a loop with the phase comparator 1, the low-pass wave filter 2, and the adder circuit 5, and the output of the detection circuit 5 detects the locked state of the PLL circuit. Sweep signal generation circuit 4 when unlocked
, the oscillation frequency of the voltage controlled oscillator 6 is changed, and the sweep is stopped when the lock is reached. However, the input signal to input noise power density ratio is low, so
In order to stably lock the PLL, if the equivalent noise band of the PLL circuit must be narrowed to several tens of tlz, the time constant of the low-pass filter 2 should be increased, and at the same time, the sweep speed of the sweep signal generation circuit 4 should not be reduced. However, there was a problem in that the pull-in time was too short. In addition, a related circuit of this type is disclosed in Japanese Patent Application Laid-open No. 1986-1.
Publication No. 20620 is mentioned.
本発明は上述したような従来のＰＬＬ回路ｌこ於ける、
低入力信号対入力雑音電力密度比での、広い引き込み範
囲を有する場合の、引き込み時間に関する問題点を除去
して、短時間で引き込むことが可能となるＰＬＬ回路を
提供することを目的とする。The present invention provides the above-mentioned conventional PLL circuit.
It is an object of the present invention to provide a PLL circuit which eliminates problems related to the pull-in time when having a wide pull-in range with a low input signal to input noise power density ratio, and which enables the pull-in in a short time.
本発明は、上記目的を達成するために、ＰＬＬ回路のロ
ック状態を検出するロック検出回路からの出力により、
ＰＬＬ回路のループを開閉するスイッチと、該検出回路
からの出力により、一定時間内で電圧制御発振器の出力
と入力信号との周波数差を測定し、該測定周波数差に応
じた信号を発生する初期設定回路とを備え、非ロツク時
に、一定時間ＰＬＬ回路のループを開き、該一定時間内
で前記電圧制御発振器の出力と入力信号との周波数差に
応じた信号を、前記初期設定回路で発生し、該初期設定
回路の出力を前記電圧制御発振器の制御信号に重畳して
、該電圧制御発振器に加え、初期周波数差をキャンセル
した後、ＰＬＬ回路のループを閉じて、ＰＬＬ回路のル
ープ制御開始とするようにしたものである。In order to achieve the above object, the present invention has the following features:
An initial stage in which the frequency difference between the output of the voltage controlled oscillator and the input signal is measured within a certain period of time using a switch that opens and closes the loop of the PLL circuit and the output from the detection circuit, and a signal corresponding to the measured frequency difference is generated. and a setting circuit, the loop of the PLL circuit is opened for a certain period of time when the lock is not locked, and within the certain period of time, a signal corresponding to the frequency difference between the output of the voltage controlled oscillator and the input signal is generated by the initial setting circuit. , superimposing the output of the initial setting circuit on the control signal of the voltage controlled oscillator and adding it to the voltage controlled oscillator, canceling the initial frequency difference, closing the loop of the PLL circuit, and starting loop control of the PLL circuit. It was designed to do so.
以下、本発明の一冥施例を第１図により説明する。第４
図と同様の構成要素については同一番号を付しである。Hereinafter, one embodiment of the present invention will be explained with reference to FIG. Fourth
Components similar to those in the figures are given the same numbers.
本発明のＰＬＬ回路は、入力信号と掃引信号発生回路６
との位相を比較する位相比較回路１とこの出力の低域出
力を通過させる低域通過フィルタ２と、前記位相比較回
路１の出力をもってＰＬＬ回路がロックか非ロックかを
検出するロック検出回路５と、前記入力信号と掃引信号
発生回路６の出力および前記ロック検出回路の出力とを
取込み初期設定出力を低域通過フィルタの出力と電圧制
御発振器の入力との間に直列に接続されたループ開閉ス
イッチ８と加算回路３に出力し、スイッチの制御と電圧
制御発振器の設定電圧として供給するように構成しであ
る。第２図は、第１図の初期設定回路７の一構成例であ
る。第３図は第１図（ａ）〜（ｄ）各部の波形を示すタ
イミングチャートである。以下、第３図を用いて第１図
に示すＰＬＬ回路の動作の説明をする。The PLL circuit of the present invention has an input signal and a sweep signal generation circuit 6.
a low-pass filter 2 that passes the low-frequency output of this output, and a lock detection circuit 5 that detects whether the PLL circuit is locked or non-locked based on the output of the phase comparison circuit 1. The input signal, the output of the sweep signal generation circuit 6, and the output of the lock detection circuit are taken in and the initial setting output is connected to a loop connected in series between the output of the low-pass filter and the input of the voltage controlled oscillator. The configuration is such that the voltage is output to the switch 8 and the adder circuit 3 to control the switch and supply it as a set voltage for the voltage controlled oscillator. FIG. 2 shows an example of the configuration of the initial setting circuit 7 shown in FIG. FIG. 3 is a timing chart showing waveforms at each part of FIGS. 1(a) to (d). The operation of the PLL circuit shown in FIG. 1 will be explained below using FIG. 3.
今、入力信号と電圧制御発振器６の出力（ｅ）とに周波
数差が位相比較回路１の出力に生じ、この出力を受けて
ロック検出回路５ζこよりＰＬＬ回路が非ロックと検出
されると、ロック検出回路５のロック／非ロツク信号（
ａ）が非ロックとなり、初期設定回路７を通じて、ルー
プ開閉スイッチ８への０Ｎ１０ＦＦ信号伽）が０１・’
Ｆとなり、該スイッチをＯＦ″ＦにしてＰＬＬ回路の
ループを開く。同時に、初期設定回路７は第２図に示す
ようにビート検出回路９．カウンタ１０．Ａ／Ｄ変換器
１１およびタイミング制御回路１２とで構成されている
のでこの回路では、入力信号と電圧制御発振器６の出力
（ｅ）との周波数差に等しいビート信号が発生し、これ
をビート検出回路９で検出し、この周波数差に応じた電
圧ＶＩＮＩをカウンタ１０． Ａ／Ｄ変換器１１および
タイミング制御回路１２とでビート信号（ｆ）の−周期
後に設定電圧（Ｃ）として電圧制御発振器６に加え、ル
ープ開閉スイッチ８への０Ｎ１０Ｆ′Ｆ信号（ｂ）をＯ
Ｎとして位相比較回路１．低域通過フィルタ２．加算回
路６．電圧制御発振器６からなるＰＬＬ回路のループを
閉じる。この時入力信号と電圧？［’ｌＪ御発振器６の
出力（ｅ）との周波数は、ＰＬＬ回路のロックインレン
ジ内にあるので、電圧制御発振器６の制御信号（ｄ）は
第３図に示すようになり、ループ開閉スイッチＯＮより
Ｔ２後にＰＬＬ回路ロックとなる。Now, a frequency difference occurs at the output of the phase comparison circuit 1 between the input signal and the output (e) of the voltage controlled oscillator 6, and upon receiving this output, the lock detection circuit 5ζ detects that the PLL circuit is not locked. Lock/unlock signal of detection circuit 5 (
a) is unlocked, and the 0N10FF signal (0N10FF signal) to the loop open/close switch 8 is set to 01・' through the initial setting circuit 7.
F, and the switch is turned OFF'' to open the loop of the PLL circuit. At the same time, the initial setting circuit 7, as shown in FIG. 12, in this circuit, a beat signal equal to the frequency difference between the input signal and the output (e) of the voltage controlled oscillator 6 is generated, which is detected by the beat detection circuit 9, and this frequency difference is detected by the beat detection circuit 9. The corresponding voltage VINI is added to the voltage controlled oscillator 6 as a set voltage (C) after - period of the beat signal (f) by the counter 10, the A/D converter 11 and the timing control circuit 12, and is applied to the voltage control oscillator 6 as a set voltage (C), and is applied to the loop open/close switch 8 at 0N10F. 'F signal (b) to O
Phase comparator circuit 1 as N. Low pass filter 2. Addition circuit 6. The loop of the PLL circuit consisting of the voltage controlled oscillator 6 is closed. What is the input signal and voltage at this time? ['l Since the frequency with the output (e) of the J control oscillator 6 is within the lock-in range of the PLL circuit, the control signal (d) of the voltage control oscillator 6 becomes as shown in Fig. 3, and the loop open/close switch PLL circuit becomes locked after T2 from ON.
以上のタイミング時間をＰＬＬ回路の等価雑音帯域が数
十Ｈｚとなる場合に対応させて説明する０
初期設定回路７での周波数差測定時間Ｔ１は、初期設定
回路７で補償する最小周波数差による。The above timing time will be explained in connection with the case where the equivalent noise band of the PLL circuit is several tens of Hz.The frequency difference measurement time T1 in the initial setting circuit 7 depends on the minimum frequency difference compensated by the initial setting circuit 7.
これを、等価雑音帯域数十ＨｚとするＰＬＬ回路のロッ
クインレンジが数十ｆｉｚより、今、１０ｈとする、前
記周波数差測定時間Ｔ１は０．１（ｓ：ｌ以下となり、
Ｔ２としても数十（ｍｓ）となる。つまり、ＰＬＬ回路
の引き込み時間は百数十（ｍｓ）となる。Assuming that the lock-in range of the PLL circuit with an equivalent noise band of several tens of Hz is now 10 hours, the frequency difference measurement time T1 is less than 0.1 (s:l),
Even T2 is several tens (ms). In other words, the pull-in time of the PLL circuit is over 100 ms.
周波数差が大きい程、ビート信号（ｆ）の発生周期は短
かくなるので、前記周波数差測定時間Ｔｌは小さくなり
、引き込み時間も短かくなる。本実施例によれば、数曲
の周波数偏差に対し、数十ｋＨｚ刻みで掃引を行なう従
来の掃引方式に比べ約１００分の１の引き込み時間とす
ることが出来る。The larger the frequency difference, the shorter the generation period of the beat signal (f) becomes, so the frequency difference measurement time Tl becomes shorter and the pull-in time also becomes shorter. According to this embodiment, it is possible to reduce the pull-in time to about 1/100 compared to the conventional sweep method in which sweep is performed in steps of several tens of kHz for frequency deviations of several songs.
この効果は周波数差が大きくなる程大きくなる。This effect becomes larger as the frequency difference becomes larger.
本発明によれば、電圧制御発振器と、該電圧制御発振器
の出力と入力信号との位相誤差成分を低域通過フィルタ
を通じて該電圧制御発振器に制御信号として与えるよう
にしたＰＬＬ回路において、前記ＰＬＬ回路のロック状
態を検出する検出回路と、該検出回路の出力により、非
ロツク時に一定時間該低域通過フィルタの出力を切断す
るループ開閉スイッチと、該一定時間に、該電圧制御発
振器の出力と入力信号との周波数差を測定し、該周波数
差に応じた信号を発生する初期設定回路とを設け、該初
期設定回路の出力を前記制御信号に重畳させ前記電圧制
御発振器に加えるようにしたので、等価雑音帯域を狭帯
域とする時定数の大きい低域通過フィルタから成るＰＬ
Ｌ回路において、広い周波数引き込み範囲を有し、高速
で引き込むことが可能となる。According to the present invention, in the PLL circuit, the PLL circuit includes a voltage controlled oscillator and a phase error component between the output of the voltage controlled oscillator and an input signal is provided as a control signal to the voltage controlled oscillator through a low-pass filter. a detection circuit that detects the locked state of the low-pass filter; a loop open/close switch that disconnects the output of the low-pass filter for a certain period of time when the filter is not locked according to the output of the detection circuit; An initial setting circuit is provided which measures the frequency difference with the signal and generates a signal according to the frequency difference, and the output of the initial setting circuit is superimposed on the control signal and applied to the voltage controlled oscillator. PL consisting of a low-pass filter with a large time constant and a narrow equivalent noise band
The L circuit has a wide frequency pull-in range and can be pulled in at high speed.
第１図乃至第６図はいずれも本発明の一実施例を示すも
ので、第２図はＰＬＬ回路の構成図、ＷＪ２図は第１図
の初期設定回路の構成図、第３図は第１図の（ａ）〜（
ｄ）、および第２図の（ｆ）各部の波形を示すタイミン
グチャート、第４図は従来の掃引方式によるＰＬＬ回路
の構成図である。
符号の説明
１・・・位相比較器 ２・・・低域通過フィルタ３
・・・加算回路 ４・・・掃引信号発生回路５・
・・ロック検出回路 ６・・・電圧制御発振器７・・・
初期設定回路 ８・・・ループ開閉スイッチ９・・・
ビート検出回路 １０・・・カウンタ１１・・・Ｄ／Ａ
ｆ換器
１２・・・タイミング制御回路
（Ａ）・・・ロック／非ロツク信号
（ｂ）・・・スィッチ０Ｎ１０ＦＦ信号（ｃ）・・・設
定電圧 （ｄ）・・・制御信号（ｆ）・・・ビー
ト信号
ヌ １ 記
季 ２ ロ1 to 6 each show an embodiment of the present invention. FIG. 2 is a configuration diagram of a PLL circuit, FIG. WJ2 is a configuration diagram of the initial setting circuit of FIG. 1, and FIG. Figure 1 (a) to (
d) and (f) of FIG. 2 are timing charts showing waveforms of various parts, and FIG. 4 is a configuration diagram of a PLL circuit using a conventional sweep method. Explanation of symbols 1... Phase comparator 2... Low pass filter 3
...Addition circuit 4...Sweep signal generation circuit 5.
...Lock detection circuit 6...Voltage controlled oscillator 7...
Initial setting circuit 8... Loop open/close switch 9...
Beat detection circuit 10...Counter 11...D/A
f converter 12...Timing control circuit (A)...Lock/non-lock signal (b)...Switch 0N10FF signal (c)...Setting voltage (d)...Control signal (f) ...Beat signal 1 Recording period 2 Ro
Claims (1)
との位相誤差成分を低域通過フイルタを通じて該電圧制
御発振器に制御信号として与えるようにしたＰＬＬ回路
において、前記ＰＬＬ回路のロツク状態を検出する検出
回路と、該検出回路の出力により、非ロツク時に一定時
間該低域通過フイルタの出力を切断するループ開閉スイ
ツチと、該一定時間に、該電圧制御発振器の出力と入力
信号との周波数差を測定し、該周波数差に応じた信号を
発生する初期設定回路とを設け、該初期設定回路の出力
を前記制御信号に重畳させ前記電圧制御発振器に加える
ようにしたことを特徴とするＰＬＬ回路。In a PLL circuit including a voltage controlled oscillator and a phase error component between the output of the voltage controlled oscillator and an input signal, which is applied as a control signal to the voltage controlled oscillator through a low-pass filter, a lock state of the PLL circuit is detected. a detection circuit; a loop opening/closing switch that uses the output of the detection circuit to cut off the output of the low-pass filter for a certain period of time when the lock is out; A PLL circuit comprising: an initial setting circuit that measures the frequency difference and generates a signal according to the frequency difference; the output of the initial setting circuit is superimposed on the control signal and applied to the voltage controlled oscillator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61010040A JPS62169525A (en) | 1986-01-22 | 1986-01-22 | Pll circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61010040A JPS62169525A (en) | 1986-01-22 | 1986-01-22 | Pll circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62169525A true JPS62169525A (en) | 1987-07-25 |
Family
ID=11739278
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61010040A Pending JPS62169525A (en) | 1986-01-22 | 1986-01-22 | Pll circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62169525A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01209816A (en) * | 1988-02-17 | 1989-08-23 | Nec Corp | Frequency phase locked loop circuit |
| JPH0368216A (en) * | 1989-08-07 | 1991-03-25 | Mitsubishi Electric Corp | Pll circuit |
| JPH07170176A (en) * | 1993-09-29 | 1995-07-04 | Sgs Thomson Microelectron Ltd | Device for setting up tuning frequency of pll circuit and its method |
-
1986
- 1986-01-22 JP JP61010040A patent/JPS62169525A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01209816A (en) * | 1988-02-17 | 1989-08-23 | Nec Corp | Frequency phase locked loop circuit |
| JPH0368216A (en) * | 1989-08-07 | 1991-03-25 | Mitsubishi Electric Corp | Pll circuit |
| JPH07170176A (en) * | 1993-09-29 | 1995-07-04 | Sgs Thomson Microelectron Ltd | Device for setting up tuning frequency of pll circuit and its method |
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