JPS62130540A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62130540A JPS62130540A JP26949485A JP26949485A JPS62130540A JP S62130540 A JPS62130540 A JP S62130540A JP 26949485 A JP26949485 A JP 26949485A JP 26949485 A JP26949485 A JP 26949485A JP S62130540 A JPS62130540 A JP S62130540A
- Authority
- JP
- Japan
- Prior art keywords
- layer wiring
- thickness
- upper layer
- semiconductor device
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 〈産業上の利用分野〉 本発明は多層配線構造をもつ半導体装置に係る。[Detailed description of the invention] <Industrial application field> The present invention relates to a semiconductor device having a multilayer wiring structure.
〈従来の技術〉
多層配線構造を有する半導体装置の断面図は第２図に示
すごときものが知られている。<Prior Art> A cross-sectional view of a semiconductor device having a multilayer wiring structure as shown in FIG. 2 is known.
即ち基板１の上に金属蒸着法やスパッタリング法で形成
されたＡＩ等からなる下層配線２、その上にＣＶＤ等の
方法で形成された層間絶縁膜３を介して金属蒸着法やス
パッタリング法で形成されたＡＩ等の上層配線４からな
ろ多層配線構造を有する゛に導体装置が知られている。That is, a lower wiring 2 made of AI or the like is formed on a substrate 1 by a metal evaporation method or a sputtering method, and an interlayer insulating film 3 is formed thereon by a method such as a CVD method. A conductor device is known that has a multilayer wiring structure including an upper layer wiring 4 such as AI.
〈発明が解決しようとする問題点〉
第２図に示したような多、ｌＦ？配線構造をもつ半導体
装置では基板１の上に下う配線２及び層間絶縁膜３を形
成し、さらにその上に、上層配線４を形成する。この際
に、下層配線２と基板１との段差部分５に対応して、上
層配線４にくぼみ６が生ずる。このようなくぼみ６の部
分では断面がきわめて小さ・くなり、上層配線４の断線
を起す危険性がある。又その学的の発見はきわめてデ１
かしく、製品に組込まれた際、これが原因で所望の回路
特性が得られなかったり、機能しないことが起った。<Problem to be solved by the invention> Multi, IF? as shown in Figure 2? In a semiconductor device having a wiring structure, a lower wiring 2 and an interlayer insulating film 3 are formed on a substrate 1, and an upper layer wiring 4 is further formed thereon. At this time, a depression 6 is created in the upper layer wiring 4 corresponding to the stepped portion 5 between the lower layer wiring 2 and the substrate 1. The cross section of the recess 6 becomes extremely small, and there is a risk that the upper layer wiring 4 may break. Also, the scientific discovery is extremely de1.
However, when incorporated into a product, this caused the desired circuit characteristics to not be obtained or the circuit to malfunction.
本発明はかかる従来技術の欠点に鑑みてなされたもので
、下層配線２の段差部２に対応して上層配線４に生じて
いたくびれ部６を除去し得ろ半導体装置を提供すること
を目的とするものである。The present invention has been made in view of the drawbacks of the prior art, and an object of the present invention is to provide a semiconductor device in which the constriction 6 formed in the upper layer wiring 4 corresponding to the stepped portion 2 of the lower layer wiring 2 can be removed. It is something to do.
く問題点を解決するための手段〉
かかる目的を達成した本発明による半導体装置の構成（
よ、多、う配線構造をもつ半導体装置において、上層配
線の、膜厚が下層配線の膜厚よりも厚く形成されている
ことを特徴とするものである。Means for Solving the Problems> Configuration of a semiconductor device according to the present invention that achieves the above objects (
A semiconductor device having a multi-wiring structure is characterized in that the thickness of the upper layer wiring is thicker than the thickness of the lower layer wiring.
〈実 施 例〉
本発明による半導体装置の一実施例について図面を参照
して説明する。<Example> An example of a semiconductor device according to the present invention will be described with reference to the drawings.
第１図は本発明による半導体装置の一実施例の断面図で
ある。本発明による半導体装置によれば、第１図に示す
如く、基板１の上に金属蒸着法やスパッタリング法にそ
ってＡＩ等の下層配線２が形成さね、ＣＶＤ法等によっ
て下、腎と上層配線を絶縁するためのＳ ｉ Ｏ，。FIG. 1 is a sectional view of an embodiment of a semiconductor device according to the present invention. According to the semiconductor device according to the present invention, as shown in FIG. 1, the lower layer wiring 2 such as AI is formed on the substrate 1 by metal vapor deposition method or sputtering method, and the lower layer wiring 2 and upper layer wiring 2 are formed by CVD method etc. S i O, for insulating wiring.
の層間絶縁Ｎ３が形成されている。さらに層間絶縁層３
の上に与えられてパターンに従って、金属蒸着法やスパ
ッタリング法でＡｌ２等の下層配線４が形成されろ。本
発明のものでは上層配線４の厚みｄを下層配線２の厚み
ｄ。An interlayer insulation N3 is formed. Furthermore, interlayer insulating layer 3
A lower layer wiring 4 made of Al2 or the like is formed by metal vapor deposition or sputtering according to the pattern given above. In the present invention, the thickness d of the upper layer wiring 4 is the thickness d of the lower layer wiring 2.
にくらべて充分大きくたとえば、倍位に厚く施す。上層
配線４の厚みを下層配線２の厚みｄｏより大きく施すこ
とによって、蒸着法あるいはスパッタリング法で上層配
線４の層が層間絶縁膜３の段差部分５に形成される際、
順次所望の厚さｄ＝２ｄｏ （２倍の場合）に上層配
線層４の厚みが増していくにつれて、下地の段差に基づ
くくびれ部の凹みが少なくなることが分った。実験的に
上層配線４の厚みｄがほぼ２ｄｏであれば、従来しばし
ば問題となった段差部Ｓでの上層配線４のくびれ（よほ
とんど消え、なめらかな屈曲カーブをもつ屈曲部７を示
すことが分かった。従って、下層配線２の段差部５ての
上層配線４のくびれに基づく断線の問題は解消された。It is sufficiently large compared to, for example, applied twice as thickly. By making the thickness of the upper layer wiring 4 larger than the thickness do of the lower layer wiring 2, when the layer of the upper layer wiring 4 is formed on the stepped portion 5 of the interlayer insulating film 3 by a vapor deposition method or a sputtering method,
It has been found that as the thickness of the upper wiring layer 4 is gradually increased to the desired thickness d=2do (double case), the concavity of the constriction due to the step of the underlying layer decreases. Experimentally, if the thickness d of the upper layer wiring 4 is approximately 2do, the constriction of the upper layer wiring 4 at the stepped portion S, which has often been a problem in the past, almost disappears, and the bending portion 7 with a smooth bending curve is no longer shown. Understood. Therefore, the problem of disconnection due to the constriction of the upper layer wiring 4 at the stepped portion 5 of the lower layer wiring 2 has been solved.
〈発明の効果〉
本発明による半導体装置によれば下層配線の膜厚より上
層配線の膜厚を厚（することにより、下層配線の段差部
によって生じた上層配線のくびれがなくなす、くびれに
よる上層配線層の断線による不良品の発生は完全に防止
された。従って、本発明による半導体装置によれば多層
配線構造をもつ半導体装置の信頼性を一段と向上し、優
れた半導体製品を得ることができるようになった。<Effects of the Invention> According to the semiconductor device of the present invention, the film thickness of the upper layer wiring is made thicker than that of the lower layer wiring, thereby eliminating the constriction of the upper layer wiring caused by the stepped portion of the lower layer wiring. The occurrence of defective products due to disconnection in the wiring layer was completely prevented.Therefore, according to the semiconductor device of the present invention, the reliability of the semiconductor device having a multilayer wiring structure can be further improved, and an excellent semiconductor product can be obtained. It became so.
第１図は本発明による半導体装置の断面図、第２図は従
来のものの断面図である。
図 面 中、
１）よ基板、
２は下層配線、
３は層間絶縁膜、
４は上層配線、
５は段差部、
７（よ屈曲部である。
第１図
り ｚｌFIG. 1 is a sectional view of a semiconductor device according to the present invention, and FIG. 2 is a sectional view of a conventional device. In the drawing, 1) is the substrate, 2 is the lower layer wiring, 3 is the interlayer insulating film, 4 is the upper layer wiring, 5 is the step part, and 7 (the bent part). 1st drawing zl
Claims (1)
厚が下層配線の膜厚よりも厚く形成されていることを特
徴とする半導体装置。What is claimed is: 1. A semiconductor device having a multilayer wiring structure, characterized in that an upper layer wiring is formed thicker than a lower layer wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26949485A JPS62130540A (en) | 1985-12-02 | 1985-12-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26949485A JPS62130540A (en) | 1985-12-02 | 1985-12-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62130540A true JPS62130540A (en) | 1987-06-12 |
Family
ID=17473215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26949485A Pending JPS62130540A (en) | 1985-12-02 | 1985-12-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62130540A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05243637A (en) * | 1992-02-28 | 1993-09-21 | Nec Corp | Magnetic resistance sensor |
| JP2008292311A (en) * | 2007-05-24 | 2008-12-04 | Panasonic Electric Works Co Ltd | Sensor device and method for manufacturing the same |
-
1985
- 1985-12-02 JP JP26949485A patent/JPS62130540A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05243637A (en) * | 1992-02-28 | 1993-09-21 | Nec Corp | Magnetic resistance sensor |
| JP2008292311A (en) * | 2007-05-24 | 2008-12-04 | Panasonic Electric Works Co Ltd | Sensor device and method for manufacturing the same |
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