JPS6212658B2 - - Google Patents
Info
- Publication number
- JPS6212658B2 JPS6212658B2 JP54151852A JP15185279A JPS6212658B2 JP S6212658 B2 JPS6212658 B2 JP S6212658B2 JP 54151852 A JP54151852 A JP 54151852A JP 15185279 A JP15185279 A JP 15185279A JP S6212658 B2 JPS6212658 B2 JP S6212658B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- substrate
- concentration
- layer
- depth
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 239000012212 insulator Substances 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 239000013078 crystal Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- 238000009826 distribution Methods 0.000 description 9
- 238000007796 conventional method Methods 0.000 description 7
- 238000002513 implantation Methods 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000635 electron micrograph Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
本発明は、半導体集積回路の作成において、絶
縁性基板上に半導体素子を構成する際に絶縁性基
板を形成する絶縁層形成法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulating layer forming method for forming an insulating substrate when forming a semiconductor element on the insulating substrate in the production of a semiconductor integrated circuit.
従来、絶縁性基板上に半導体素子を構成する方
法として、SOS（Silicon On Sapphireの略で、
絶縁物であるサフアイア基板上にシリコン単結晶
薄膜を形成したもの）の他に、シリコンと絶縁性
化合物を形成する元素である酸素をイオン注入す
ることにより、シリコン単結晶基板内部に絶縁層
を形成し、表面に残存する単結晶シリコン層上
に、直接またはエピタキシヤル層を形成したの
ち、半導体素子を構成する方法が提案されてい
る。この方法の中で、後者の方法で形成された絶
縁層をもつ基板の断面とイオン注入された酸素の
濃度分布は、第１図に示したようになり、注入さ
れた酸素は、注入エネルギーで決まる深さ１を中
心にガウス型分布に分布し、深さ１付近には均一
な絶縁層２が形成される。しかしながら、深さ１
よりも浅い所と深い所には、均一な絶縁層形成に
必要な濃度３（4.5×1022個／cm3）に達しない領
域、即ち結晶欠陥や多結晶を含む境界層４が存在
する。このように、従来方法では、表面に残存す
る単結晶層５と内部に形成された絶縁層２の界面
が急峻でないため、表面単結晶シリコン層５上に
半導体集積回路を構成したとき、十分な電気特性
が得られなかつた。 Conventionally, SOS (abbreviation for Silicon On Sapphire) has been used as a method of configuring semiconductor elements on an insulating substrate.
In addition to forming a silicon single-crystal thin film on an insulating sapphire substrate, an insulating layer is formed inside the silicon single-crystal substrate by ion-implanting oxygen, an element that forms an insulating compound with silicon. However, a method has been proposed in which a semiconductor element is formed directly or after forming an epitaxial layer on the single crystal silicon layer remaining on the surface. In this method, the cross section of a substrate with an insulating layer formed by the latter method and the concentration distribution of ion-implanted oxygen are as shown in Figure 1, and the implanted oxygen changes depending on the implantation energy. The insulating layer 2 is distributed in a Gaussian shape around a predetermined depth 1, and a uniform insulating layer 2 is formed near the depth 1. However, depth 1
In areas shallower and deeper than this, there exists a region where the concentration does not reach the concentration 3 (4.5×10 22 /cm 3 ) required for forming a uniform insulating layer, that is, a boundary layer 4 containing crystal defects and polycrystals. In this way, in the conventional method, since the interface between the single crystal layer 5 remaining on the surface and the insulating layer 2 formed inside is not steep, when a semiconductor integrated circuit is constructed on the surface single crystal silicon layer 5, the Electrical characteristics could not be obtained.
本発明は、上記従来例の欠点である結晶欠陥や
多結晶を含む境界層をなくすため、熱拡散及び化
学反応が生じる温度に基板の温度を制御しなが
ら、均一な絶縁層形成に必要な濃度以上にイオン
の注入を行なつて、表面に残存する単結晶層と内
部絶縁層の界面を急峻なものとする絶縁層形成法
を提供するものである。以下、図面により実施例
を詳細に説明する。 In order to eliminate the boundary layer containing crystal defects and polycrystals, which are the drawbacks of the conventional example, the present invention aims to control the temperature of the substrate to a temperature at which thermal diffusion and chemical reactions occur, while maintaining the concentration necessary to form a uniform insulating layer. The present invention provides an insulating layer forming method in which the interface between the single crystal layer remaining on the surface and the internal insulating layer is made steep by performing ion implantation as described above. Hereinafter, embodiments will be described in detail with reference to the drawings.
第２図は、本発明によつて形成した絶縁層をも
つ基板の断面図と注入した酸素の濃度の深さ方向
分布を示したもので、熱拡散と化学反応が生じる
温度（約200℃以上）に保つた単結晶シリコン基
板に酸素をイオン注入すると、第２図ｂに示した
ように、最も濃度が高くなる深さ６付近に均一な
絶縁層が形成されるまでは従来法と同じガウス型
分布をとりつつその濃度を増していく。しかし、
深さ６付近が均一な絶縁層形成に十分な濃度に達
した後、更にイオン注入を続けると、深さ６付近
には絶縁物を形成できない過剰な酸素が注入され
ることになり、この過剰酸素は熱拡散により未反
応のシリコン原子が存在する領域まで移動し、そ
こで絶縁層を形成して静止する。このように、深
さ６付近に均一な絶縁層形成に必要な濃度以上の
イオン注入を行うことにより、注入された酸素の
濃度の深さ方向分布は注入量を増すに従つて７か
ら８，９，１０と変化する。従来法の1.5倍の注
入量８から分布の急峻化が著しくなり、従来法の
約２倍の注入量である１０ではきわめて急峻な分
布が実現され、この結果、基板の断面構造は第２
図ａのようになる。第２図ａにおいて、１１は表
面の単結晶層、１２は内部の化合物層であり、従
来法で存在した境界層は存在しない。 Figure 2 shows a cross-sectional view of a substrate with an insulating layer formed according to the present invention and the depth distribution of the concentration of implanted oxygen. ) When oxygen is ion-implanted into a single-crystal silicon substrate maintained at Its concentration increases while taking a type distribution. but,
If ion implantation is continued after the concentration near depth 6 reaches a level sufficient to form a uniform insulating layer, excess oxygen that cannot form an insulator will be implanted near depth 6, and this excess Oxygen moves by thermal diffusion to a region where unreacted silicon atoms exist, forms an insulating layer there, and remains stationary. In this way, by implanting ions at a concentration higher than that required to form a uniform insulating layer near the depth 6, the depth distribution of the implanted oxygen concentration changes from 7 to 8 as the implantation amount increases. It changes from 9 to 10. The distribution becomes noticeably steeper at an implantation amount of 8, which is 1.5 times the conventional method, and an extremely steep distribution is achieved at an implantation amount of 10, which is approximately twice the conventional method.As a result, the cross-sectional structure of the substrate becomes
It will look like figure a. In FIG. 2a, 11 is a single crystal layer on the surface, 12 is an internal compound layer, and there is no boundary layer that exists in the conventional method.
第３図は、絶縁層上に残存するシリコン層の結
晶性を示したもので、第３図ａは従来法によるも
のであり、高密度の結晶欠陥が存在するが、第３
図ｂに示した本発明のものでは、結晶欠陥は存在
せず、著しく結晶性が改善されていることがわか
る。更に、絶縁層の厚さは素子特性を保つ必要か
ら厚い方がよいが、同じ注入エネルギーで従来法
と本発明の方法を比べると、従来法が約1200Åで
あるのに対し、本発明の方法では4000Å以上であ
る。 Figure 3 shows the crystallinity of the silicon layer remaining on the insulating layer.
In the case of the present invention shown in FIG. b, there are no crystal defects, and it can be seen that the crystallinity is significantly improved. Furthermore, the thickness of the insulating layer should be thicker because it is necessary to maintain device characteristics, but when comparing the conventional method and the method of the present invention at the same implantation energy, the thickness of the conventional method is about 1200 Å, whereas the thickness of the method of the present invention is about 1200 Å. It is more than 4000Å.
以上説明したように、本発明によれば、注入し
た酸素の深さ方向の分布をきわめて急峻にできる
ため、表面残存単結晶層と内部絶縁層との界面の
結晶欠陥や多結晶を高密度に含む層をなくすこと
ができ、結晶性が著しく改善できる。また絶縁層
の厚さを厚くすることができるので、本発明の方
法で形成した絶縁層を有する基板上に半導体集積
回路を構成すれば、飛躍的な特性向上が期待され
る。また本発明の方法によれば、絶縁層の厚さは
注入エネルギーとその注入量によつてきわめて精
度よく制御可能であるので、実用上の効果は顕著
である。 As explained above, according to the present invention, the distribution of implanted oxygen in the depth direction can be made extremely steep, so that crystal defects and polycrystals at the interface between the surface remaining single crystal layer and the internal insulating layer can be removed at a high density. The crystallinity can be significantly improved by eliminating the layer containing the crystal. Further, since the thickness of the insulating layer can be increased, if a semiconductor integrated circuit is constructed on a substrate having an insulating layer formed by the method of the present invention, a dramatic improvement in characteristics is expected. Further, according to the method of the present invention, the thickness of the insulating layer can be controlled with extremely high precision by controlling the implantation energy and the implantation amount, so that the practical effects are remarkable.
第１図は、従来法で形成した絶縁層をもつ基板
の断面図とイオン注入された元素の深さ方向の濃
度分布を示した図、第２図は、本発明の方法で形
成した絶縁層をもつ基板の断面図とイオン注入さ
れた元素の深さ方向濃度分布を示した図、第３図
は、従来法と本発明の方法で形成した絶縁層上の
単結晶シリコン層の結晶性を比較した電子顕微鏡
写真である。
FIG. 1 is a cross-sectional view of a substrate with an insulating layer formed by the conventional method and a diagram showing the concentration distribution of ion-implanted elements in the depth direction, and FIG. 2 is a diagram showing the insulating layer formed by the method of the present invention. Figure 3 shows the cross-sectional view of a substrate with ion-implanted elements and the depth direction concentration distribution of ion-implanted elements. These are comparative electron micrographs.
Claims (1)
晶シリコン基板内部に、シリコンと反応して絶縁
物を形成する元素である酸素を均一な絶縁層中の
酸素濃度（4.5×1022個／cm3）の1.5倍以上の濃度
となるようにイオン注入することにより、表面に
残存する単結晶シリコン層との界面が急峻となる
ようにしたことを特徴とする単結晶シリコン基板
内部の絶縁層形成法。1 Oxygen , an element that reacts with silicon to form an insulator, is placed inside a single-crystal silicon substrate kept at a temperature that allows thermal diffusion and chemical reactions to occur. 3 ) Formation of an insulating layer inside a single-crystal silicon substrate characterized by implanting ions at a concentration of 1.5 times or more to make the interface with the single-crystal silicon layer remaining on the surface steep. Law.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15185279A JPS5674929A (en) | 1979-11-22 | 1979-11-22 | Insulating layer forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15185279A JPS5674929A (en) | 1979-11-22 | 1979-11-22 | Insulating layer forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5674929A JPS5674929A (en) | 1981-06-20 |
| JPS6212658B2 true JPS6212658B2 (en) | 1987-03-19 |
Family
ID=15527668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15185279A Granted JPS5674929A (en) | 1979-11-22 | 1979-11-22 | Insulating layer forming method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5674929A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5918151A (en) * | 1993-12-28 | 1999-06-29 | Nippon Steel Corporation | Method of manufacturing a semiconductor substrate and an apparatus for manufacturing the same |
| KR102482185B1 (en) | 2022-09-15 | 2022-12-29 | (주)코리아테크 | Stick type container |
| KR102484068B1 (en) | 2021-10-22 | 2023-01-04 | (주)코리아테크 | Stick type container |
-
1979
- 1979-11-22 JP JP15185279A patent/JPS5674929A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5918151A (en) * | 1993-12-28 | 1999-06-29 | Nippon Steel Corporation | Method of manufacturing a semiconductor substrate and an apparatus for manufacturing the same |
| KR102484068B1 (en) | 2021-10-22 | 2023-01-04 | (주)코리아테크 | Stick type container |
| KR102482185B1 (en) | 2022-09-15 | 2022-12-29 | (주)코리아테크 | Stick type container |
| KR102517535B1 (en) | 2022-09-15 | 2023-04-05 | (주)코리아테크 | Stick type container |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5674929A (en) | 1981-06-20 |
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