JPS62123785A - Semiconductor light emitting device - Google Patents

Abstract

PURPOSE:To control a large number of light emitting devices easily and individually by a method wherein a large number of column-shape protrusions in which P-N junctions extended to the direction vertical to a substrate are incorporated are solidly integrated and grooves are provided in flat plate parts between the protrusions. CONSTITUTION:An N-type AlGaAs barrier layer 3 and an N-type GaAs upper layer 4 are laminated on an N-type GaAs substrate 2 to form a flat plate part 1 and a large number of column-shaped protrusions 7 are formed on the flat plate part 1 with a predetermined space between each other in parallel to the direction vertical to the flat plate part 1 and solidly integrated. The front side electrodes E1 made of Cr, Au or the like are provided on the surfaces of the flat part 1 and the column-shaped protrusions 7 and a backside electrode E2 are provided on the backside of the flat part 1. Also, an impurity is diffused to form a P<+> type high concentration doped region 5 and a P-type low concentration doped region 6. Grooves 8 and 9 are formed along approximately central parts of the flat plate part 1 between the respective column-shaped protrusions 7 in checkerboard pattern.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は基板上に、これと交叉する方向に発光する複数
の発光素子を集積配置した半導体発光装置に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor light emitting device in which a plurality of light emitting elements emitting light in a direction crossing the substrate are integrated and arranged on a substrate.

〔従来技術〕[Prior art]

光ファイバを用いて複数個所と同時的、或いは個別的に
光通信、光情報伝達処理を行うシステム等においては、
多数の光ファイバ夫々について光源としての、例えば発
光素子を用意する必要がある。In systems that use optical fibers to perform optical communication and optical information transmission processing at multiple locations simultaneously or individually,
It is necessary to prepare, for example, a light emitting element as a light source for each of a large number of optical fibers.

このため従来にあっては、発光素子を組み込んだコネク
タを光フアイバ端部に装着することにより各光ファイバ
と発光素子との光学的結合を行っているが、光フアイバ
本数が増大するとコネクタが嵩張り全体が極めて大嵩と
なる。これを改善する方法として、近時にあっては１個
の基台上に別途形成した発光素子、例えば第５図に示す
如き面発光形の発光素子（発光ダイオード等）を配列固
定し、光ファイバをコネクタ等を用いて一括して各対応
する発光素子に対向保持せしめる構成が採られている。For this reason, conventionally, each optical fiber and the light emitting element are optically coupled by attaching a connector incorporating a light emitting element to the end of the optical fiber, but as the number of optical fibers increases, the connector becomes bulky. The entire tension becomes extremely bulky. Recently, as a method to improve this, separately formed light emitting elements, such as surface emitting type light emitting elements (light emitting diodes, etc.) as shown in FIG. 5, are arrayed and fixed on a single base, and optical fibers are A configuration is adopted in which the light emitting elements are collectively held facing each corresponding light emitting element using a connector or the like.

第５図は従来の面発光形の半導体発光素子を示す模式図
であり、基本的には、面発光型発光ダイオードの活性領
域を挟んでその上、下面に夫々クラッド層及び電極を順
次に設けて構成されている。FIG. 5 is a schematic diagram showing a conventional surface-emitting type semiconductor light-emitting device. Basically, a cladding layer and an electrode are sequentially provided on the upper and lower surfaces of the surface-emitting type light emitting diode with the active region sandwiched therebetween. It is composed of

即ち、図示の構成においては、中間層５１を、大きいエ
ネルギー・ギャップを有するクラッド層５２と５３とに
より上、下から挟んでサンドイッチ構造にしてあり、サ
ンドインチ構造の上、下両面に、例えば図示のように、
環状電極５８及び円形電極５６を設け、通例真性とする
中間層５１の中央部に活性領域５１ａを形成し、この活
性領域５１ａのみに上、下よりキャリヤを注入し、白抜
矢符で示す如くに光を取出すようにしである。That is, in the illustrated configuration, the intermediate layer 51 is sandwiched between upper and lower cladding layers 52 and 53 having a large energy gap to form a sandwich structure, and the upper and lower surfaces of the sandwich structure have, for example, like,
An annular electrode 58 and a circular electrode 56 are provided, and an active region 51a is formed in the center of the intermediate layer 51, which is usually intrinsic. Carriers are injected only into this active region 51a from above and below, as shown by the open arrow. It is designed to take out light.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

然しながら、従来の面発光素子は、活性領域５１ａを構
成するｐ−ｎ接合部が基板に対して平行に存在し、活性
領域５１ａの厚さは通常２〜３μｍにしかすぎない。そ
の結果、この種の発光素子から基板に対して直交する方
向に充分な強さの発振をおこさせるに必要な利得を得る
ためには、極めて大きい注入電流密度が必要となり、実
用的な発光素子に不可欠の条件である室温における連続
発振の実現が困難という致命的な欠点を本質的に有して
いる。However, in conventional surface emitting devices, the pn junction forming the active region 51a exists parallel to the substrate, and the thickness of the active region 51a is usually only 2 to 3 μm. As a result, in order to obtain the gain necessary to cause this type of light emitting device to oscillate with sufficient strength in the direction perpendicular to the substrate, an extremely large injection current density is required, making it difficult to make a practical light emitting device. The essential drawback is that it is difficult to achieve continuous oscillation at room temperature, which is an essential condition.

また上述の如き多数の発光素子を基台上に正確に配列固
定する作業自体も容易でなく、作業能率が低く作業も極
めて煩わしいという問題があった。Furthermore, the task of accurately arranging and fixing a large number of light emitting elements as described above on a base is not easy, and there are problems in that the work efficiency is low and the work is extremely troublesome.

〔問題点を解決するための手段〕[Means for solving problems]

本発明はかかる事情に鑑みなされたものであって、その
目的とするところは多数の発光素子を基板上に一体的に
集積形成すると共に、各発光素子は基板と交わる向きに
延在するｐ−ｎ接合部を備える柱状突起にて構成し、ま
た各発光素子は電気的に独立して個別に駆動制御が出来
ると共に室温下での連続発光が可能であり、同時的に複
数個所との通信、データ処理を行うのに適し、しかも極
めてコンパクトに構成し得る半導体発光装置を提供する
にある。The present invention has been made in view of the above circumstances, and its purpose is to integrally form a large number of light emitting elements on a substrate, and each light emitting element has a It is composed of columnar protrusions with n-junctions, and each light emitting element can be electrically independent and individually controlled, and can emit light continuously at room temperature, and can communicate with multiple locations simultaneously. It is an object of the present invention to provide a semiconductor light emitting device which is suitable for data processing and which can be configured extremely compactly.

本発明に一係る半導体発光装置は、基板と平行に延在す
るｐ−ｎ接合部を備えた平板部と、内部に前記基板と交
叉する向きに延在するｐ−ｎ接合部を備え、前記平板部
上に並列形成された複数個の柱状突起と、前記平板部の
裏面側に形成された裏面電極、並びに平板部の表面側及
び柱状突起の側周面にわたして形成された表面電極と、
前記各柱状突起を相互に電気的に遮断すべく柱状突起間
の平板部に形成された溝とを具備することを特徴とする
。A semiconductor light emitting device according to one aspect of the present invention includes a flat plate portion including a pn junction extending parallel to a substrate, and a pn junction extending in a direction intersecting the substrate; A plurality of columnar protrusions formed in parallel on the flat plate part, a back electrode formed on the back side of the flat plate part, and a front electrode formed across the front side of the flat plate part and the side peripheral surface of the columnar protrusion. ,
A groove is formed in the flat plate portion between the columnar projections to electrically isolate the columnar projections from each other.

〔実施例〕〔Example〕

以下本発明をその実施例を示す図面に基づき具体的に説
明する。第１図は本発明に係る半導体発光装着（以下本
発明装置という）の模式図、第２図は第１図の■−■線
による拡大断面図、第３図は柱状突起の部分拡大断面図
であり、図中１は平板部、７は柱状突起を示している。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof. Fig. 1 is a schematic diagram of a semiconductor light emitting device according to the present invention (hereinafter referred to as the device of the present invention), Fig. 2 is an enlarged sectional view taken along the line ■-■ in Fig. 1, and Fig. 3 is a partial enlarged sectional view of a columnar projection. In the figure, 1 indicates a flat plate portion, and 7 indicates a columnar projection.

柱状突起７は平板部１の片側面にこれと直交（非直角で
もよい）する向きで相互の間に所要の間隔を隔てて多数
一体的に集積して並列形成され、この平板部１及び柱状
突起の周面にはＣｒｙ、Ａｕ等を素材とする表面電極Ｅ
１が、また平板部１の下面にはＡｕ−Ｇｅ合金。A large number of columnar protrusions 7 are integrated and formed in parallel on one side of the flat plate part 1 in a direction perpendicular (or non-perpendicular) to the flat plate part 1 with a required interval between them. A surface electrode E made of Cry, Au, etc. is placed on the circumferential surface of the protrusion.
1 is an Au-Ge alloy on the lower surface of the flat plate part 1.

Ａｕ等を素材とする裏面電極Ｅ２が夫々設けられている
。A back electrode E2 made of Au or the like is provided respectively.

平板部１は例えばｎ型のＧａＡｓを材料とする基板２０
表面にｎ型のＡ　１　ｘＧａｌＸＡＳを材料とするバリ
ア［３，ｎ型のＧａＡｓを材料とする上部層４を積層形
成して構成しである。バリア層３は上部層４の構成材料
が有するエネルギーギャップよりも広いエネルギーギャ
ップを有する材料にて構成され、また上部層４は柱状突
起７と同し材料にて構成されている。The flat plate portion 1 includes a substrate 20 made of n-type GaAs, for example.
A barrier [3] made of n-type A 1 xGalXAS and an upper layer 4 made of n-type GaAs are laminated on the surface. The barrier layer 3 is made of a material having a wider energy gap than that of the constituent material of the upper layer 4, and the upper layer 4 is made of the same material as the columnar projections 7.

平板部１及び柱状突起７内には外表面に沿うよう不純物
を拡散により高濃度にドープされたｐ＋型（又はｎ＋型
）領域５が形成され、またこの領域５の内側に１８って
低濃度にドープされたｐ型（又はｎ型）領域６がバリア
層３中に位置させて形成されている。これら領＠５．６
以外のドープされていない領域はいずれも伝導型がｎ型
（又はｐ型）の材料にて形成されている。A heavily doped p+ type (or n+ type) region 5 is formed by diffusing impurities along the outer surface of the flat plate portion 1 and the columnar protrusion 7, and a low concentration region 18 is formed inside this region 5. A doped p-type (or n-type) region 6 is formed in the barrier layer 3 . These territories @5.6
All other undoped regions are formed of a material with n-type (or p-type) conductivity.

従って、平板部１内においてはバリア層３内に不純物が
拡散していない領域と領域５との界面にｐ−ｎ接合部Ｐ
Ｎ、が、また同様に柱状突起７内には不純物が拡散して
いない領域と領域５との界面に同軸円筒状をなすｐ−ｎ
型接合部ＰＮ２が形成されている。Therefore, in the flat plate portion 1, there is a p-n junction P at the interface between the region 5 and the region where impurities are not diffused in the barrier layer 3.
Similarly, in the columnar protrusion 7, there is a p-n having a coaxial cylindrical shape at the interface between the region 5 and the region where impurities are not diffused.
A mold joint PN2 is formed.

８．９は溝であり、各柱状突起７間の略中央部を通って
平板部１に基盤目状に形成されており、平板部１におけ
る表面電極Ｅｌ、ｐ＋型（又はｎ＋型）領域５及びｐ型
（又はｎ型）領域６を分断し、バリア層３内であって基
板２の近傍に達する略一様な深さに形成され、少なくと
も表面電極Ｅ１及び平板部１内のｐ−ｎ接合部ＰＮ、を
柱状突起７周囲において分断するようにしである。この
溝８゜９の深さについては特に限定するものではなく、
表面電極Ｅ１及びｐ−ｎ接合部ＰＮ、を分断し得る深さ
であればよい。Reference numeral 8.9 denotes a groove, which is formed in the flat plate part 1 in the shape of a base line passing approximately at the center between the columnar projections 7, and is connected to the surface electrode El in the flat plate part 1 and the p+ type (or n+ type) region 5. and the p-type (or n-type) region 6, and are formed at a substantially uniform depth within the barrier layer 3 and reaching the vicinity of the substrate 2, and are formed at least in the surface electrode E1 and the p-n region in the flat plate portion 1. The joint portion PN is divided around the columnar projection 7. The depth of this groove 8°9 is not particularly limited;
The depth may be any depth that can separate the surface electrode E1 and the p-n junction PN.

ただｔＩＢ、９の深さがバリア層３の中間部に留まって
いる以上この溝底から裏面電極Ｅ２の表面までの間のバ
リア層３を通して若干ではあるが、電流が相隣する他の
柱状突起７側に漏洩することは免れないから溝の深さは
基板２面に達するよう可及的に深くするのが望ましい。However, since the depth of tIB,9 remains in the middle part of the barrier layer 3, the current flows through the barrier layer 3 between the bottom of the groove and the surface of the back electrode E2, albeit slightly, to other adjacent columnar protrusions. Since leakage to the 7 side is inevitable, it is desirable that the depth of the groove be as deep as possible so as to reach the 2nd surface of the substrate.

平板部１、柱状突起７における各ｐ＋型（又はｎ＋型）
領域５、ｐ型（又はｎ型）領域６の形成方法については
特に限定するものではなく、例えば不純物の拡散法、或
いはｐ＋型（又はｎ＋型）半導体層、ｐ型（又はｎ型）
半導体層夫々を順次的にエピタキシャル成長させる方法
を採ってもよい。ｐ＋、ｐ型頭域５．６を例えば不純物
の拡散によって形成する場合、柱状突起７は反応性イオ
ンエツチング法等によって予め平板部１上にｎ型材料に
よる円柱を形成した後、これにｐ＋型（又はｎ＋型＞、
ｐ型（又はｎ型）形成のための不純物の拡散を施せばよ
い。Each p+ type (or n+ type) in the flat plate part 1 and columnar projection 7
The method of forming the region 5 and the p-type (or n-type) region 6 is not particularly limited, and for example, an impurity diffusion method, a p+-type (or n+-type) semiconductor layer, a p-type (or n-type)
A method may be adopted in which each semiconductor layer is epitaxially grown in sequence. When the p+, p-type head region 5.6 is formed, for example, by diffusion of impurities, the columnar protrusion 7 is formed by forming a column of n-type material on the flat plate part 1 in advance by reactive ion etching, etc. (or n+ type>,
Impurity diffusion for forming p-type (or n-type) may be performed.

柱状突起７の高さはｐ−ｎ接合部ＰＮ２の長さ。The height of the columnar projection 7 is the length of the p-n junction PN2.

換言すれば発光強度を考慮して設定すればよいが、通常
は２〜数百μｍ程度であり、またその形状は必ずしも円
柱状とする必要はなく、上端側に向かうに従って直径を
縮小した円錐台形、或いは逆円１１ｉ台形、その他種円
形、矩形、方形、三角形等であってもよい。In other words, it can be set taking into account the emission intensity, but it is usually about 2 to several hundred μm, and the shape does not necessarily have to be cylindrical, but a truncated cone shape whose diameter decreases toward the upper end. , or may be an inverted circle 11i trapezoid, other circular shapes, rectangles, squares, triangles, etc.

なお柱状突起７の軸心線、換言すればｐ−ｎ接合部ＰＮ
２は必ずしも平板部１、具体的には基Ｆｉ２と直交させ
る必要はな（、基板２と所要の角度で交叉させる向きに
形成し、基板２と非直角の方向に光を発する構成として
もよい。Note that the axial center line of the columnar projection 7, in other words, the p-n junction PN
2 does not necessarily need to be orthogonal to the flat plate portion 1, specifically, the base Fi2 (although it may be formed in a direction that intersects the substrate 2 at a required angle, and emit light in a direction that is not perpendicular to the substrate 2. .

本発明装置に用いる発光材料としては、ｎ−ｖ−族化合
物半導体であるＧａＡｓ、八ｊ２　ＧａＡｓ、　ＴｎＰ
、　ＴｎＧａＡｓＰ。The light-emitting materials used in the device of the present invention include n-v-group compound semiconductors such as GaAs, 8j2 GaAs, and TnP.
, TnGaAsP.

ＩｎＧａＰ、　　ＩｎＡｊ！Ｐ、　　ＧａＡｓＰ、　　
ＧａＮ、　　ＩｎＡｓＰ、　　［ｎＡｓＳｂ等、ｎ−ｖ
ｉ族化合物半導体であるＺｎ５ｅ、　ＺｎＳ、　ＺｎＯ
。InGaP, InAj! P, GaAsP,
GaN, InAsP, [nAsSb, etc., n-v
Zn5e, ZnS, ZnO, which are i-group compound semiconductors
.

ＣｄＳｅ、　ＣｄＴｅ等、あるいはＩＶ−ＶＩ族化合物
半導体であるＰｂＴｅ、　Ｐｂ５ｎＴｅ、　Ｐｂ５ｎＳ
ｅ等があり、それぞれの材料の長所を活かして適用する
ことが可能である。CdSe, CdTe, etc., or IV-VI group compound semiconductors such as PbTe, Pb5nTe, Pb5nS
e, etc., and it is possible to apply them by taking advantage of the advantages of each material.

而して上述した如き本発明装置にあっては裏面電極Ｅ２
と選択した柱状突起７のいずれかの表面電極Ｅ１との間
に所定の電圧を印加することによって他の柱状電極７と
は無関係に各柱状突起７の上端面から個別的に発光を行
わせ得ることとなる。Therefore, in the device of the present invention as described above, the back electrode E2
By applying a predetermined voltage between the selected columnar protrusion 7 and the surface electrode E1 of any one of the selected columnar protrusions 7, light can be emitted individually from the upper end surface of each columnar protrusion 7, regardless of the other columnar electrodes 7. That will happen.

第４図は本発明の他の実施例を示す拡大断面図であり、
平板部１１における基板１２には半絶縁性材料にて構成
すると共に、各柱状突起１７の中央部と対応する位置に
は基板１２を貫通する孔１２ａを形成する一方、基板１
２の裏面には各柱状突起１７と対応する位置に個々に分
断された裏面電極Ｅ２を設け、孔１２ａと対向する部分
では各裏面電極Ｅ２が孔１２ａを通して基板１２の表面
に位置するバリア層１３と接触するようにしである。FIG. 4 is an enlarged sectional view showing another embodiment of the present invention,
The substrate 12 in the flat plate portion 11 is made of a semi-insulating material, and a hole 12a passing through the substrate 12 is formed at a position corresponding to the center of each columnar projection 17.
On the back surface of the substrate 12, individually divided back electrodes E2 are provided at positions corresponding to the respective columnar protrusions 17, and each back electrode E2 passes through the hole 12a and forms a barrier layer 13 located on the surface of the substrate 12 at a portion facing the hole 12a. It is necessary to come into contact with.

また相隣する柱状突起１７間においてこれらを相互に電
気的に遮断すべく平板部１１に基盤目状に形成した溝１
８（これと直交する溝は図面には現れていない）はその
溝底が表面電極Ｅ１．上部層１４゜バリア層１３を分断
し基板１２の表面に達するように形成されている。Further, grooves 1 are formed in the flat plate part 11 in the shape of a base line between adjacent columnar projections 17 to electrically isolate them from each other.
8 (the groove orthogonal to this does not appear in the drawing), the groove bottom of which is the surface electrode E1. The upper layer 14 is formed by dividing the barrier layer 13 and reaching the surface of the substrate 12.

他の構成は前記実施例と実質的に同じであり説明を省略
する。The other configurations are substantially the same as those of the previous embodiment, and their explanation will be omitted.

而して上述した如き本発明装置にあっては溝１８が表面
電極Ｅ＋、Ｉ）＋型（又はｎ＋型）領域１５、ｐ型（又
はｎ型）領域１６．バリア層１３のいずれもが分断され
、また裏面電極Ｅ２も各柱状突起１７毎に分断されてい
るから各柱状突起１７は半絶縁性の基板２のみを残して
相互に連結された状態となり相互の電気的な遮断効果が
一層確実となり、誤動作が少なく、そのうえ裏面電極Ｅ
２は柱状突起１７と対応する位置では基板１２を貫通し
て柱状突起１７側に接近位冒せしめであるから柱状突起
１７に対する通電効果も向上する。In the device of the present invention as described above, the groove 18 has the surface electrodes E+, I)+ type (or n+ type) region 15, p type (or n type) region 16, . Since both of the barrier layers 13 are separated and the back electrode E2 is also separated for each columnar protrusion 17, each columnar protrusion 17 is connected to each other with only the semi-insulating substrate 2 remaining. The electrical isolation effect is more reliable, there are fewer malfunctions, and the back electrode E
2 penetrates the substrate 12 and approaches the columnar projection 17 at the position corresponding to the columnar projection 17, so that the effect of conducting current to the pillar projection 17 is also improved.

なお上述の実施例にあっては平板部１．１１、柱状突起
７．１７内の構造はいずれも単純なｐ−ｎ接合構造とな
っている場合を示したが、このような内部構造について
は特に上記した構造にのみ限定するものではなく、例え
ば平板部内に分布型ブラッグ反射鏡を設け、或いは可飽
和光吸収層を具備させ、また柱状突起内を分布帰還構造
成いは多重量子井戸構造とし、更にこの柱状突起内のｐ
−ｎ接合部の長手方向の両側に反射手段を設ける構成と
してもよいことは言うまでもない。In the above embodiment, the structure inside the flat plate part 1.11 and the columnar projection 7.17 is a simple p-n junction structure. The structure is not limited to the above-described structure; for example, a distributed Bragg reflector may be provided within the flat plate portion, or a saturable light absorption layer may be provided, or a distributed feedback structure or multiple quantum well structure may be formed within the columnar protrusion. , furthermore, p in this columnar projection
It goes without saying that reflecting means may be provided on both sides of the -n junction in the longitudinal direction.

〔効果〕〔effect〕

以上の如く本発明装置にあっては、基板に、その表面に
対し垂直な方向に延在するｐ−ｎ接合部を内在させた柱
状突起を多数一体的に集積化すると共に、各柱状突起を
相隣する他の柱状突起から電気的に遮断せしめたから多
数の発光素子を容易に個々独立して制御することが出来
、しかも全体が極めてコンパクトに構成し得るなど本発
明は優れた効果を奏するものである。As described above, in the device of the present invention, a large number of columnar protrusions each having a p-n junction extending in a direction perpendicular to the surface of the substrate are integrally integrated, and each columnar protrusion is Since the light emitting elements are electrically isolated from other adjacent columnar projections, it is possible to easily control a large number of light emitting elements individually and independently, and the whole structure can be extremely compact.The present invention has excellent effects. It is.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明装置の模式的断面図、第２図は第１図の
ｎ−ｎ線による拡大断面図、第３図は柱状突起の部分切
欠拡大斜視図、第４図は本発明の他の実施例を示す拡大
断面図、第５図は従来装置において使用されている面発
光形発光素子の断面構造図である。 １・・・平板部　２・・・基板　３・・・バリア層　４
・・・上部層　５・・・ｐ＋型領領域６・・・ｐ型領域
　７・・・柱状突起　１１・・・平板部　１２・・・基
板　１３・・・バリア層　１４・・・上部層　１５・・
・ｐ＋型領領域１６・・・ｐ型領域　１７・・・柱状突
起　Ｅｌ・・・表面電極　Ｅｌ・・・裏面電極ＰＪ　、
　ＰＮ２−　ｐ　−ｎ接合部 特　許　出願人　　稲　　場　　文　　男外２名FIG. 1 is a schematic sectional view of the device of the present invention, FIG. 2 is an enlarged sectional view taken along line nn in FIG. FIG. 5 is an enlarged sectional view showing another embodiment, and is a sectional structural view of a surface emitting type light emitting element used in a conventional device. 1... Flat plate part 2... Substrate 3... Barrier layer 4
. . . Upper layer 5 .・・・
・p+ type region 16...p type region 17...columnar projection El...surface electrode El...back surface electrode PJ,
PN2-p-n junction patent Applicant: Aya Inaba, male and 2 other persons

Claims (1)

【特許請求の範囲】 １、基板と平行に延在するｐ−ｎ接合部を備えた平板部
と、内部に前記基板と交叉する向きに延在するｐ−ｎ接
合部を備え、前記平板部上に並列形成された複数個の柱
状突起と、前記平板部の裏面側に形成された裏面電極、
並びに平板部の表面側及び柱状突起の側周面にわたって
形成された表面電極と、前記各柱状突起を相互に電気的
に遮断すべく柱状突起間の平板部に形成された溝とを具
備することを特徴とする半導体発光装置。 ２、基板と平行に延在するｐ−ｎ接合部を有する平板部
と、内部に前記基板と交叉する向きに延在するｐ−ｎ接
合部を備え、前記平板部上に並列形成された複数個の柱
状突起と、前記平板部の裏面側に形成され、前記柱状突
起と対応する位置で基板を貫通して柱状突起下に臨ませ
た裏面電極、並びに平板部の表面及び柱状突起の側周面
にわたって形成された表面電極と、前記各柱状突起を相
互に電気的に遮断すべく柱状突起間の平板部にその表面
から基板面に達するよう形成された溝とを具備すること
を特徴とする半導体発光装置。[Scope of Claims] 1. A flat plate portion including a p-n junction extending parallel to the substrate, and a p-n junction extending in a direction intersecting the substrate, the flat plate portion a plurality of columnar projections formed in parallel on the top; a back electrode formed on the back side of the flat plate portion;
and a surface electrode formed over the surface side of the flat plate portion and the side peripheral surface of the columnar projection, and a groove formed in the flat plate portion between the columnar projections to electrically isolate the columnar projections from each other. A semiconductor light emitting device characterized by: 2. A flat plate part having a p-n junction extending parallel to the substrate, and a plurality of p-n junction parts formed in parallel on the flat plate part, each having a p-n junction extending in a direction intersecting the substrate. columnar projections, a back electrode formed on the back side of the flat plate portion, penetrating the substrate at a position corresponding to the columnar projections and facing below the columnar projections, and the surface of the flat plate portion and the side periphery of the columnar projections. It is characterized by comprising a surface electrode formed over the surface, and a groove formed in a flat plate portion between the columnar projections so as to reach from the surface to the substrate surface in order to electrically isolate the columnar projections from each other. Semiconductor light emitting device.