JPS62120355U - - Google Patents

Info

Publication number
JPS62120355U
JPS62120355U JP811886U JP811886U JPS62120355U JP S62120355 U JPS62120355 U JP S62120355U JP 811886 U JP811886 U JP 811886U JP 811886 U JP811886 U JP 811886U JP S62120355 U JPS62120355 U JP S62120355U
Authority
JP
Japan
Prior art keywords
semiconductor device
wiring
radius
utility
scope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP811886U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP811886U priority Critical patent/JPS62120355U/ja
Publication of JPS62120355U publication Critical patent/JPS62120355U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【図面の簡単な説明】
第１図は本考案にかかる配線のコーナー部を示
す図、第２図は半導体チツプの部分平面図、第３
図ａ，ｂは従来の配線のコーナー部を示す図であ
る。 図において、１は電源配線、２は信号配線、１
１は従来の配線、１２は絶縁膜、２１は本考案に
かかる配線、を示している。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体装置の上面に設けた内部配線がコーナー
    部で半径０．５μｍ以上の曲面を有していること
    を特徴とする半導体装置。
JP811886U 1986-01-22 1986-01-22 Pending JPS62120355U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP811886U JPS62120355U (ja) 1986-01-22 1986-01-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP811886U JPS62120355U (ja) 1986-01-22 1986-01-22

Publications (1)

Publication Number Publication Date
JPS62120355U true JPS62120355U (ja) 1987-07-30

Family

ID=30792202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP811886U Pending JPS62120355U (ja) 1986-01-22 1986-01-22

Country Status (1)

Country Link
JP (1) JPS62120355U (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005533367A (ja) * 2001-11-21 2005-11-04 ゼネラル セミコンダクター，インク． パッシベーション層のクラックの発生を防止した集積回路
JP2016174021A (ja) * 2015-03-16 2016-09-29 株式会社東芝 半導体装置
JP2016195286A (ja) * 2010-01-15 2016-11-17 ローム株式会社 半導体装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5389688A (en) * 1977-01-19 1978-08-07 Hitachi Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5389688A (en) * 1977-01-19 1978-08-07 Hitachi Ltd Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005533367A (ja) * 2001-11-21 2005-11-04 ゼネラル セミコンダクター，インク． パッシベーション層のクラックの発生を防止した集積回路
JP2010147498A (ja) * 2001-11-21 2010-07-01 General Semiconductor Inc パッシベーション層のクラックの発生を防止した集積回路の製造方法
JP2016195286A (ja) * 2010-01-15 2016-11-17 ローム株式会社 半導体装置
JP2016174021A (ja) * 2015-03-16 2016-09-29 株式会社東芝 半導体装置
US9899346B2 (en) 2015-03-16 2018-02-20 Kabushiki Kaisha Toshiba Semiconductor device

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