JPS6211227A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6211227A JPS6211227A JP15046385A JP15046385A JPS6211227A JP S6211227 A JPS6211227 A JP S6211227A JP 15046385 A JP15046385 A JP 15046385A JP 15046385 A JP15046385 A JP 15046385A JP S6211227 A JPS6211227 A JP S6211227A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- contact hole
- insulating layer
- cvd
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体基板上の絶縁層に形成したコンタクトホールを該
基板と密着よく穴埋めする方法として、該基板をプラズ
マエツチングにより活性化した後、選択的に化学気相成
長を行う穴埋め方法。[Detailed Description of the Invention] [Summary] As a method for filling contact holes formed in an insulating layer on a semiconductor substrate with good contact with the substrate, the substrate is activated by plasma etching, and then selective chemical vapor deposition is performed. How to fill in the blanks.
本発明は基板と密着性よくコンタクトホールを穴埋めす
る半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device in which contact holes are filled with good adhesion to a substrate.
ＬＳｌ、ＶＬＳＩなどの半導体装置は半導体基板上に絶
縁層を形成した後、写真食刻技術（ホトリソグラフィ或
いは電子線リソグラフィ）を用いて必要位置の絶縁層を
窓開けし、この窓開は部を通して不純物を熱拡散させて
半導体領域を形成するか、或いはイオン注入法により窓
開は部を通して不純物イオンの注入を行うか又は直接に
イオン注入を行って半導体領域が形成される。For semiconductor devices such as LSI and VLSI, after forming an insulating layer on a semiconductor substrate, windows are formed in the insulating layer at necessary positions using photolithography (photolithography or electron beam lithography). A semiconductor region is formed by thermally diffusing impurities, or by implanting impurity ions through the window opening by an ion implantation method, or by directly implanting ions.
次に窓開は部を絶縁被覆した後、必要位置を窓開けして
コンタクトホールを作り、このコンタクトホールを金属
材料で穴埋めして絶縁層の上に電極パターンや配線パタ
ーンを形成し、これにより半導体デバイスが形成されて
いる。Next, after insulating the window opening, open the window at the required position to make a contact hole, fill this contact hole with a metal material, and form an electrode pattern or wiring pattern on the insulating layer. A semiconductor device is formed.
ここで半導体装置は大量の情報を高速処理するために高
集積化が進んでおり、これは基板上の半導体領域や配線
パターンなどを小形化すると共に三次元化することによ
り行われている。Semiconductor devices are becoming highly integrated in order to process large amounts of information at high speed, and this is achieved by downsizing semiconductor regions and wiring patterns on substrates and making them three-dimensional.
例えば基板上に形成されている電極パターンの上に二酸
化硅素（Ｓｉ０２ ）や窒化硅素（Ｓｉ３ Ｎ ４）な
どの絶縁物で絶縁して絶縁層を作り、この上に配線パタ
ーンを形成して基板に形成されている半導体領域と配線
接続する場合がある。For example, an insulating layer is created by insulating an electrode pattern formed on a substrate with an insulating material such as silicon dioxide (Si02) or silicon nitride (Si3N4), a wiring pattern is formed on this, and the wiring pattern is attached to the substrate. There is a case where wiring is connected to the formed semiconductor region.
このような場合、絶縁層を基板の半導体領域に達するま
で選択エツチングしてコンタクトホールを作り、これを
アルミニウム（ＡＩ）などの金属で穴埋めすることによ
り行われているが、穴が深い場合は穴の底面に沿って一
様に金属層を形成し、半導体領域と密着性の良い接触を
保つことは容易ではない。In such cases, contact holes are created by selectively etching the insulating layer until it reaches the semiconductor region of the substrate, and the holes are filled with metal such as aluminum (AI). However, if the holes are deep, It is not easy to uniformly form a metal layer along the bottom surface of the substrate and maintain good contact with the semiconductor region.
コンタクトホールを穴埋めするには化学気相成長法（Ｃ
ｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏｎ法
略してＣＶＤ法）が使用されている。Chemical vapor deposition (C) is used to fill contact holes.
A chemical vapor deposition method (abbreviated as CVD method) is used.
第３図はシリコン（Ｓｉ）半導体基板（以下略して基板
）に形成されている半導体領域２に絶縁層３を選択エツ
チングしてコンタクトホール４を作り、これにＣＶＤ法
によりＡＩ５を析出させて穴埋めを行った状態を示して
いる。Figure 3 shows that a contact hole 4 is created by selectively etching an insulating layer 3 in a semiconductor region 2 formed on a silicon (Si) semiconductor substrate (hereinafter referred to as the substrate), and then AI5 is deposited in the hole by the CVD method to fill the hole. This shows the state in which the following steps have been performed.
すなわち、絶縁層３に形成されている直径が１μｍ程度
のコンタクトホール４を穴埋めするのに真空蒸着法やス
パッタ法などの方法を使用すると、蒸発源或いは陰極タ
ーゲットから金属粒子が直線状に飛散するため、コンタ
クトホール４の内部に均一に膜形成させることは不可能
であり、そのために基板上で反応ガスを熱分解させて析
出させるＣＶＯ法が用いられている。That is, when a method such as a vacuum evaporation method or a sputtering method is used to fill a contact hole 4 having a diameter of about 1 μm formed in an insulating layer 3, metal particles are scattered in a straight line from an evaporation source or a cathode target. Therefore, it is impossible to uniformly form a film inside the contact hole 4, and for this reason, a CVO method is used in which reactive gas is thermally decomposed on the substrate to deposit it.
然しなから従来のように絶縁層３の厚さが１μｍ程度で
コンタクトホール４の直径が１μｍ以上ある場合には差
支えないが、先に記したように三次元の高密度化が行わ
れると、絶縁層３の厚さが２〜３μｍにもなり、一方コ
ンタクトホール４の径が１μｍ程度と狭いので、ＣＶＤ
法を用いても半導体領域２とコンタクトホールの底部で
充分に接触することは難しく、隙間６などを生じて低抵
抗な導通を得ることは困難となっている。However, there is no problem when the thickness of the insulating layer 3 is about 1 μm and the diameter of the contact hole 4 is 1 μm or more as in the conventional case, but when three-dimensional densification is performed as described above, The thickness of the insulating layer 3 is 2 to 3 μm, and the diameter of the contact hole 4 is narrow, about 1 μm, so CVD
Even if a method is used, it is difficult to make sufficient contact with the semiconductor region 2 at the bottom of the contact hole, and a gap 6 is created, making it difficult to obtain low-resistance conduction.
そこでこのように段差が高く且つ微細なコンタクトホー
ルを穴埋めする技術を確立する必要がある。Therefore, it is necessary to establish a technique for filling such a fine contact hole with a high level difference.
以上説明したように三次元デバイスにおいては高段差の
コンタクトホールを穴埋めし、基板の半導体領域と低抵
抗の導通路を作る必要があるが、コンタクトホールの底
部にＣＶＤ膜を如何にして密着して形成するかが問題で
ある。As explained above, in three-dimensional devices, it is necessary to fill contact holes with high height differences and create a low-resistance conductive path with the semiconductor region of the substrate. The question is whether to form one.
上記の問題は半導体領域上の絶縁層に形成した高段差の
コンタクトホールにアルミニウムを選択成長せしめ、該
半導体領域と密着性よく穴埋めを行う方法として、被処
理半導体基板を塩化硼素ガス雰囲気中でプラズマエツチ
ングしてコンタクトホール底部の半導体領域を活性化せ
しめた後、アルミニウムを主構成分とする反応ガスを用
いて化学気相成長を行い、コンタクトホール底部の活性
化領域に選択的にアルミニウムを成長せしめて穴埋めを
行うことを特徴とする半導体装置の製造方法により解決
することができる。The above problem can be solved by selectively growing aluminum into contact holes with high height differences formed in an insulating layer on a semiconductor region, and filling the hole with good adhesion to the semiconductor region. After etching to activate the semiconductor region at the bottom of the contact hole, chemical vapor deposition is performed using a reactive gas containing aluminum as a main component to selectively grow aluminum in the activated region at the bottom of the contact hole. This problem can be solved by a semiconductor device manufacturing method characterized in that the holes are filled by using the same method.
本発明はＣＶＯ法で金属などの導体層を形成する場合に
酸化物などの絶縁層上よりもＳｉ基板上のほうが析出が
起こり易いのを利用し、プラズマエツチングによりコン
タクトホールの底の基板を活性化し、選択的にコンタク
トホールの底からＣＶＤ０層成長が起こるようにしたも
のである。The present invention takes advantage of the fact that when a conductive layer of metal or the like is formed using the CVO method, precipitation occurs more easily on a Si substrate than on an insulating layer such as an oxide, and activates the substrate at the bottom of the contact hole by plasma etching. The CVD layer is grown selectively from the bottom of the contact hole.
このような前処理を行って後ＣＶＤ処理を行えば基板と
の密着性のよい穴埋めが可能となる。If such pretreatment is performed and then CVD treatment is performed, it becomes possible to fill holes with good adhesion to the substrate.
〔実施例〕
第２図は本発明を実施するのに使用したプラズマエツチ
ング兼ＣｖＤ装置の断面図、また第１図（Ａ）〜（Ｃ）
は本発明の詳細な説明する断面図である。[Example] Figure 2 is a sectional view of a plasma etching/CvD apparatus used to carry out the present invention, and Figures 1 (A) to (C)
FIG. 2 is a cross-sectional view illustrating the present invention in detail.
本発明はプラズマエツチングによってコンタクトホール
底部の基板面を活性化し、この活性面にＣＶＤ成長が起
こり易い性質を利用するものであるからＣＶＤの析出が
起こるまで活性状態を維持しておくことが必要であり、
そのため同一装置を切り換えてプラズマエツチングとＣ
ＶＤ成長とを引き続いて行う必要がある。The present invention activates the substrate surface at the bottom of the contact hole by plasma etching and utilizes the property that CVD growth easily occurs on this active surface, so it is necessary to maintain the active state until CVD precipitation occurs. can be,
Therefore, we changed the same equipment to perform plasma etching and C.
It is necessary to continue with VD growth.
以下導体としてＡｌを用いる場合について本発明を説明
する。The present invention will be described below with reference to the case where Al is used as the conductor.
第１図（Ａ）は半導体領域２を備えた基板１の上に熱処
理或いはこれとＣＶＤとの併用により厚さ４〜５μｍと
厚いＳｉＯ２絶縁層７を形成し、これをリアクティブイ
オンエツチング（Ｒｅａｃｔｉｖｅ−ｉｏｎＥｔｃｈｉ
ｎｇ 略してＲＩＥ）などのドライエツチングを施し
て半導体領域２に達するコンタクトホール４を形成した
状態を示す断面図であって、コンタクトホール４の底に
はＳｉ基板が現れているが、このＳｉ基板面は空気に触
れると空気中の酸素（０２）により容易に酸化され、Ｓ
ｉＯ２よりなる厚さ数１０人の不動態被膜が表面に形成
されている。In FIG. 1(A), a thick SiO2 insulating layer 7 with a thickness of 4 to 5 μm is formed on a substrate 1 having a semiconductor region 2 by heat treatment or a combination of this and CVD, and this is then etched by reactive ion etching (reactive ion etching). -ionEtchi
ng is a cross-sectional view showing a state in which a contact hole 4 reaching a semiconductor region 2 has been formed by dry etching such as RIE, and a Si substrate is exposed at the bottom of the contact hole 4. When the surface comes into contact with air, it is easily oxidized by oxygen (02) in the air, and S
A passive film made of iO2 and having a thickness of several tens of layers is formed on the surface.
本発明を実施するにはコンタクトホール４の形成が終わ
った基板ｌを第２図に示すプラズマエツチング兼ＣＶＤ
装置のサセプタ８の上に載置し、排気系を動作して装置
内を排気した後、シャワー９から塩化硼素（ＢＣＩ ３
）ガスを供給し、装置内の気圧を０．３〜１．０ Ｔ
ｏｒｒに保持した状態で高周波電源１０よりシャワー９
とサセプタ８との間に高周波電界を加えて基板１を２〜
３分に互ってプラズマエツチングを行う。To carry out the present invention, the substrate 1 on which the contact hole 4 has been formed is subjected to plasma etching/CVD as shown in FIG.
After placing the device on the susceptor 8 and operating the exhaust system to exhaust the inside of the device, boron chloride (BCI 3
) Supply gas and reduce the pressure inside the device to 0.3 to 1.0 T.
Shower 9 from high frequency power supply 10 while held at orr.
A high frequency electric field is applied between the substrate 1 and the susceptor 8 to
Plasma etching is performed for 3 minutes at a time.
このプラズマエツチングにより第１図（Ｂ）に示すよう
にコンタクトホール４の底の不動態被膜は除去され、半
導体領域２の活性面１１が現れる。By this plasma etching, the passive film at the bottom of the contact hole 4 is removed, and the active surface 11 of the semiconductor region 2 is exposed, as shown in FIG. 1(B).
プラズマエツチング終了の後は第２図の装置において供
給ガスを切り換え、反応ガスとしてトリイソブチルアル
ミニウム（Ａｌ （ＣＩＩ２ ＣＩ（ＣＨ３） ２）３
〕を用い、キャリアガスとしてアルゴン（Ａｒ）を、ま
た分解促進ガスとして水素（Ｈ２）をシャワー９から供
給し、排気装置により装置内の真空度を０．３〜１．Ｑ
Ｔｏｒｒに保ちながらヒータ１２に通電 □し、
基板１の温度を約３００℃に加熱することにより（Ａｌ
（ＣＨ２ＣＨ（ＣＨ３） ｚ ） ３ ）を分解せし
め、基板１の上でＣＶＤ反応を起こさせる。After the plasma etching is completed, the supply gas is switched in the apparatus shown in Fig. 2, and triisobutylaluminum (Al (CII2 CI(CH3) 2) 3 is used as the reaction gas.
], argon (Ar) is used as a carrier gas, and hydrogen (H2) is supplied as a decomposition accelerating gas from the shower 9, and the degree of vacuum in the apparatus is maintained at 0.3-1. Q
While maintaining the Torr, energize the heater 12 □,
By heating the substrate 1 to approximately 300°C (Al
(CH2CH(CH3) z ) 3 ) is decomposed and a CVD reaction is caused on the substrate 1.
ここで先に第１図（Ｂ）で説明したようにコンタクトホ
ール４の底部は活性化されているためにＣＶＤ成長は第
１図（Ｃ）に示すようにこの活性面１１から優先的に成
長し、コンタクトホール４を埋めて後、Ｓｉ０２絶縁層
７の上にＡＩの成長が行われることになる。Since the bottom of the contact hole 4 is activated as previously explained with reference to FIG. 1(B), the CVD growth preferentially grows from this active surface 11 as shown in FIG. 1(C). After filling the contact hole 4, AI will be grown on the Si02 insulating layer 7.
以下は従来と同様であって、約１μｍの膜厚にまでＡ１
層５を形成し、これに写真食刻技術を適用して電極や配
線パターンなどの微細パターンを形成すればよい。The following is the same as before, and A1 up to a film thickness of about 1 μm.
The layer 5 may be formed, and a fine pattern such as an electrode or a wiring pattern may be formed thereon by applying a photolithography technique.
このようにコンタクトホール４の底の活性面１１から導
電層の成長が起こるようにすることより理想的なコンタ
クトホール４の穴埋めを行うことができる。By allowing the conductive layer to grow from the active surface 11 at the bottom of the contact hole 4 in this manner, the contact hole 4 can be ideally filled.
以上説明したように本発明の実施により、従来のような
隙間の発生はなく、コンタクトホールの低抵抗な穴埋め
が可能となる。As explained above, by carrying out the present invention, there is no generation of gaps as in the conventional method, and contact holes can be filled with low resistance.
第１図（Ａ）〜（Ｃ）は本発明の詳細な説明する断面図
で、同図（Ａ）はコンタクトホール形成後、同図（Ｂ）
はプラズマエツチング後、同図（Ｃ）は選択成長中の状
態図、
第２図はプラズマエツチング兼ＣＶＤ装置の断面図、
第３図は従来のＣＶＤ成長後の断面図、である。
図において、
ｌは基板、 ２は半導体領域、３は絶縁層
、 ４はコンタクトホール、５はへ１層、
６は隙間、７はＳｉＯ２絶縁層、 ９
はシャワー、１１は活性面、FIGS. 1(A) to 1(C) are cross-sectional views explaining the present invention in detail, and FIG. 1(A) shows the state after forming the contact hole.
2 is a state diagram after plasma etching, FIG. 2C is a state diagram during selective growth, FIG. 2 is a cross-sectional view of the plasma etching/CVD apparatus, and FIG. 3 is a cross-sectional view after conventional CVD growth. In the figure, l is the substrate, 2 is the semiconductor region, 3 is the insulating layer, 4 is the contact hole, 5 is the first layer,
6 is a gap, 7 is a SiO2 insulating layer, 9
is the shower, 11 is the active surface,
Claims (1)
コンタクトホール（４）内に導電層形成金属を選択成長
せしめ、該半導体領域（２）と密着性よく穴埋めを行う
方法として、被処理半導体基板（１）を予めプラズマエ
ッチングしてコンタクトホール（４）底部の半導体領域
（２）を活性化せしめた後、前記導電層形成金属を主構
成分とする反応ガスを用いて化学気相成長を行い、コン
タクトホール（４）底部の活性化領域（２）上に選択的
に導電層を成長せしめる工程を含むことを特徴とする半
導体装置の製造方法。As a method of selectively growing a conductive layer forming metal in a contact hole (4) with a high level difference formed in an insulating layer (7) on a semiconductor region (2), and filling the hole with good adhesion to the semiconductor region (2), After plasma etching the semiconductor substrate (1) to be processed in advance to activate the semiconductor region (2) at the bottom of the contact hole (4), chemical A method for manufacturing a semiconductor device, comprising the step of performing phase growth to selectively grow a conductive layer on an active region (2) at the bottom of a contact hole (4).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15046385A JPS6211227A (en) | 1985-07-09 | 1985-07-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15046385A JPS6211227A (en) | 1985-07-09 | 1985-07-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6211227A true JPS6211227A (en) | 1987-01-20 |
Family
ID=15497466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15046385A Pending JPS6211227A (en) | 1985-07-09 | 1985-07-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6211227A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6333569A (en) * | 1986-07-25 | 1988-02-13 | Nippon Telegr & Teleph Corp <Ntt> | Production of thin metallic film |
| US5180687A (en) * | 1989-09-26 | 1993-01-19 | Canon Kabushiki Kaisha | Deposited film formation method utilizing selective deposition by use of alkyl aluminum hydride |
| US5316972A (en) * | 1989-09-26 | 1994-05-31 | Canon Kabushiki Kaisha | Process for forming deposited film by use of alkyl aluminum hydride and process for preparing semiconductor device |
| US5637534A (en) * | 1992-12-25 | 1997-06-10 | Kawasaki Steel Corporation | Method of manufacturing semiconductor device having multilevel interconnection structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54154291A (en) * | 1978-05-25 | 1979-12-05 | Itt | Method of forming aliminum conductor path |
-
1985
- 1985-07-09 JP JP15046385A patent/JPS6211227A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54154291A (en) * | 1978-05-25 | 1979-12-05 | Itt | Method of forming aliminum conductor path |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6333569A (en) * | 1986-07-25 | 1988-02-13 | Nippon Telegr & Teleph Corp <Ntt> | Production of thin metallic film |
| US5180687A (en) * | 1989-09-26 | 1993-01-19 | Canon Kabushiki Kaisha | Deposited film formation method utilizing selective deposition by use of alkyl aluminum hydride |
| US5316972A (en) * | 1989-09-26 | 1994-05-31 | Canon Kabushiki Kaisha | Process for forming deposited film by use of alkyl aluminum hydride and process for preparing semiconductor device |
| US5637534A (en) * | 1992-12-25 | 1997-06-10 | Kawasaki Steel Corporation | Method of manufacturing semiconductor device having multilevel interconnection structure |
| US5952723A (en) * | 1992-12-25 | 1999-09-14 | Kawasaki Steel Corporation | Semiconductor device having a multilevel interconnection structure |
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