JPS61139026A - Production of semiconductor device - Google Patents
Production of semiconductor deviceInfo
- Publication number
- JPS61139026A JPS61139026A JP26233584A JP26233584A JPS61139026A JP S61139026 A JPS61139026 A JP S61139026A JP 26233584 A JP26233584 A JP 26233584A JP 26233584 A JP26233584 A JP 26233584A JP S61139026 A JPS61139026 A JP S61139026A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- silicon film
- tungsten
- conductive polycrystalline
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 24
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 24
- 239000010937 tungsten Substances 0.000 claims abstract description 24
- 238000007788 roughening Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- -1 silicon ions Chemical class 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000012535 impurity Substances 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 5
- 239000013078 crystal Substances 0.000 abstract description 2
- 230000007547 defect Effects 0.000 abstract description 2
- 238000001312 dry etching Methods 0.000 abstract description 2
- 239000007788 liquid Substances 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 239000002245 particle Substances 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 9
- 239000005360 phosphosilicate glass Substances 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- WGLPBDUCMAPZCE-UHFFFAOYSA-N Trioxochromium Chemical compound O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- GVGCUCJTUSOZKP-UHFFFAOYSA-N nitrogen trifluoride Chemical compound FN(F)F GVGCUCJTUSOZKP-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 102220043690 rs1049562 Human genes 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体装置の製造方法にかかり、特に接続電換
の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a connection converter.
周知のように半導体集積回路（ＩＣ）などの半導体装置
においでは、半導体基板上に半導体素子や抵抗等の素子
が形成されて、これらの電極から導出する配線層、ある
いは電極間を接続する配線層が表面に多数設けられてい
る。As is well known, in semiconductor devices such as semiconductor integrated circuits (ICs), elements such as semiconductor elements and resistors are formed on a semiconductor substrate, and wiring layers lead out from these electrodes or interconnect layers connecting between the electrodes. are provided in large numbers on the surface.
その配線層には、従前からアルミニウム（＾１）膜また
はその合金膜が用いられており、これはアルミニウムが
半導体基板とのオーミックコンタクトが容易に得られ、
二酸化シリコン（Ｓｉ０２ ） ｔｌＱとの密着がよい
高電導度材料であるからである。For the wiring layer, an aluminum (^1) film or an alloy film thereof has been used for a long time, and this is because aluminum can easily make ohmic contact with the semiconductor substrate.
This is because silicon dioxide (Si02) is a highly conductive material that has good adhesion to tlQ.
しかし、アルミニウムは熔融点の低いのが欠点で、その
ためにＩＣを高密度化して、その上面に多層配線層を積
層する場合には絶縁膜の形成等に制約があった。However, the disadvantage of aluminum is that it has a low melting point, which imposes restrictions on the formation of an insulating film, etc. when increasing the density of an IC and stacking a multilayer wiring layer on its top surface.
従って、それに代わる配線層として導電性多結晶シリコ
ン膜が使用されており、また、モリブデン（ＭＯ）やタ
ングステン（Ｗ）などの高融点金属や、そのシリサイド
膜も使用されている。Therefore, a conductive polycrystalline silicon film is used as an alternative wiring layer, and high melting point metals such as molybdenum (MO) and tungsten (W) and their silicide films are also used.
このような導電性多結晶シリコン膜や高融点金属膜は、
絶縁膜を介した形成が容易で、且つ、表面が平坦化し易
く、多層配線の作成に好適なものであるが、その被着並
びにパターンニングは出来るだけ簡易に形成され、その
品質や信頼度の高いことが要望されている。Such conductive polycrystalline silicon films and high melting point metal films are
It is easy to form via an insulating film, and the surface is easy to flatten, making it suitable for creating multilayer wiring. However, its deposition and patterning must be as simple as possible, and its quality and reliability cannot be improved. There is a high demand.
［従来の技術］
第３図は半導体装置における従来の一例の電極および配
線層部分の断面図を示しており、１はｐ型シリコン基板
、２はｎ型領域、３は燐珪酸ガラス（Ｐ Ｓ Ｇ）膜か
らなる絶縁膜、４．６はｎ型多結晶シリコン膜、５，７
はタングステン膜で、本例は電極窓８の内部をｎ型多結
晶シリコン膜４とタンゲステレ膜５とで充填し、その上
にｎ型多結晶シリコン膜６とタングステン膜７からなる
複合膜で配線層を形成した平坦化配線構造である。[Prior Art] FIG. 3 shows a cross-sectional view of an electrode and wiring layer portion of a conventional example of a semiconductor device, in which 1 is a p-type silicon substrate, 2 is an n-type region, and 3 is a phosphosilicate glass (PS). G) An insulating film consisting of a film, 4.6 is an n-type polycrystalline silicon film, 5, 7
is a tungsten film, and in this example, the inside of the electrode window 8 is filled with an n-type polycrystalline silicon film 4 and a tungsten film 5, and on top of that, a composite film consisting of an n-type polycrystalline silicon film 6 and a tungsten film 7 is used for wiring. This is a planarized wiring structure in which layers are formed.
このような複合膜配線に形成すると、そのままでも十分
な高電導度を有し、且つ、絶縁膜との密着性も良いが、
熱処理すればタングステンシリサイド（ＷＳｉ） 、あ
るいはタングステン主体の配線層に変成される利点があ
る。When formed into such a composite film wiring, it has sufficient high conductivity as it is and also has good adhesion with the insulating film.
It has the advantage of being transformed into tungsten silicide (WSi) or a tungsten-based wiring layer by heat treatment.
更に、本構造は、その形成方法に大きな特徴を有してお
り、第４図（ａ）〜（ｅ）にその工程順断面図を示して
いる。Furthermore, this structure has a major feature in its formation method, and FIGS. 4(a) to 4(e) show cross-sectional views in the order of steps.
まず、第４図（ａ）はｎ型領域２が設けられたＰ型シリ
コン基板ｌに膜厚１μｍ程度のＰＳＧ膜３を被着し、そ
のＰＳＧ膜３に公知の方法で窓あけして電極窓８を形成
した工程断面図である。First, in FIG. 4(a), a PSG film 3 with a thickness of about 1 μm is deposited on a P-type silicon substrate l provided with an n-type region 2, and a window is formed in the PSG film 3 by a known method to form an electrode. FIG. 8 is a cross-sectional view showing a process in which a window 8 is formed.
次いで、第４図山）に示すように上面にｎ型多結晶シリ
コンＩ！ｌＩ４を化学気相成長（ＣＶ Ｄ）法で被着す
る。このｎ型多結晶シリコン膜４の被着は、モノシラン
（ＳｉＨ４）とホスフィン（ＰＨ３）とを６２０℃で分
解させて被着させる方法が採られる。Next, as shown in Fig. 4, n-type polycrystalline silicon I! is deposited on the top surface. lI4 is deposited by chemical vapor deposition (CVD). The n-type polycrystalline silicon film 4 is deposited by a method of decomposing monosilane (SiH4) and phosphine (PH3) at 620°C.
次いで、第４図（Ｃ）に示すように、電極窓８をレジス
ト膜マスク（図示せず）で被覆し、ＰＳＧｌ＊３の上面
に被着しているｎ型多結晶シリコン膜４を、フレオン（
ＣＦ４）ガスを用いたドライエツチングで除去す、る。Next, as shown in FIG. 4(C), the electrode window 8 is covered with a resist film mask (not shown), and the n-type polycrystalline silicon film 4 deposited on the upper surface of the PSGl*3 is coated with Freon. (
Remove by dry etching using CF4) gas.
次いで、レジスト膜マスクを除去した後、第４図（ｄｌ
に示すように、ＣＶＤ法によって電極窓８内のｎ型多結
晶シリコン膜４上にのみ、タングステン膜５を選択的に
被着する。このＣＶＤ法による多結晶シリコン膜上への
タングステン膜の選択形成は、既に公知となっており、
ＣＶＤ装置の反応室の温度を３２５℃に保持し、窒素（
Ｎ２）ガス又はアルゴン（＾ｒ）ガスをキャリアガスと
した六弗化タングステン（ＷＦ６）ガスを流入して、分
解被着させる。そうすると、多結晶シリコン膜上にのみ
タングステン膜を選択的に成長することができる。それ
は ＷＦ６ ＋５ｉ＝Ｗ＋ＳｉＦ４なる反応式によっ
てＳｉ Ｆ ４が生成され、その触媒作用によって選択
的に成長するものと考えられている。従って、図示のよ
うに、やがて電極窓８は埋没されて、電極とＰＳＧ膜と
が同一平面になって平坦化される。Next, after removing the resist film mask, the process shown in FIG.
As shown in FIG. 2, a tungsten film 5 is selectively deposited only on the n-type polycrystalline silicon film 4 within the electrode window 8 by the CVD method. The selective formation of a tungsten film on a polycrystalline silicon film by this CVD method is already well known.
The temperature of the reaction chamber of the CVD device was maintained at 325°C, and nitrogen (
Tungsten hexafluoride (WF6) gas using N2) gas or argon (^r) gas as a carrier gas is introduced to cause decomposition and deposition. Then, the tungsten film can be selectively grown only on the polycrystalline silicon film. It is believed that Si F 4 is produced by the reaction formula: WF6 + 5i = W + SiF 4, and selectively grows due to its catalytic action. Therefore, as shown in the figure, the electrode window 8 is eventually buried, and the electrode and the PSG film are flattened to be on the same plane.
次いで、第４図（ｅ）に示すように、再び、ＣＶＤ法を
用いて、平坦化したｐｓｃＭｔｉ３とタングステン膜５
との上面に、ｎ型多結晶シリコン膜６を被着させる。Next, as shown in FIG. 4(e), the planarized pscMti3 and tungsten film 5 are deposited again using the CVD method.
An n-type polycrystalline silicon film 6 is deposited on the upper surface of the substrate.
次いで、そのｎ型多結晶シリコン膜６の上に、上記と同
様にしてタングステン膜７を選択的に成長し、更に、こ
れをパターンニングして、第３図に示す電極および配線
の構造に仕上げる。Next, a tungsten film 7 is selectively grown on the n-type polycrystalline silicon film 6 in the same manner as described above, and this is further patterned to obtain the electrode and wiring structure shown in FIG. .
このように、本構造は多結晶シリコン膜へのタングステ
ン膜の選択成長法が通用できるため、その形成方法もフ
ォトプロセス工程が少なくなって簡素化される。As described above, since the selective growth method of a tungsten film on a polycrystalline silicon film can be applied to this structure, the formation method is also simplified by reducing the number of photo process steps.
［発明が解決しようとする問題点］
ところが、この多結晶シリコン膜へのタングステン膜の
選択成長は、必ずしも満足なものではなく、その成長速
度も数１０人／分程度と大変遅く、且つ、ＰＳＧ膜上べ
の成長も皆無にはならない欠点がある。[Problems to be Solved by the Invention] However, this selective growth of a tungsten film on a polycrystalline silicon film is not necessarily satisfactory, and the growth rate is very slow at about several tens of people/minute, and the PSG There is also a drawback that growth on the film cannot be completely eliminated.
本発明はこのような問題点を減少させて、一層容易にタ
ングステンが多結晶シリコン上に選択成長される形成方
法を提案するものである。The present invention reduces these problems and proposes a method of forming tungsten that can be selectively grown on polycrystalline silicon more easily.
［問題点を解決するための手段］
その問題は、半導体基板上の絶縁膜に形成された電極窓
の底面に導電性多結晶シリコン膜を被着し、次いで該導
電性多結晶シリコン膜の表面を粗面処理した後、該導電
性多結晶シリコン膜上にタングステンを選択的に被着さ
せる工程が含まれる半導体装置の製造方法によって解決
される。[Means for solving the problem] The problem is that a conductive polycrystalline silicon film is deposited on the bottom surface of an electrode window formed in an insulating film on a semiconductor substrate, and then the surface of the conductive polycrystalline silicon film is The problem is solved by a method of manufacturing a semiconductor device that includes a step of selectively depositing tungsten on the conductive polycrystalline silicon film after roughening the surface of the conductive polycrystalline silicon film.
その粗面処理には、例えば、露出させた導電性多結晶シ
リコン膜を、弗酸を含む溶液でウェットエツチングした
り、弗素ガスを含む反応ガスでプラズマエツチングした
り、あるいは、導電性多結晶シリコン膜に含まれるシリ
コンイオンや不純物イオンを注入したりする方法を用い
る。To roughen the surface, for example, the exposed conductive polycrystalline silicon film may be wet etched with a solution containing hydrofluoric acid, plasma etched with a reactive gas containing fluorine gas, or the conductive polycrystalline silicon film A method such as implanting silicon ions or impurity ions contained in the film is used.
［作用］
卯ち、本発明は、選択成長させる多結晶シリコン膜の表
面を、粗い凹凸ある面にして、タングステン成長核が発
生し易くした後、選択成長させて、その選択成長を容易
にするものである。[Function] First, in the present invention, the surface of the polycrystalline silicon film to be selectively grown is made rough and uneven so that tungsten growth nuclei are easily generated, and then selective growth is performed to facilitate the selective growth. It is something.
［実施例］ 以下、実施例によって詳細に説明する。[Example] Examples will be described in detail below.
本発明にがかる粗面処理は、上記に説明した第４図の工
程順図において、同図ｆｃ）に示す工程後に行なわれる
ものである。The surface roughening treatment according to the present invention is performed after the step shown in fc) in the process sequence diagram of FIG. 4 explained above.
今、第１図（ａｌ、 （ｂ）にその粗面処理を行なった
工程断面図を示している。Now, FIGS. 1A and 1B show cross-sectional views of the process in which the surface roughening treatment was performed.
上記した第４図（Ｃ）に示す工程断面図のように、ドラ
イエツチングして、電極窓８内のｎ型多結晶シリコンＩ
ｆ９１！４のみを残存させた後、第１図（ａｌに示すよ
うに、レジスト膜マスク１０を全面に被覆して、ｎ型多
結晶シリコン膜４のみ露出させ、これをエツチング液に
浸漬して、その多結晶シリコン膜の表面をエツチングし
て粗面にする。As shown in the cross-sectional view of the process shown in FIG.
After leaving only the f91!4 remaining, as shown in FIG. , the surface of the polycrystalline silicon film is etched to make it rough.
このウエノトエノチンダ液は、例えば
ＨＦ ： Ｋ２ Ｃｒ２０７ （０，１５Ｍ０Ｉχ）
＝ １００ｃｃ ： ５０ｃｃあるいは、
ＨＦ ：ＣｒＯ３： Ｈ２０＝１００ｃｃ ：５０ｇ
： １００ｃｃ等を用いる。This uenotoenochinda liquid is, for example, HF: K2 Cr207 (0,15M0Iχ)
= 100cc: 50cc or HF:CrO3:H20=100cc: 50g
: Use 100cc etc.
そうすれば、多結晶シリコン膜４“は、その表面の結晶
欠陥部分や粒子境界部分が、特にエツチングで荒らされ
、凹凸が激しくなって、ギザギザになった粗面がえられ
る。Then, the crystal defect portions and grain boundary portions on the surface of the polycrystalline silicon film 4'' are roughened, especially by etching, and the unevenness becomes severe, resulting in a jagged rough surface.
次いで、第１５図（ｂｌに示すように、レジスｌ−１’
Ｊマスク１０を除去し、上記の選択成長法によって多結
晶シリコン膜４“の上にタングステン膜５を成長する。Then, as shown in FIG. 15 (bl), register l-1'
J mask 10 is removed and tungsten film 5 is grown on polycrystalline silicon film 4'' by the selective growth method described above.
そうすると、タングステンの核が速く、しかも、多数発
生して、成長速度が速まる。その反面、ＰＳＧ膜３上へ
のタングステンの被着も減少する。As a result, tungsten nuclei are generated quickly and in large numbers, increasing the growth rate. On the other hand, the adhesion of tungsten onto the PSG film 3 is also reduced.
なお、ウェットエツチングの代わりに、プラズマエツチ
ングを行なっても良い。エツチングガスとしては、ＣＦ
４ （四弗化炭素）ガスやＮＦ３ （三弗化窒素）が
適当である。Note that plasma etching may be performed instead of wet etching. As an etching gas, CF
4 (carbon tetrafluoride) gas and NF3 (nitrogen trifluoride) gas are suitable.
更に、イオン注入法によって、多結晶シリコン膜４の表
面を叩いて粗くすることもできる。その場合、注入イオ
ンとしては、シリコンイオンや燐イオンなどの多結晶シ
リコン膜に含まれる元素が好ましい。Furthermore, the surface of the polycrystalline silicon film 4 can be roughened by pounding it by ion implantation. In this case, the implanted ions are preferably elements contained in the polycrystalline silicon film, such as silicon ions or phosphorus ions.
同様に、このような粗面処理を、第４図（ｅｌに示す工
程後にも行なって、多結晶シリコン膜６°の上にタング
ステン膜７を選択成長し、第２図に示す配線構造に仕上
げる。かようにすれば、多結晶シリコン膜上へのタング
ステン膜の選択成長を、より完全に、且つ、より速く行
なうことができる。Similarly, such surface roughening treatment is carried out after the step shown in FIG. In this way, the tungsten film can be selectively grown on the polycrystalline silicon film more completely and more quickly.
［発明の効果］
以上の実施例の説明から明らかなように、本発明によれ
ば、選択成長による配線構造の形成が一層容易になり、
ＩＣの品質並びに信頼性の向上に好影響を与えるもので
ある。[Effects of the Invention] As is clear from the description of the embodiments above, according to the present invention, it becomes easier to form a wiring structure by selective growth.
This has a positive effect on improving the quality and reliability of the IC.
第１図（ａ）、 （ｂｌは本発明にかかる工程順断面図
、第２図は本発明にかかる配線構造図、
第３図は従来の配線構造図、
第４図（ａｌ〜（ｅ）ば従来の工程順断面図である。
図において、
■はＰ型シリコン基板、２はｎ型領域、３はｐｓｃ膜、
４．６はｎ型多結晶シリコン膜、
４゛ ６゛は′■而面理し７た多結晶・２・リコン股５
．７はタ／ゲコテン膜、
８は１ｉｉ窓−、１０はレジスｌ−１ｔ’；ｌ！下マス
クを示している。
第１図
第 ２ ロ
ア
第３図
、−
第４図
第４図1(a), (bl is a cross-sectional view of the process according to the present invention, FIG. 2 is a wiring structure diagram according to the present invention, FIG. 3 is a conventional wiring structure diagram, and FIG. 4 (al to (e)) This is a cross-sectional view of a conventional process in the order of steps. Faceted 7 polycrystalline 2. Recon crotch 5
．． 7 is a T/Gecoten film, 8 is a 1ii window, and 10 is a resist l-1t'; l! Showing the bottom mask. Figure 1 Figure 2 Lower Figure 3, - Figure 4 Figure 4
Claims (4)
に導電性多結晶シリコン膜を被着し、次いで該導電性多
結晶シリコン膜の表面を粗面処理した後、該導電性多結
晶シリコン膜上にタングステンを選択的に被着させる工
程が含まれてなることを特徴とする半導体装置の製造方
法。(1) A conductive polycrystalline silicon film is deposited on the bottom surface of an electrode window formed in an insulating film on a semiconductor substrate, and then the surface of the conductive polycrystalline silicon film is roughened, and then the conductive polycrystalline silicon film is roughened. A method for manufacturing a semiconductor device, comprising the step of selectively depositing tungsten on a crystalline silicon film.
シリコン膜を、弗酸を含む溶液でウェットエッチングす
る工程が含まれてなることを特徴とする特許請求の範囲
第１項記載の半導体装置の製造方法。(2) The surface roughening treatment includes a step of wet etching the exposed conductive polycrystalline silicon film with a solution containing hydrofluoric acid. A method for manufacturing a semiconductor device.
シリコン膜を、弗素ガスを含む反応ガスでプラズマエッ
チングする工程が含まれてなることを特徴とする特許請
求の範囲第１項記載の半導体装置の製造方法。(3) The surface roughening treatment includes a step of plasma etching the exposed conductive polycrystalline silicon film with a reactive gas containing fluorine gas. A method for manufacturing a semiconductor device.
シリコン膜に、該導電性多結晶シリコン膜に含まれるシ
リコンイオン、または不純物イオンを注入する工程が含
まれてなることを特徴とする特許請求の範囲第１項記載
の半導体装置の製造方法。(4) The surface roughening treatment is characterized by including a step of implanting silicon ions contained in the conductive polycrystalline silicon film or impurity ions into the exposed conductive polycrystalline silicon film. A method for manufacturing a semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26233584A JPS61139026A (en) | 1984-12-11 | 1984-12-11 | Production of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26233584A JPS61139026A (en) | 1984-12-11 | 1984-12-11 | Production of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61139026A true JPS61139026A (en) | 1986-06-26 |
Family
ID=17374329
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26233584A Pending JPS61139026A (en) | 1984-12-11 | 1984-12-11 | Production of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61139026A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4963511A (en) * | 1987-11-30 | 1990-10-16 | Texas Instruments Incorporated | Method of reducing tungsten selectivity to a contact sidewall |
| US4983543A (en) * | 1988-09-07 | 1991-01-08 | Fujitsu Limited | Method of manufacturing a semiconductor integrated circuit having an interconnection wire embedded in a protective layer covering the semiconductor integrated circuit |
| US5110762A (en) * | 1988-07-07 | 1992-05-05 | Kabushiki Kaisha Toshiba | Manufacturing a wiring formed inside a semiconductor device |
| US5231054A (en) * | 1989-12-20 | 1993-07-27 | Fujitsu Limited | Method of forming conductive material selectively |
| JPH08293550A (en) * | 1995-04-24 | 1996-11-05 | Nec Corp | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5248468A (en) * | 1975-10-15 | 1977-04-18 | Nec Home Electronics Ltd | Process for production of semiconductor device |
| JPS5776833A (en) * | 1980-09-04 | 1982-05-14 | Applied Materials Inc | Heat resistant metal depositing method and product thereof |
-
1984
- 1984-12-11 JP JP26233584A patent/JPS61139026A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5248468A (en) * | 1975-10-15 | 1977-04-18 | Nec Home Electronics Ltd | Process for production of semiconductor device |
| JPS5776833A (en) * | 1980-09-04 | 1982-05-14 | Applied Materials Inc | Heat resistant metal depositing method and product thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4963511A (en) * | 1987-11-30 | 1990-10-16 | Texas Instruments Incorporated | Method of reducing tungsten selectivity to a contact sidewall |
| US5110762A (en) * | 1988-07-07 | 1992-05-05 | Kabushiki Kaisha Toshiba | Manufacturing a wiring formed inside a semiconductor device |
| US4983543A (en) * | 1988-09-07 | 1991-01-08 | Fujitsu Limited | Method of manufacturing a semiconductor integrated circuit having an interconnection wire embedded in a protective layer covering the semiconductor integrated circuit |
| US5231054A (en) * | 1989-12-20 | 1993-07-27 | Fujitsu Limited | Method of forming conductive material selectively |
| JPH08293550A (en) * | 1995-04-24 | 1996-11-05 | Nec Corp | Semiconductor device |
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