JPS6195613A - Reset signal generating circuit - Google Patents
Reset signal generating circuitInfo
- Publication number
- JPS6195613A JPS6195613A JP21701184A JP21701184A JPS6195613A JP S6195613 A JPS6195613 A JP S6195613A JP 21701184 A JP21701184 A JP 21701184A JP 21701184 A JP21701184 A JP 21701184A JP S6195613 A JPS6195613 A JP S6195613A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- voltage
- output
- capacitor
- reset signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
Landscapes
- Electronic Switches (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は、マイクロコンピュータ等のりセクトを行う為
のリセット信号を発生するリセット信号発生回路に関す
るもので、特にＩＣ（集積回路）化に適し、かつ電源投
入時と遮断時とに確笑にリセット信号を発生させること
の出来るリセット信号発生回路に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a reset signal generation circuit that generates a reset signal for performing cross-section of a microcomputer, etc., and is particularly suitable for IC (integrated circuit). The present invention also relates to a reset signal generating circuit that can generate a reset signal reliably when power is turned on and when power is turned off.
（ロ）従来の技術
最近、民生用の様々な機器にマイクロコンピュータが使
用されている。前記マイクロコンピュータは、正常な動
作を行なわせる為に、を源投入時や′邂源遮断時にリセ
ットをかけ、一旦内部回路をリセット状態にしなければ
ならない。しかして。(b) Prior Art Recently, microcomputers have been used in various consumer devices. In order for the microcomputer to operate normally, it is necessary to reset the internal circuit once when the power is turned on or when the power is turned off. However.
リセットをかける為のリセット信号は、前記マイクロコ
ンピュータの電源電圧が十分高くなったときに一定期間
発生させる必要がある為、前記マイクロコンピュータの
電源電圧に関連して適切に発生させなければならない。Since the reset signal for resetting must be generated for a certain period of time when the power supply voltage of the microcomputer becomes sufficiently high, it must be generated appropriately in relation to the power supply voltage of the microcomputer.
しかして、リセット信号発生回路としては１例えば昭和
５７年１２月１日に発行された雑誌「トランジスタ技術
Ｊ １９８２年１２月号広告特色４３頁に記載されてい
る如きものが公知である。このリセット信号発生回路は
。As a reset signal generating circuit, for example, one such as that described in the magazine "Transistor Technology J, December 1982 issue, advertising feature page 43, published on December 1, 1982, is known. The signal generation circuit.
簡略化して示せば第２図の如くなり、電源電圧が印加さ
れる電源端子（１）と、前記電源電圧から定電圧を発生
する定電圧回路（２）と、前記電源電圧により充電され
るコンデンサ（３）と、該コンデンサ（３）の端子電圧
と基４！ｉ電圧とを比較する比較回路（４）と。If it is simplified, it will be as shown in Fig. 2, which includes a power supply terminal (1) to which a power supply voltage is applied, a constant voltage circuit (2) that generates a constant voltage from the power supply voltage, and a capacitor that is charged by the power supply voltage. (3), the terminal voltage of the capacitor (3) and the base 4! A comparison circuit (4) that compares the i voltage.
該比較回路（４）の出力信号に応じてリセット信号を発
生するトランジスタ（５）とから構成されている。and a transistor (5) that generates a reset signal in response to the output signal of the comparison circuit (4).
第２図の場合、を源を投入するとコンデンサ（３）の充
電が開始されるが、前記コンデンサ（３）の端子電圧が
基準電圧よりも低い間、比較回路（４）の出力が「Ｈ」
になり、トランジスタ（５）がオンしている。In the case of Fig. 2, charging of the capacitor (3) starts when the power is turned on, but while the terminal voltage of the capacitor (3) is lower than the reference voltage, the output of the comparator circuit (4) is "H".
, and the transistor (5) is turned on.
抵抗（６）とコンデンサ（３）とで決まる時定数に応じ
て） 前記コンデンサ（３）の端子電圧が
上昇し、基準電圧よりも高くなると、比較回路（４）の
出力がｒＬＪになり、トランジスタ（５）がオフになる
。従って、電源投入時に、出力端子（７）に所定のリセ
ットａ号を発生させろことが出来、該リセット信号を被
制御回路（図示せず）となるマイクロコンピュータに印
加すれば、［源投入時のリセットを行うことが出来る。When the terminal voltage of the capacitor (3) increases and becomes higher than the reference voltage (according to the time constant determined by the resistor (6) and the capacitor (3)), the output of the comparator circuit (4) becomes rLJ, and the transistor (5) is turned off. Therefore, when the power is turned on, a predetermined reset signal a can be generated at the output terminal (7), and if the reset signal is applied to the microcomputer that becomes the controlled circuit (not shown), [when the power is turned on] You can perform a reset.
また、電源を遮断すると、コンデンサ（３）に蓄積され
た電荷が抵抗（８）を介して放電される。その為。Furthermore, when the power is cut off, the charges accumulated in the capacitor (3) are discharged via the resistor (8). For that reason.
前記コンデンサ（３）の端子電圧が低下して基準電圧以
下となり、比較回路（４）の出力がｒＨＪになってトラ
ンジスタ（５）がオンする。従って、を源遮断時にもリ
セット信号を発生させることが出来、マイクロコンピュ
ータのリセットを行うことが出来る。The terminal voltage of the capacitor (3) decreases to below the reference voltage, and the output of the comparator circuit (4) becomes rHJ, turning on the transistor (5). Therefore, a reset signal can be generated even when the power source is cut off, and the microcomputer can be reset.
（ハ）発明が解決しようとする問題点
しかしながら、第２図の回路は、ＩＣ化した場合、外部
接続端子の数が多くなるという欠点を有する。すなわち
、第２図の回路は、リセット信号の巾を所定値に設定す
る為のコンデンサ（３）を比較回路（４）の入力端に外
部接続する為の外部接続端子と、リセット信号を被制御
回路に印加する為の外部接続端子とを必要とするもので
あった。その為。(c) Problems to be Solved by the Invention However, the circuit shown in FIG. 2 has the disadvantage that, when integrated into an IC, the number of external connection terminals increases. That is, the circuit shown in Figure 2 has an external connection terminal for externally connecting a capacitor (3) for setting the width of the reset signal to a predetermined value to the input terminal of the comparator circuit (4), and a terminal for controlling the reset signal. This required an external connection terminal for applying voltage to the circuit. For that reason.
リセット機能の他ミューティング機能等別の機能を有す
る電源用ＩＣ内に前記第２図のリセット信号発生回路を
組み込むと、外部接続端子が足りなくなる危険があった
。If the reset signal generating circuit shown in FIG. 2 was incorporated into a power supply IC having other functions such as a muting function in addition to a reset function, there was a risk of running out of external connection terminals.
に）問題点を解決するための手段
本発明は、上述の点に鑑み成されたもので、リセット信
号が発生される出力端子にコンデンサを接続するととも
に該コンデンサを第１の時定数で充電する第１充直回路
、前記コンデンサを第１の時定数よりも短い第２の時定
数で充電する第２充電回路、前記コンデンサを放電する
放電回路、第１及び第２の基準電圧を発生する基準電圧
発生回路、定電圧を発生する定遜圧回路、前記出力端子
の電圧と前記第２基準電圧とを比較し、前記第２充電回
路を駆動する第１比較回路、及び前記定電圧回路の出力
電圧と前記第１基準電圧とを比較し。B) Means for Solving the Problems The present invention has been made in view of the above points, and includes connecting a capacitor to the output terminal at which the reset signal is generated and charging the capacitor with a first time constant. a first charging circuit; a second charging circuit for charging the capacitor with a second time constant shorter than the first time constant; a discharging circuit for discharging the capacitor; and a reference for generating first and second reference voltages. a voltage generation circuit, a constant voltage circuit that generates a constant voltage, a first comparison circuit that compares the voltage of the output terminal with the second reference voltage and drives the second charging circuit, and an output of the constant voltage circuit. Compare the voltage with the first reference voltage.
前記放電回路を駆動する第２比較回路を設けた点を特徴
とする。The present invention is characterized in that a second comparison circuit that drives the discharge circuit is provided.
（ホ）作用
本発明に依れば、リセット信号が得られる出力端子に接
続されるコンデンサが、電源投入時において、まず第１
充電回路により第１の時定数により充電され、前記コン
デンサの端子電圧が所定値罠なったとき、第２充電回路
により第１の時定数よりも短い第２の時定数で充電され
、かつ前記コンデンサが、電源遮断時において、放電回
路により直ちに放電される。(E) Effect According to the present invention, when the power is turned on, the capacitor connected to the output terminal from which the reset signal is obtained is first connected to the first capacitor.
The capacitor is charged by a charging circuit with a first time constant, and when the terminal voltage of the capacitor reaches a predetermined value, the capacitor is charged by a second charging circuit with a second time constant shorter than the first time constant, and the capacitor is charged with a second time constant shorter than the first time constant. is immediately discharged by the discharge circuit when the power is cut off.
（ハ）実施例 第１図は１本発明の一実施例を示す回路図で。(c) Examples FIG. 1 is a circuit diagram showing one embodiment of the present invention.
（９）は電源電圧が印加される電源端子、Ｃ１０１は前
記電源電圧から定電圧を得る定電圧回路、αＤは第１及
び＠２基準電圧Ｖ＋ 及びＶ、 （タタＬ 、 Ｖ、
＞Ｖ２ ）を発生する基準電圧発生回路、α２はりセク
ト信号が得られる出力端子、αｙは該出力端子αりに接
続されたコンデンサ、■は電源出力端子αつに得られる
電圧■、により、前記コンデンサａＳを第１の充電時定
数Ｔ１で充電する充電抵抗（第１充電回路）。(9) is a power supply terminal to which a power supply voltage is applied, C101 is a constant voltage circuit that obtains a constant voltage from the power supply voltage, αD is the first and @2 reference voltages V+ and V, (Tata L, V,
>V2), an output terminal from which the α2 sector signal is obtained, αy is a capacitor connected to the output terminal α, and ■ is a voltage obtained at the power supply output terminal α. A charging resistor (first charging circuit) that charges the capacitor aS with a first charging time constant T1.
［相］はインバータαηと、電流ミラー接続された第１
及び第２トランジスタａ秒及びα９と、ダイオード■と
から成り、前記コンデンサ０段を前記第１の充電時定数
よりも短い第２の充電時定数Ｔ２で充邂丁ろ第２元重回
路、＠はインバータ（２２１及び放電トランジスタＣ２
３）から成り、前記コンデンサ０３の電荷を放電する放
電回路、（財）は前記定電圧回路Ｑｌの出力定電圧Ｖ、
を分圧する抵抗田及び弼から成る分圧回路、＠は基準電
圧発生回路０１）の第２基準電圧Ｖ！と出力端子αりの
電圧Ｖ、とを比較し、その出力信号により前記第２充電
回路四を駆動する第１比較回路、及び弼は前記基準電圧
発生回路ＯＢの第１基準亀圧ｖ１ と前記分圧回路東の
出力電圧Ｖ５ とを比較し、その出力信号により前記放
電回路Ｏを駆動する第２比較回路である。[Phase] is the first phase connected to the inverter αη and the current mirror.
and a second element heavy circuit consisting of a second transistor a seconds and α9, and a diode ■, which charges the capacitor 0 stage with a second charging time constant T2 shorter than the first charging time constant. is an inverter (221 and discharge transistor C2
3), a discharge circuit for discharging the charge of the capacitor 03, the output constant voltage V of the constant voltage circuit Ql;
A voltage dividing circuit consisting of a resistor field and a voltage divider, @ is the second reference voltage V! of the reference voltage generating circuit 01). and a voltage V at the output terminal α, and a first comparison circuit that drives the second charging circuit 4 with its output signal, and a first reference voltage V1 of the reference voltage generation circuit OB and the This is a second comparator circuit that compares the output voltage V5 of the voltage divider circuit east and drives the discharge circuit O with the output signal thereof.
次に動作を説明する。電源を投入すると、まず基準電圧
発生回路αＤから第１及び第２基準電圧ｖ１及びＶ！が
発生し、該第１及び第２基準電圧ｖ１及びＶ、がそれぞ
れ第２及び第１比較回路１２ｅ及び（２）の負入力端子
に印加される。一方、定電圧回路（ｌ［）の出力電圧Ｖ
、は未だ十分に高くならず１分圧回路吻）の出力電圧ｖ
５は、 Ｖ＋ ＞ Ｖｓの関係になる為、第２比較回路
（２Ｑの出力は「Ｌ」になり、放電回路Ｏの放電トラン
ジスタ２３がオンになる。またコンデンサＱ３１が初期
状態において完全放鉦されているとすれば、第１比較回
路額の正入力端子に印加される出力端子（１２１の電圧
Ｖ、はＩ２ ＞ Ｉ４となり。Next, the operation will be explained. When the power is turned on, first and second reference voltages v1 and V! are generated from the reference voltage generation circuit αD. is generated, and the first and second reference voltages v1 and V are applied to the negative input terminals of the second and first comparison circuits 12e and (2), respectively. On the other hand, the output voltage V of the constant voltage circuit (l[)
, is still not high enough and the output voltage v of the voltage divider circuit
5 has a relationship of V+ > Vs, so the output of the second comparison circuit (2Q becomes "L" and the discharge transistor 23 of the discharge circuit O is turned on. Also, the capacitor Q31 is completely discharged in the initial state. If so, the voltage V at the output terminal (121) applied to the positive input terminal of the first comparator circuit becomes I2 > I4.
前記第１比較回路（至）の出力がｒＬＪになっているの
で、＠２２充屯路ｔ１６１は動作を停止している。その
為、出力端子０ｚの電圧は、電源投入直後にはｒＬＪ状
態を保っている。Since the output of the first comparison circuit (to) is rLJ, @22 charging road t161 has stopped operating. Therefore, the voltage at the output terminal 0z maintains the rLJ state immediately after the power is turned on.
時間が経過し１時刻 １． Ｋなると定電圧回路（１（
１の出力電圧Ｖ、が高くなり１分圧回路りからＶ。Time has passed and 1 hour has passed 1. When K, the constant voltage circuit (1(
The output voltage V of 1 becomes high and V from the 1 voltage divider circuit.
＜Ｉ５ どなる電圧が発生し、第２比較回路ｔｊｌの
出力がｒＨＪになり、放電回路Ｏの放電トランジスタの
がオフになる。その為、充電抵抗Ｉによるコンデンサ０
３の充電が開始されるｂ′−１前記光−抵抗Ｉと前記コ
ンデンサＱ３１とによって決まる第１の充電時定数Ｔ、
は長い為、前記コンデンサ０３）の端子電圧は徐々に上
昇し、出力端子０２１０′）電圧もそれに応じたものと
なる。しかして１時刻ｔ、に出力端子ＣＬ２の電圧ｖ４
がＩ２ ＜ ｖ４になると、第１比較回路（５）の出力
が「Ｈ」になり、第２充電回路西が作動を開始する。前
記第２光電回路四は、インバータαＤの入力がｒＬＪの
とき該インバータ面の出力６；ｒＨＪになり、第１トラ
ンジスタ賭のコレクタ電流が流れず、第２トランジスタ
（１’Ｊのコレクタ電流も流れない。また、前記インバ
ータ０ηの入力が「Ｈ」のとき該インバータαηの出力
がｒＬＪにな１）、第１）ランジスタ（１８）のコレク
タ電流が流れ。<I5 A loud voltage is generated, the output of the second comparator circuit tjl becomes rHJ, and the discharge transistor of the discharge circuit O is turned off. Therefore, the capacitor 0 due to charging resistance I
3 starts charging b'-1; a first charging time constant T determined by the photoresistor I and the capacitor Q31;
Since the voltage is long, the voltage at the terminal of the capacitor 03) gradually increases, and the voltage at the output terminal 0210') also increases accordingly. Therefore, at time t, the voltage v4 of the output terminal CL2
When I2 < v4, the output of the first comparator circuit (5) becomes "H" and the second charging circuit (west) starts operating. In the second photoelectric circuit 4, when the input of the inverter αD is rLJ, the output of the inverter becomes rHJ, and the collector current of the first transistor does not flow, and the collector current of the second transistor (1'J also flows). Also, when the input of the inverter 0η is "H", the output of the inverter αη becomes rLJ1), and the collector current of the first transistor (18) flows.
ミラー関係にある第２トランジスタα９のコレクタに所
定の定ｔＫが発生する様に成されている。従って、前記
第１比較回路（２）の出力が「Ｈ」になると、前記第２
充電回路鵠から光１電流が発生し、コンデンサ０Ｊは、
前記第１の充電時定数Ｔ１ よりも短い第２０充屯時定
数Ｔ２で光電され、前記コンデンサ（１３１の端子電圧
、すなわち出力端子ａｚの電圧ｖ４は、略直ちに［ＨＪ
Ｋなる。A predetermined constant tK is generated at the collector of the second transistor α9 in a mirror relationship. Therefore, when the output of the first comparison circuit (2) becomes "H", the output of the second comparison circuit (2) becomes "H".
A light 1 current is generated from the charging circuit, and the capacitor 0J is
The terminal voltage of the capacitor 131, that is, the voltage v4 of the output terminal az, is almost immediately [HJ
K becomes.
上述の如く、電源投入時において）１．電源出力端子（
１９の電圧が定電圧になる前後進、出力端子α２の電圧
がＩＩ、Ｊに保たれるから、前記出力端子（Ｉ２１の電
圧ｒＬＪをリセット信号として被制御回路に。As mentioned above, when the power is turned on) 1. Power output terminal (
19 becomes a constant voltage, the voltage at the output terminal α2 is maintained at II, J, and the voltage rLJ at the output terminal (I21) is used as a reset signal to the controlled circuit.
前記を像出力端子α９の定電圧をｔ原電圧として前記被
制御回路にそれぞれ印加すれば、前記被制御回路の確実
なるリセット及び駆動を達成することが出来る。尚、実
施例においては、基準電圧発生回路ｕＤの第１基準電圧
ｖ１を４．５Ｖ、第２基準電圧Ｖ、を１．２Ｖ、定電圧
回路０１の出力定電圧を５．６Ｖ、を原端子（９）に印
加される電源電圧を８ｖに設定している。By applying the constant voltage of the image output terminal α9 as the original voltage to each of the controlled circuits, it is possible to reliably reset and drive the controlled circuit. In the embodiment, the first reference voltage v1 of the reference voltage generation circuit uD is 4.5V, the second reference voltage V is 1.2V, and the output constant voltage of the constant voltage circuit 01 is 5.6V. The power supply voltage applied to (9) is set to 8V.
次に電源遮断時の動作を説明する。時刻ｔ、に電源を遮
断すると、まず定電圧回路ＱＯＩの出力電圧Ｖ、が低下
し、 Ｖ＋ ＞ Ｖ！どなる。その為、第２比較回路（
ハ）の出力がｒＬＪになり、放電回路ゆの放電トランジ
スタｃ！３がオンになって、コンデンサαＪの放ばが開
始される。しかして、前記コンデンサ０３の放電が進み
、出力端子Ｏ３の電圧Ｖ、がＶ、 ＞ Ｖ。Next, the operation when the power is cut off will be explained. When the power is cut off at time t, the output voltage V of the constant voltage circuit QOI decreases, and V+ > V! bawl. Therefore, the second comparison circuit (
The output of c) becomes rLJ, and the discharge transistor c! of the discharge circuit Yuno! 3 is turned on and discharge of capacitor αJ is started. As a result, the discharge of the capacitor 03 progresses, and the voltage V at the output terminal O3 becomes V>V.
となる迄低下すると、第１比較回路額の出力がｒＬＪに
なり、第２充電回路肋の動作が停止し。When the voltage decreases to , the output of the first comparison circuit becomes rLJ, and the operation of the second charging circuit stops.
その後、″ＦＩＬ源端子（９）に印加される電源電圧の
低下に応じて、第１図の回路は初期状態に戻る。Thereafter, the circuit of FIG. 1 returns to its initial state in response to a decrease in the power supply voltage applied to the FIL source terminal (9).
第３図は、電源出力端子Ｑ９に得られる被制御回路の為
の電源′電圧Ｖ、 （第３図（イ））と、出力端子α２
に得られる出力電圧（リセット信号２第３図（ロ））と
の関係を示すものである。時刻ｔ０に電源を投入すると
、電源電圧Ｖ、が上昇していき１時刻ｔ１になって第１
基準電圧ｖ１を越えると放電回路＠の放電トランジスタ
（ハ）がオフになる。その為、コンデンサ０３は充電抵
抗α４により充電され、出力電圧ｖ４が徐々に上昇し１
時刻ｔ、で第２基準電圧Ｖ、を越えると、第２充電回路
四が作動し、前記端子電圧Ｖ、が急速にｒＨＪになる。Figure 3 shows the power source voltage V for the controlled circuit obtained at the power output terminal Q9 (Figure 3 (a)) and the output terminal α2.
3 shows the relationship between the output voltage (reset signal 2 in FIG. 3 (b)) obtained in FIG. When the power is turned on at time t0, the power supply voltage V increases until the first time t1.
When the reference voltage v1 is exceeded, the discharge transistor (c) of the discharge circuit @ is turned off. Therefore, the capacitor 03 is charged by the charging resistor α4, and the output voltage v4 gradually increases to 1
When the second reference voltage V, is exceeded at time t, the second charging circuit 4 is activated, and the terminal voltage V, rapidly becomes rHJ.
また、時刻ｔ、にｔ＃、を遮断すると、前記放電トラン
ジスタｃ！３がオンになり、コンデンサ（１３の電荷を
急速に放電するので、出力電圧はｒＬＪになる。Further, when t# is cut off at time t, the discharge transistor c! 3 turns on and quickly discharges the charge on the capacitor (13), so the output voltage becomes rLJ.
（ハ）発明の効果
以上述べた如く１本発明に依れば、電源投入時υ
及び遮断時に、被制御回路の電源電圧の変化に応たタイ
ミングで、確実１［ＩＪ上セツト号を発生させることが
出来るリセット信号発生回路を提供出来１
ろ。またリセット信号のパルス巾を定めるコンデンサ
をリセット信号の出力端子に接続しているので、ＩＣ化
に際し、端子数の少いリセット信号発生回路を提供出来
る。更に、前記コンデンサの放電を行う放電回路を、前
記被制御回路のｔｉｔ（ｌＩｊｊ［圧の変化に応じて駆
動しているので、電源遮断時に正確なタイミングでリセ
ット信号を発生させることが出来る。(c) Effects of the Invention As described above, according to the present invention, the 1 We can provide a reset signal generation circuit that can
reactor. Furthermore, since the capacitor that determines the pulse width of the reset signal is connected to the output terminal of the reset signal, it is possible to provide a reset signal generation circuit with a small number of terminals when integrated into an IC. Furthermore, since the discharge circuit that discharges the capacitor is driven in response to changes in the tit(lIjj) pressure of the controlled circuit, a reset signal can be generated at accurate timing when the power is cut off.
第１図は１本発明の一実施例を示す回路図、第２図は従
来のリセット信号発生回路を示す回路図。
及び＠３図（イ）、（ロ）は本発明の説明に供する為の
特性図である。
主な図番の説明
（Ｉｎ・・・定電圧回路、 Ｕ・・・基準信号発生回路
、Ｃ２・・・出力端子、 Ｃ３）・・・コンデンサ、
（１４・・・充電抵抗、 ［相］・・・第２光゛亀回路
、 ゆ・・・放電回路。
（ハ）・・・第１比較回路、Ｃ８）・・・第２比較回路
。
出願人 三洋電機株式会社 外１名
代理人 弁理士 佐 野 靜 夫
＠１図
第３図FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional reset signal generating circuit. and @3 Figures (a) and (b) are characteristic diagrams for explaining the present invention. Explanation of main drawing numbers (In...constant voltage circuit, U...reference signal generation circuit, C2...output terminal, C3)...capacitor,
(14...Charging resistor, [phase]...Second optical turtle circuit, Yu...Discharging circuit. (C)...First comparison circuit, C8)...Second comparison circuit. Applicant: Sanyo Electric Co., Ltd. and 1 other representative: Patent attorney: Shizuo Sano @Figure 1 Figure 3
Claims (1)
為の回路であつて、前記リセット信号が得られる出力端
子と、該出力端子に接続されたコンデンサと、該コンデ
ンサを第１の時定数で充電する第１充電回路と、第１及
び第２基準電圧を発生する基準電圧発生回路と、前記コ
ンデンサを第１の時定数よりも短い第２の時定数で充電
する第２充電回路と、前記コンデンサを放電する回路と
、前記出力端子の電圧と前記第２基準電圧とを比較する
第１比較回路と、定電圧を発生する定電圧回路と、前記
定電圧回路の出力電圧と前記第１基準電圧とを比較する
第２比較回路とから成り、前記第１比較回路の出力信号
に応じて前記第２充電回路を作動させ、前記コンデンサ
の充電を行うとともに、前記第２比較回路の出力信号に
応じて前記放電回路を作動させ、前記コンデンサの放電
を行う様にしたことを特徴とするリセット信号発生回路
。(1) A circuit for generating a reset signal to be applied to a controlled circuit, comprising an output terminal from which the reset signal is obtained, a capacitor connected to the output terminal, and a first time constant. a first charging circuit that charges the capacitor with a second time constant, a reference voltage generation circuit that generates first and second reference voltages, and a second charging circuit that charges the capacitor with a second time constant that is shorter than the first time constant; a circuit for discharging the capacitor; a first comparison circuit for comparing the voltage of the output terminal with the second reference voltage; a constant voltage circuit for generating a constant voltage; and a second comparison circuit that compares the output signal with a reference voltage, and operates the second charging circuit in response to the output signal of the first comparison circuit to charge the capacitor, and the output signal of the second comparison circuit. 1. A reset signal generating circuit, wherein the discharge circuit is operated in response to the discharge of the capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21701184A JPS6195613A (en) | 1984-10-16 | 1984-10-16 | Reset signal generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21701184A JPS6195613A (en) | 1984-10-16 | 1984-10-16 | Reset signal generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6195613A true JPS6195613A (en) | 1986-05-14 |
Family
ID=16697424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21701184A Pending JPS6195613A (en) | 1984-10-16 | 1984-10-16 | Reset signal generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6195613A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53106524A (en) * | 1977-03-01 | 1978-09-16 | Toshiba Corp | Initial clear unit for digital circuit |
| JPS56122225A (en) * | 1980-02-29 | 1981-09-25 | Fujitsu Ltd | Power on reset circuit |
-
1984
- 1984-10-16 JP JP21701184A patent/JPS6195613A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53106524A (en) * | 1977-03-01 | 1978-09-16 | Toshiba Corp | Initial clear unit for digital circuit |
| JPS56122225A (en) * | 1980-02-29 | 1981-09-25 | Fujitsu Ltd | Power on reset circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3884810B2 (en) | High voltage generator | |
| US5157321A (en) | Charging control apparatus for vehicle | |
| JP3256732B2 (en) | Programming voltage adjustment circuit for programmable memory | |
| JP2628642B2 (en) | Automatic voltage switching power supply | |
| JPH07326194A (en) | Voltage booster for nonvolatile memory | |
| US4360855A (en) | Injector drive circuit | |
| US5023470A (en) | Electronic flash charging circuit | |
| US4453115A (en) | DC Motor control system | |
| JPS6195613A (en) | Reset signal generating circuit | |
| US7535206B2 (en) | Synchronous rectifying type switching regulator control circuit and semiconductor integrated circuit including the same | |
| GB2159351A (en) | Charge/discharge circuit | |
| JPH0154944B2 (en) | ||
| US4007467A (en) | Exposure control circuit | |
| US4550992A (en) | Motor drive control circuit | |
| JPH0345409B2 (en) | ||
| JPH07105702B2 (en) | Reset signal generation circuit | |
| JP2717829B2 (en) | Timer device | |
| US4482238A (en) | Brightness warning device for camera | |
| JPS5812569A (en) | Phase controlling circuit | |
| JPH0256034B2 (en) | ||
| US4097880A (en) | Photographic stroboscope | |
| JPS6139883A (en) | Rotating speed controller of dc motor | |
| JP3479572B2 (en) | LCD display drive | |
| JPS6243389Y2 (en) | ||
| JPS5837724A (en) | Reset circuit for microprocessor |