JPS6190469A - Field effect transistor - Google Patents
Field effect transistorInfo
- Publication number
- JPS6190469A JPS6190469A JP21236784A JP21236784A JPS6190469A JP S6190469 A JPS6190469 A JP S6190469A JP 21236784 A JP21236784 A JP 21236784A JP 21236784 A JP21236784 A JP 21236784A JP S6190469 A JPS6190469 A JP S6190469A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- active layer
- substrate
- pinch
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 13
- 239000002184 metal Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 239000013078 crystal Substances 0.000 abstract description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 241001480592 Chlorophyllum molybdites Species 0.000 description 1
- 238000002109 crystal growth method Methods 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、超高周波・高周波電子機器等に用いられる電
界効果トランジスタに関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a field effect transistor used in ultra-high frequency/high frequency electronic equipment and the like.
（従来例の構成とその問題点）
近年、１０数ＧＨｚ程度に至るマイクロ波・超高周波領
域においても半導体デバイスが使用される様になってき
ている。(Structure of conventional example and its problems) In recent years, semiconductor devices have come to be used even in the microwave and ultra-high frequency range up to about 10-odd GHz.
この周波数帯域に使用されるトランジスタには低雑音・
高利得が要求されている。これらトランジスタとしては
、通常、電界効果型のトランジスタが用いられ、とりわ
けＧａＡｓを用いた電界効果トランジスタ（ＦＥＴ）が
、低雑音特性を持つとされている。Transistors used in this frequency band have low noise and
High profits are required. As these transistors, field effect transistors are usually used, and in particular, field effect transistors (FETs) using GaAs are said to have low noise characteristics.
この電界効果トランジスタにおいて、雑音・利得を左右
するデバイス・パラメータの一つに相互コンダクタンス
Ｇ■がある。低雑音動作を得るためにはＧＩｌｌを出来
るだけ大きくしなければならない。In this field effect transistor, one of the device parameters that influences noise and gain is mutual conductance G. GIll must be made as large as possible to obtain low noise operation.
このＧ＋ｏは、ゲート長等のジオメトリを一定とすると
、活性層のキャリア濃度と移動度によってきまる。This G+o is determined by the carrier concentration and mobility of the active layer, assuming that the geometry such as the gate length is constant.
ところで、ＦＥＴを低雑音動作させるには、通常、ピン
チオフぎりぎりにゲートバイアスを掛けた状態で用いる
。従って、そのバイアス時のゲート空乏層先端、即ち、
活性層の下側（ゲート電極の反対側）の界面付近におけ
るキャリア濃度と移動濃度が問題となる。By the way, in order to operate an FET with low noise, it is usually used in a state where a gate bias is applied to the edge of pinch-off. Therefore, the tip of the gate depletion layer at that bias, ie,
The carrier concentration and mobile concentration near the interface below the active layer (on the opposite side of the gate electrode) are problematic.
移動濃度は制御困難なパラメータであるので、キャリア
濃度を考えると以下のようになる。Since the mobile concentration is a parameter that is difficult to control, considering the carrier concentration, the following results are obtained.
第１図はＦＥＴに使用される半導体結晶の活性層近傍の
キャリア濃度プロファイルを示すもので、ａは理想的プ
ロファイル、ｂは現実のプロファイルをそれぞれ示す。FIG. 1 shows a carrier concentration profile near the active layer of a semiconductor crystal used in an FET, where a shows an ideal profile and b shows an actual profile.
適当なピンチオフと高Ｇｍを実現するためには、第１図
ａに示すような界面での急峻なキャリア濃度プロファイ
ルが理想的である。ところが、現実に得られるエピタキ
シャル活性層のキャリア濃度プロファイルは、第１図す
に示すように有限の立上り幅が出来てしまう。In order to realize appropriate pinch-off and high Gm, a steep carrier concentration profile at the interface as shown in FIG. 1a is ideal. However, the carrier concentration profile of the epitaxial active layer actually obtained has a finite rise width as shown in FIG.
この立上り幅は、出来得る限り狭くすることが望ましい
が、＠在の工業生産設備技術を以ってしては、キャリア
濃度変化１０１６〜１０”ｃ＋ｗ−”に対して２００人
が限界であり、さらに大きな規格許容値を定めても、エ
ピタキシャル成長の歩留りはどれで律せられているのが
現状である。It is desirable to make this rise width as narrow as possible, but with the current industrial production equipment technology, the limit is 200 people for a carrier concentration change of 1016~10"c+w-". Even if larger standard tolerance values are established, the current situation is that the yield of epitaxial growth is still limited.
（発明の目的）
本発明は上記欠点に鑑み、ピンチオフ近くの深いゲート
バイアスにおいても高いＧｗ＋を実現し、ひいては、低
雑音動作を可能にする電界効果トランジスタを提供する
ことを目的とするものである。(Object of the Invention) In view of the above drawbacks, it is an object of the present invention to provide a field effect transistor that achieves high Gw+ even at a deep gate bias near pinch-off, and furthermore enables low-noise operation. .
（発明の構成）
この目的を達成するために本発明の電界効果トランジス
タは、活性層と基板との間に金属層が介在した構成とし
たものであり、この構成により、活性層界面のキャリア
濃度変化層が、介在金属から伸びた空乏層内に入り、Ｆ
ＥＴのチャネルはキャリア濃度一定となる。従って、ピ
ンチオフ直前の状態においても６膳の余分な低下を引き
起こさず、雑音特性も優れた電界効果トランジスタが実
現されるものである。(Structure of the Invention) In order to achieve this object, the field effect transistor of the present invention has a structure in which a metal layer is interposed between the active layer and the substrate, and this structure reduces the carrier concentration at the interface of the active layer. The change layer enters the depletion layer extending from the intervening metal, and F
The carrier concentration in the ET channel is constant. Therefore, it is possible to realize a field-effect transistor that does not cause an excessive drop in noise even in the state immediately before pinch-off and has excellent noise characteristics.
（実施例の説明）
第２図は、本発明の電界効果トランジスタの構成を示す
一実施例の断面概略を示し、１は基板、２は金属層、３
は活性層、４はゲート電極、５はソース電極、６はドレ
イン電極、７は界面変性層、８は介在金属による空乏層
、９はゲート空乏層である。(Description of an embodiment) FIG. 2 shows a schematic cross-section of an embodiment showing the structure of a field effect transistor of the present invention, in which 1 is a substrate, 2 is a metal layer, and 3
4 is an active layer, 4 is a gate electrode, 5 is a source electrode, 6 is a drain electrode, 7 is an interface modified layer, 8 is a depletion layer formed by an intervening metal, and 9 is a gate depletion layer.
この例では、半導体としてＧａＡｇを用いている。In this example, GaAg is used as the semiconductor.
基板１としてはＣｒドープ半絶縁性ＧａＡｓを用い、分
子線エピタキシャル法によって基板１上にまず金属層２
として１層を成長させる。 ＧａＡｓ（１００）面上へ
Ａ＃はエピタキシャル成長し、単結晶層が得られる。厚
さは５００人とした。Cr-doped semi-insulating GaAs is used as the substrate 1, and a metal layer 2 is first formed on the substrate 1 by molecular beam epitaxial method.
Grow one layer as follows. A# is epitaxially grown on the GaAs (100) plane to obtain a single crystal layer. The thickness was set at 500 people.
引き続き分子線エピタキシャル装置でｎ−ＧａＡｓ活性
層３を成長させるａ ＧａＡｓはＡ＃単単結晶へエピタ
キシャル成長し、やはり単結晶ＧａＡｓが得られる。Subsequently, the n-GaAs active layer 3 is grown using a molecular beam epitaxial device.a GaAs is epitaxially grown into an A# single crystal, and single crystal GaAs is also obtained.
ドーピングはＳｉを用い３×１０″７ＣＩ＋−３とした
。厚さは１０００人である。活性層表面にゲート電極４
、ソース電極５．ドレイン電極６を付設してＦＥＴとし
た。The doping was done using Si at 3×10″7CI+-3.The thickness was 1000mm.A gate electrode 4 was placed on the surface of the active layer.
, source electrode5. A drain electrode 6 was attached to form an FET.
以上の様に構成された電界効果トランジスタについて、
以下その動作について説明する。Regarding the field effect transistor configured as above,
The operation will be explained below.
基板１と活性層３の間に介在する金属層２は、接する活
性層３を一定深さに空乏化する。活性層３の界面付近に
は、どの様な結晶成長方法によってもキャリア濃度が変
化したりする界面変性層７が存在する。ところが本発明
によれば、この変性層７は、介在金属による空乏層８の
内側に含まれてしまい、ＦＥＴの動作チャネルとはなら
ない。The metal layer 2 interposed between the substrate 1 and the active layer 3 depletes the adjacent active layer 3 to a certain depth. Near the interface of the active layer 3, there is an interface-modified layer 7 whose carrier concentration changes depending on any crystal growth method. However, according to the present invention, this modified layer 7 is included inside the depletion layer 8 formed by the intervening metal, and does not become an operating channel of the FET.
従って１表面のゲート電極５にバイアス電圧を印加し、
ゲート空乏層９を広げて行くと、基板界面にその先端が
達する以前に、介在金属による空乏層に接してチャネル
を閉じピンチオフ状態となる。Therefore, applying a bias voltage to the gate electrode 5 on one surface,
When the gate depletion layer 9 is widened, before its tip reaches the substrate interface, it comes into contact with the intervening metal depletion layer and closes the channel, resulting in a pinch-off state.
以上の様に本発明によれば、基板界面の変性層は、介在
金属より延びた空乏層内に入り、チャネルとして使用さ
れないので、ピンチオフ直前に至るまで相互コンダクタ
ンスＧｍは、急激には低下しない。As described above, according to the present invention, the modified layer at the substrate interface enters the depletion layer extending from the intervening metal and is not used as a channel, so the mutual conductance Gm does not drop sharply until just before pinch-off.
（発明の効果）
以上説明したように本発明は、活性層と基板の間に金属
層を介在させる構造により、特性の優れた電界効果トラ
ンジスタを実現するものであり、その実用的効果は大な
るものがある。(Effects of the Invention) As explained above, the present invention realizes a field effect transistor with excellent characteristics by using a structure in which a metal layer is interposed between an active layer and a substrate, and its practical effects are great. There is something.
第１図はＦＥＴに使用される半導体結晶の活性層近傍の
キャリア濃度プロファイルを示す図、第２図は本発明の
電界効果トランジスタの構成を示す一実施例の断面概略
を示す図である。
１ ・・・基板、２・・・金属層、３ ・・・活、他層
、４ ・・・ゲート電極、５・・・ソース電極。
６ ・・・ ドレイン電極、７ ・・・界面変性層。
８・・・介在金属による空乏層、９ ・・・ゲート空乏
層。FIG. 1 is a diagram showing a carrier concentration profile in the vicinity of an active layer of a semiconductor crystal used in a FET, and FIG. 2 is a diagram showing a schematic cross-section of an embodiment showing the structure of a field effect transistor of the present invention. 1...substrate, 2...metal layer, 3...active, other layer, 4...gate electrode, 5...source electrode. 6...Drain electrode, 7...Interfacial modification layer. 8... Depletion layer due to intervening metal, 9... Gate depletion layer.
Claims (1)
する電界効果トランジスタ。A field effect transistor characterized by a metal layer interposed between an active layer and a substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21236784A JPS6190469A (en) | 1984-10-09 | 1984-10-09 | Field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21236784A JPS6190469A (en) | 1984-10-09 | 1984-10-09 | Field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6190469A true JPS6190469A (en) | 1986-05-08 |
Family
ID=16621381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21236784A Pending JPS6190469A (en) | 1984-10-09 | 1984-10-09 | Field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6190469A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01155664A (en) * | 1987-12-12 | 1989-06-19 | Agency Of Ind Science & Technol | Field effect type transistor |
| KR102538966B1 (en) * | 2023-02-22 | 2023-06-01 | 대우공업 (주) | press forming apparatus having burr cutting unit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5587492A (en) * | 1978-12-26 | 1980-07-02 | Fujitsu Ltd | Field effect type semiconductor device |
-
1984
- 1984-10-09 JP JP21236784A patent/JPS6190469A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5587492A (en) * | 1978-12-26 | 1980-07-02 | Fujitsu Ltd | Field effect type semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01155664A (en) * | 1987-12-12 | 1989-06-19 | Agency Of Ind Science & Technol | Field effect type transistor |
| KR102538966B1 (en) * | 2023-02-22 | 2023-06-01 | 대우공업 (주) | press forming apparatus having burr cutting unit |
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