JPS6188189U - - Google Patents
Info
- Publication number
- JPS6188189U JPS6188189U JP17170384U JP17170384U JPS6188189U JP S6188189 U JPS6188189 U JP S6188189U JP 17170384 U JP17170384 U JP 17170384U JP 17170384 U JP17170384 U JP 17170384U JP S6188189 U JPS6188189 U JP S6188189U
- Authority
- JP
- Japan
- Prior art keywords
- address
- character generator
- write
- bits
- latch circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Digital Computer Display Output (AREA)
Description
第１図は本考案の一実施例に係るキヤラクタジ
エネレータ読出回路の構成図、第２図は第１図の
実施例のタイミング図である。
１〜３…キヤラクタジエネレータ（CGROM）、
４…ＣＰＵ、５…第１のアドレスデコーダ、６…
第２のアドレスデコーダ、７…第１のラツチ回路
、８…第２のラツチ回路、９…カウンタ、１０…
入力バツフア、１１…出力バツフア、１２…アド
レスバス、１３…データバス、MGWR１，MGWR２…
書込みパルス、MAGRD…読出しパルス、Ｓ１，Ｓ
２，Ｓ３…選択信号。
FIG. 1 is a block diagram of a character generator readout circuit according to an embodiment of the present invention, and FIG. 2 is a timing diagram of the embodiment of FIG. 1. 1 to 3...Character generator (CGROM),
4...CPU, 5...First address decoder, 6...
Second address decoder, 7... First latch circuit, 8... Second latch circuit, 9... Counter, 10...
Input buffer, 11...Output buffer, 12...Address bus, 13...Data bus, MGWR1, MGWR2...
Write pulse, MAGRD...Read pulse, S 1 , S
2 , S3 ...Selection signal.
Claims (1)
数のキヤラクタレジエネレータからデータを読出
すキヤラクタジエネレータ読出回路において、 前記ＣＰＵからデータバスに出力されたアドレ
スの上位数ビツドずつを保持して、これを各キヤ
ラクタジエネレータに出力する１ないし複数の第
１のラツチ回路と、 前記ＣＰＵからデータバスに出力されたアドレ
スの中位数ビツトおよび前記複数のキヤラクタジ
エネレータのうち一つを選択する選択ビツトを保
持して、前記アドレスの中位数ビツトを各キヤラ
クタジエネレータに出力するとともに、前記選択
ビツトで選択されたキヤラクタジエネレータに選
択信号を出力して前記キヤラクタジエネレータを
作動状態にする第２のラツチ回路と、 計数する毎にその計数値をアドレスの下位数ビ
ツトとして各キヤラクレジエネレータに出力する
カウンタと、 前記の各第１のラツチ回路および前記第２のラ
ツチ回路にそれぞれ対応して予め設定された各第
１の書込みアドレスおよび第２の書込みアドレス
を入力すると、入力した書込みアドレスに対応す
るラツチ回路に書込みパルスを出力して該ラツチ
回路を作動する第１のアドレスデコーダと、 予め設定された読出しアドレスを入力すると、
前記カウンタに読出しパルスを出力して前記カウ
ンタを作動する第２のアドレスデコーダとを有し
、 前記ＣＰＵは所望するキヤラクタジエネレータ
のアドレスの上位数ビツトずつを前記各第１の書
込みアドレスに書込み、中位数ビツトおよび前記
選択ビツトを前記第２の書込みアドレスに書込み
、前記読出しアドレスからデータを読出すことを
特徴とするキヤラクタジエネレータ読出回路。[Claims for Utility Model Registration] In a character generator readout circuit that is equipped with a CPU and reads data from a plurality of character generators having a plurality of address buses, the upper number of addresses outputted from the CPU to the data bus. one or more first latch circuits that hold bits one by one and output them to each character generator; and one or more first latch circuits that hold bits of each bit and output them to each character generator; It holds a selection bit for selecting one of the generators, outputs the middle number bits of the address to each character generator, and outputs a selection signal to the character generator selected by the selection bit. a second latch circuit that turns the character generator into an operating state; a counter that outputs the counted value as the lower several bits of the address to each character generator each time it counts; and each of the first latch circuits. When a first write address and a second write address, which are preset corresponding to the circuit and the second latch circuit, are inputted, a write pulse is output to the latch circuit corresponding to the inputted write address to write the corresponding latch circuit. When the first address decoder activates the latch circuit and the preset read address is input,
and a second address decoder that outputs a read pulse to the counter to operate the counter, and the CPU writes the upper few bits of the address of the desired character generator to each of the first write addresses. , a middle number bit, and the selection bit to the second write address, and read data from the read address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17170384U JPS6188189U (en) | 1984-11-14 | 1984-11-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17170384U JPS6188189U (en) | 1984-11-14 | 1984-11-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6188189U true JPS6188189U (en) | 1986-06-09 |
Family
ID=30729382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17170384U Pending JPS6188189U (en) | 1984-11-14 | 1984-11-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6188189U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5722281A (en) * | 1980-07-16 | 1982-02-05 | Hitachi Ltd | Display unit extended in address space |
-
1984
- 1984-11-14 JP JP17170384U patent/JPS6188189U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5722281A (en) * | 1980-07-16 | 1982-02-05 | Hitachi Ltd | Display unit extended in address space |
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