JPS6180836A - Semiconductor device having multilayer interconnection - Google Patents
Semiconductor device having multilayer interconnectionInfo
- Publication number
- JPS6180836A JPS6180836A JP59201756A JP20175684A JPS6180836A JP S6180836 A JPS6180836 A JP S6180836A JP 59201756 A JP59201756 A JP 59201756A JP 20175684 A JP20175684 A JP 20175684A JP S6180836 A JPS6180836 A JP S6180836A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- wiring
- aluminum wiring
- bonding pad
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は半導体装置における多層配線技術に関する。[Detailed description of the invention] The present invention relates to multilayer wiring technology in semiconductor devices.
半導体装置の高密度化に伴り℃これまでの単層構造のア
ルミニウム配線が多層配線構造すなわち、２層化、３層
化してさている。With the increase in the density of semiconductor devices, the conventional single-layer aluminum wiring structure has been replaced with a multilayer wiring structure, that is, two or three layers.
多層配線構造において、アルミニウム配線層間の絶縁膜
とし℃従来使用されていた５ｉＯｚ（シリコン酸化物）
系の無機絶縁膜は上１０になるほど表面の段差が大きく
、これの平坦化が困難である。In multilayer wiring structures, 5iOz (silicon oxide), which is conventionally used as an insulating film between aluminum wiring layers.
The surface of the inorganic insulating film has larger steps toward the top, making it difficult to flatten the surface.
このため２層や３層の配線構造では表面平坦化のでざる
高耐熱性有機樹脂、たとえばポリイミド系樹脂が使用さ
れる。このポリイミド系樹脂には。For this reason, in a two-layer or three-layer wiring structure, a highly heat-resistant organic resin, such as a polyimide resin, which does not allow surface flattening, is used. For this polyimide resin.
高純度ポリイミド系樹脂ＰＩＱ（日立化成工業の高品名
）及び感光性ポリイミドが知られている。High purity polyimide resin PIQ (Hitachi Chemical's high quality product name) and photosensitive polyimide are known.
（工業調査全発行、電子材料１９８３年７月ｐ３０２層
配線構造を有する半導体装置において、配線の一部を利
用して外部引き出し用当て部、いわゆるボンディングパ
ッドを形成する場合、第８図に示すように半導体基板１
の表面酸化膜２の上に第１層のアルミニウム配線３及び
第２層アルミニウム配線５を層間のポリイミド系樹脂４
を介して形成し、さらに表面に保藤用ポリイミド系樹脂
膜６を形成した構造を利用する。(Industrial Research Entire Publication, Electronic Materials, July 1983, p. 30 In a semiconductor device having a two-layer wiring structure, when a part of the wiring is used to form an external lead-out pad, a so-called bonding pad, as shown in Fig. 8), semiconductor substrate 1
On the surface oxide film 2 of
A structure in which a polyimide resin film 6 for Hoto is further formed on the surface is used.
同図に示すように、ボンディングパッド部７は２層のア
ルミニウム配０３，５が直接に重なった部分であり、第
Ｎｄのアルミニウム配線３の上に、それより小さくあけ
た層間膜４のスルーホール８を穏うようにして第１層配
縁３より大ぎい寸法に第２層アルミニウム配線５を敷い
である。そしてこの上の保護用ポリイミド系樹脂膜６に
は外部引出しのためのスルーホール９が２層目配綜より
も小さい寸法であけである。As shown in the figure, the bonding pad part 7 is a part where two layers of aluminum wiring 03 and 5 directly overlap, and a through hole in the interlayer film 4 made smaller than the Nd aluminum wiring 3 is formed on the bonding pad part 7. The second layer aluminum wiring 5 is laid with a larger dimension than the first layer wiring 3 so that the width of the second layer aluminum wiring 8 is larger than that of the first layer wiring 3. The upper protective polyimide resin film 6 has a through hole 9 for external extraction with a size smaller than that of the second layer.
上記構造を用いてさらに３層間縁構造とする場合、ボン
ディングパッド部は第９図に示す上うな構造になる。If the above structure is further used to form a three-layer interlayer structure, the bonding pad portion will have a structure similar to that shown in FIG.
同図で１０はポリイミド系樹脂からなる第２層絶縁膜、
１１は第３層のアルミニウム配線である。In the figure, 10 is a second layer insulating film made of polyimide resin;
11 is a third layer of aluminum wiring.
このような構造となった場合、周辺で３層に積層された
ポリイミド膜が厚くなるため、ボンディングパッド部７
と周辺部との段差が大きくなり、最上の第３層アルミニ
ウム配線１１を引出し配線として取出−ｆ朽今に、この
引出し配線を得るためのホトレジストが周辺の大ぎい段
差によって断れやすく、ホトレジストの切れた部分で第
３層アルミニウム配線の断線部１２を生じることになる
。In such a structure, the polyimide film stacked in three layers around the periphery becomes thicker, so the bonding pad portion 7
The height difference between the uppermost third layer aluminum wiring 11 and the surrounding area has become large, and the photoresist used to obtain this lead-out wiring is likely to break due to the large level difference in the periphery, causing the photoresist to break. A disconnection portion 12 of the third layer aluminum wiring is generated at the portion where the third layer aluminum wiring is broken.
特にボンディングパッド周辺部ではボンディング時の配
線ダメージを受けることが少ない。Particularly in the vicinity of the bonding pad, the wiring is less likely to be damaged during bonding.
配線を断れにくくするため、ホトレジストマスクを厚（
すれば、写真処理の際に解像力がわるくなり、加工精度
の低下を来す。このことは配線の微細化を不可能とし、
半導体装置の高密度化の妨げとなった。To make the wiring less likely to break, use a thick photoresist mask (
If this happens, the resolution during photo processing will deteriorate, resulting in a decrease in processing accuracy. This makes it impossible to miniaturize the wiring,
This became an obstacle to increasing the density of semiconductor devices.
本発明の目的は、ポリイミド系樹脂などの有機樹脂を配
線層間膜及び保護膜とじ℃用いる多層配線構造を有する
半導体装置において、ボンディングパッド部分の配線の
加工精度を向上させる構造を提供することにある。An object of the present invention is to provide a structure that improves the processing accuracy of wiring in a bonding pad portion in a semiconductor device having a multilayer wiring structure in which an organic resin such as a polyimide resin is used as a wiring interlayer film and a protective film. .
１発′Ａ″概要〕
１本願において開示される発明のうち、代衣的
なものの概要を簡単に説明すれば、下記のとおりである
。すなわち、半導体装置上に少なくとも３層のアルミニ
ウム配に９がポリイミド樹脂を層間膜とし’１Ｊ’ｌ成
され、上記アルミニウム配線の一部がボンディングパッ
ド部として形成され℃いる半導体県費において、上記ボ
ンディングパッドは上記少なくとも３層のアルミニウム
配線のうち、少なくとも１ ／ｉΩま用いられず、望ま
しくは最上層のアルミニウム配線ｔ゛よ用いられていな
いことにより、ボンディングパノド周辺部の段差による
配線きれを少なくし、ボンディングパッド時の配線ダメ
ージによる１所線を防止することができ、前記発明の目
的が５成できる。1 shot 'A'' overview]
1. Among the inventions disclosed in this application, a brief outline of the substitute clothing is as follows. That is, in a semiconductor prefectural expense in which at least three layers of aluminum wiring 9 are formed on a semiconductor device using polyimide resin as an interlayer film, and a part of the aluminum wiring is formed as a bonding pad portion, the bonding The pad is not used by at least 1/iΩ of the above-mentioned at least three layers of aluminum wiring, and preferably is not used as much as the top layer of aluminum wiring, thereby reducing wiring breakage due to steps around the bonding panode. However, it is possible to prevent a single line due to wiring damage at the time of bonding pads, thereby achieving the fifth object of the invention.
第１図乃至第７図は本発明の一実施例を示すものであっ
て、３層アルミニウム配線を使用する半心陣装置の配ね
形成プロセスの工程断面図である。FIGS. 1 to 7 show an embodiment of the present invention, and are cross-sectional views of a process for forming a half-centered device using three-layer aluminum wiring.
以下各工程に従っ工説明する。Each process will be explained below.
＋１１ シリコン半導体基体１の表面に公知の選択拡
俄技術によりトランジスタなどの素子を形成する。+11 Elements such as transistors are formed on the surface of the silicon semiconductor substrate 1 by a known selective expansion technique.
２はこの拡散の際に基体表面に熱生成された酸化物（Ｓ
ｉＯ２）ｔ［である。（第１図）＋２１ 酸化膜２の
一部をコン・タクトホトエッチし、アルミニウム蒸着、
ホトエッチにより第１層アルミニウム配線３を形成する
。（第２図）
（３１高純度ポリイミド系樹脂、たとえばポリイミドウ
ィンインドロキナゾリンジオンのフェノを塗布し、ベー
クし℃第１層の層間膜４を形成し、ホトレジストマスク
を使用しエヒドラジンエッチによりスルーホール８をあ
ける。（第３図）なお、上記ポリイミド系樹脂の代わり
に、感光性ポリイミド、たとえば全芳香族ポリイミドの
前駆体に感光性を付与したもののフェノを塗布し、プリ
ベーク後、それ自体を部分的に感光させ名ルーホールパ
ターンを得るようにしてもよい。2 is an oxide (S) thermally generated on the substrate surface during this diffusion.
iO2)t[. (Figure 1) +21 Contact photoetch a part of the oxide film 2, deposit aluminum,
First layer aluminum wiring 3 is formed by photoetching. (Fig. 2) (31) Apply a high purity polyimide resin, such as polyimide-windorokinazolinedione phenol, and bake to form the first interlayer film 4. Using a photoresist mask, etching the film through with ehydrazine. Hole 8 is opened. (Figure 3) Instead of the above polyimide resin, photosensitive polyimide, such as phenol made by imparting photosensitivity to the precursor of fully aromatic polyimide, is coated, and after prebaking, the resin itself is It may also be partially exposed to light to obtain a clear hole pattern.
＋４１ 第２層アルミニウム配線５を工程（２１と同
じ方法により形成する。（第４図）
上記スルーホール８で第１層アルミニウム配線３と重な
る部分がボンディングパッドとなる。+41 The second layer aluminum wiring 5 is formed by the same method as step 21 (FIG. 4) The portion of the through hole 8 overlapping with the first layer aluminum wiring 3 becomes a bonding pad.
（５１工程（３）と同じ方法でポリイミド系樹脂又は感
光性ポリイミドからなり、スルーホールを有する第２層
間絶縁膜１０を得る。（第５図）（６） ボンディン
グパッドとならない部分で、第２層アルミニウム配線５
にコンタクトする第３層アルミニウム配線１１を形成す
る。（第６図）（７） ポリイミド系樹脂又は感光性
ポリイミドを用い、ボンディングパッド部第２層絶縁膜
と同時にスルーホールをあけることにより最終保版膜（
プロテクション）６を形成する。（第７図）同図１３は
ポンディングされたワイヤを示すものである。(51 Using the same method as step (3), obtain a second interlayer insulating film 10 made of polyimide resin or photosensitive polyimide and having through holes. (Fig. 5) (6) In the part that will not become a bonding pad, Layer aluminum wiring 5
A third layer aluminum wiring 11 is formed in contact with. (Fig. 6) (7) Using polyimide resin or photosensitive polyimide, make a through hole at the same time as the second layer insulating film in the bonding pad area.
protection) 6. (FIG. 7) FIG. 13 shows the bonded wire.
上記プロセスにより形成された３層アルミニウム配線構
造を有する半導体装置においては、ボンディングパッド
部は、第１／ｆｉｉ及び第２層のアルミニウム配線３，
５により構成され、第３暦のアルミニウム配ｆｌｌｌは
ボンディングパッド部とは関りない部分で配線として用
いられている。In the semiconductor device having the three-layer aluminum wiring structure formed by the above process, the bonding pad portion includes the first/fii and second layer aluminum wiring 3,
5, and the third aluminum wire is used as wiring in a portion not related to the bonding pad portion.
このように、第３層アルミニウム配線をボンディングパ
ッドに用いないことにより、パッドのスルーホール部分
での急峻な段差を経て第３層アルミニウム配線が形成さ
れることがないから、この段差によって配線が断根する
ことがなくなった。In this way, by not using the third-layer aluminum wiring as a bonding pad, the third-layer aluminum wiring is not formed through a steep step in the through-hole portion of the pad, so the wiring can be broken due to this step. There was nothing left to do.
又、スルーホール部の段差を経る第３層アルミニウム配
線が存在しないことにより、ワイヤボンデインク時の第
３層アルミニウム配線のダメージもなくなった。これら
のことにより第３層アルミニウム配線の無理なレイアウ
トも必要なく、レイアウトの自由度が増すことになった
。又、第３層アルミニウム配線の加工の歩留まりを向上
できる。Further, since there is no third layer aluminum wiring that passes through the step of the through hole portion, damage to the third layer aluminum wiring during wire bonding is also eliminated. As a result, there is no need for an unreasonable layout of the third layer aluminum wiring, and the degree of freedom in layout is increased. Furthermore, the processing yield of the third layer aluminum wiring can be improved.
第１０図は、３層アルミニウム配ｆｆＪ構成を有する半
導体装置において、第１層アルミニウム配線３のみをボ
ンディングパッドとして残した場合の例を示す。FIG. 10 shows an example in which only the first layer aluminum wiring 3 is left as a bonding pad in a semiconductor device having a three-layer aluminum layout ffJ configuration.
第１１図は同じく、第２層アルミニウム配線５のみをボ
ンディングパッドとして残した場合の例を示す。Similarly, FIG. 11 shows an example in which only the second layer aluminum wiring 5 is left as a bonding pad.
第１２図は同じく第３層アルミニウム配線１１
１のみをボンディングパッドとして残した場合の
例を示す。Figure 12 also shows the third layer aluminum wiring 11.
An example will be shown in which only 1 is left as a bonding pad.
第１３図は同じく第２層及び第３層のアルミニウム配８
１５．１１のみをボンディングパッドとし、て残した例
を示す。Figure 13 also shows the aluminum wiring 8 of the second and third layers.
An example in which only 15.11 is left as a bonding pad is shown.
第１４図は４層アルミニウム配線構造を有する半導体装
置において、第１層及び第２層のアルミニウム配線３，
５のみをボンディングパッドとして残した例を示す。同
図において、１４はポリイミド系樹脂からなる第３層間
絶縁膜である。FIG. 14 shows a semiconductor device having a four-layer aluminum wiring structure, in which first and second layer aluminum wiring 3,
An example in which only 5 is left as a bonding pad is shown. In the figure, 14 is a third interlayer insulating film made of polyimide resin.
上記のその他の変形実施例では、３層又は４層のアルミ
ニウム配線構造を有する半導体装置（ＩＣ）において、
少なくとも３層のアルミニウム配線のうち、少な（とも
ＩＮはボンディングパッドとして用いないことにより、
ボンディングパッド部のスルーホールによる急峻な段差
部を、その用いられない配線が横切ることによる断線を
生じることを免れ、それにより半導体装置の信頼性を向
上することができる。In the other modified embodiments described above, in a semiconductor device (IC) having a three-layer or four-layer aluminum wiring structure,
Of the at least three layers of aluminum wiring, a small number (IN) is not used as a bonding pad, so
It is possible to avoid disconnection caused by the unused wiring crossing a steep stepped portion formed by a through hole in the bonding pad portion, thereby improving the reliability of the semiconductor device.
本発明はＩＣ，ＬＳＩ全般における多層配線構造に適用
することができる。The present invention can be applied to multilayer wiring structures in ICs and LSIs in general.
本発明は高密度化したバイポーラＩＣに応用した場合に
特忙有効である。The present invention is particularly effective when applied to high-density bipolar ICs.
第１図乃至第７図は本発明の一実施例を示すものであっ
て、３層アルミニウム配線構造を有するＩＣプロセスの
配線形成工程断面図である。
第８図は２層配線構造を有する半導体装置の例を示す断
面図である。
第９図は３層配線構造を有する半導体装置の例を示す断
面図である。
第１０図反型第１３図は本発明の実施例を示すものであ
って、３層配線構造を有する半導体装置のボンディング
パッド部分の断面図である。
第１４図は４層配線構造を有する半導体装置のボンディ
ングパッド部分の断面図である。
１・・・半導体基板、２・・・表面酸化膜、３・・・第
１層アルミニウム配線、４・・・第１層間絶縁膜、５・
・・第２層アルミニウム配線、６・・・保膿絶縁膜、７
・・・ボンデインクバッドエリア、８・・・スルーホー
ル、１０・・・第２ Ｒ５間絶（栄膜、１１・・・第３
層アルミニウム配線、１２・・・断υ部。
第 １ 図
第 ３ 図
第 ４ 図
第 ６ 図
第１１図
第 ８ 図
第 １２ 口FIGS. 1 to 7 show one embodiment of the present invention, and are cross-sectional views of wiring forming steps in an IC process having a three-layer aluminum wiring structure. FIG. 8 is a cross-sectional view showing an example of a semiconductor device having a two-layer wiring structure. FIG. 9 is a cross-sectional view showing an example of a semiconductor device having a three-layer wiring structure. FIG. 10 shows an embodiment of the present invention, and is a sectional view of a bonding pad portion of a semiconductor device having a three-layer wiring structure. FIG. 14 is a sectional view of a bonding pad portion of a semiconductor device having a four-layer wiring structure. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Surface oxide film, 3... First layer aluminum wiring, 4... First interlayer insulating film, 5...
...Second layer aluminum wiring, 6...Pulorous insulation film, 7
...Bonde ink bad area, 8...Through hole, 10...2nd R5 interval (Eiji film, 11...3rd
Layer aluminum wiring, 12... cut υ part. Figure 1 Figure 3 Figure 4 Figure 6 Figure 11 Figure 8 Figure 12
Claims (1)
がポリイミド系樹脂を層間絶縁膜として構成され、上記
アルミニウム配線の一部が外部引出し用当て部（ボンデ
ィングパッド）として形成されている半導体装置であっ
て、上記外部引出し用当て部は上記少なくとも３層のア
ルミニウム配線のうちの少なくとも１層は使用されてな
いことを特徴とする半導体装置。 ２、上記外部引出し用当て部は上記少なくとも３層のア
ルミニウム配線のうちの最上層のアルミニウム配線は使
用されない特許請求の範囲第１項記載の半導体装置。[Claims] 1. At least three layers of aluminum wiring are formed on a semiconductor substrate using polyimide resin as an interlayer insulating film, and a part of the aluminum wiring is formed as a contact portion (bonding pad) for external extraction. 1. A semiconductor device characterized in that the external drawer abutting portion does not use at least one layer of the at least three layers of aluminum wiring. 2. The semiconductor device according to claim 1, wherein the topmost aluminum wiring of the at least three layers of aluminum wiring is not used in the external drawer pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59201756A JPS6180836A (en) | 1984-09-28 | 1984-09-28 | Semiconductor device having multilayer interconnection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59201756A JPS6180836A (en) | 1984-09-28 | 1984-09-28 | Semiconductor device having multilayer interconnection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6180836A true JPS6180836A (en) | 1986-04-24 |
Family
ID=16446414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59201756A Pending JPS6180836A (en) | 1984-09-28 | 1984-09-28 | Semiconductor device having multilayer interconnection |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6180836A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01211953A (en) * | 1988-02-18 | 1989-08-25 | Nec Corp | Semiconductor integrated circuit |
| JPH01257353A (en) * | 1988-04-06 | 1989-10-13 | Nec Corp | Semiconductor device |
| JPH06151424A (en) * | 1992-02-19 | 1994-05-31 | Nec Corp | Semiconductor device |
| JP2006351767A (en) * | 2005-06-15 | 2006-12-28 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
-
1984
- 1984-09-28 JP JP59201756A patent/JPS6180836A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01211953A (en) * | 1988-02-18 | 1989-08-25 | Nec Corp | Semiconductor integrated circuit |
| JPH01257353A (en) * | 1988-04-06 | 1989-10-13 | Nec Corp | Semiconductor device |
| JPH06151424A (en) * | 1992-02-19 | 1994-05-31 | Nec Corp | Semiconductor device |
| JP2006351767A (en) * | 2005-06-15 | 2006-12-28 | Sanyo Electric Co Ltd | Semiconductor device and its manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0373136B2 (en) | ||
| KR20010062130A (en) | Semiconductor device | |
| JPH01280337A (en) | Semiconductor integrated circuit device | |
| JP2002231753A (en) | Bonding pad for semiconductor element and manufacturing method therefor | |
| JPS6180836A (en) | Semiconductor device having multilayer interconnection | |
| JP3206243B2 (en) | Bonding pad and method of forming the same | |
| JPH0695517B2 (en) | Semiconductor device | |
| JP3915670B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR20060097442A (en) | Bonding pad having groves and method of fabricating the same | |
| JPH0677315A (en) | Semiconductor device | |
| JP3098450B2 (en) | Semiconductor integrated circuit | |
| JPS5833705B2 (en) | Hands-on-hand training | |
| JP3243913B2 (en) | Dummy pad structure of semiconductor device | |
| JPH0612789B2 (en) | Semiconductor device | |
| JP2762844B2 (en) | Semiconductor device | |
| JPH0340449A (en) | Semiconductor device provided with integrated circuit | |
| JPH05243393A (en) | Integrated circuit | |
| JPS59117236A (en) | Semiconductor device | |
| JPS6043845A (en) | Manufacture of multilayer interconnection member | |
| JPH0786281A (en) | Semiconductor device and manufacture of semiconductor device | |
| JP3435317B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
| KR100835442B1 (en) | Pad structure and fabrication method of semiconductor device | |
| JP2006294837A (en) | Semiconductor device and its manufacturing method | |
| JPH07153756A (en) | Semiconductor integrated circuit device | |
| JP2001007113A (en) | Semiconductor device |