JPS6180828A - Semiconductor package structure - Google Patents

Semiconductor package structure

Info

Publication number
JPS6180828A
JPS6180828A JP20170884A JP20170884A JPS6180828A JP S6180828 A JPS6180828 A JP S6180828A JP 20170884 A JP20170884 A JP 20170884A JP 20170884 A JP20170884 A JP 20170884A JP S6180828 A JPS6180828 A JP S6180828A
Authority
JP
Japan
Prior art keywords
solder
lead
tin
substrate
package structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20170884A
Other languages
Japanese (ja)
Inventor
Koichi Inoue
井上　広一
Yasutoshi Kurihara
保敏 栗原
Tadashi Minagawa
皆川　忠
Komei Yatsuno
八野　耕明
Mamoru Sawahata
沢畠　守
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP20170884A priority Critical patent/JPS6180828A/en
Priority to DE3523808A priority patent/DE3523808C3/en
Publication of JPS6180828A publication Critical patent/JPS6180828A/en
Pending legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24—Selection of soldering or welding materials proper
    • B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
    • B23K35/262—Sn as the principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3463—Solder compositions in relation to features of the printed circuit board or the mounting process

Landscapes

  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To improve the property of lift for thermal fatigue of a semiconductor package structure by a method wherein a semiconductor substrate and a dielec tric substrate are coupled using a solder having the structure, wherein the cir cumference of the alpha initial crystal, containing a specific weight ratio of tin, lead for the remainder and having large grain diameter, is surrounded by the eutectic of relatively large grain diameter. CONSTITUTION:Solder is formed on the soldering electrode 4 located on the side of a silicon chip by performing a vapor-deposition method, and the composition of the solder is set at 50wt% of lead and 50wt% of tin. A silicon substrate 6 is plated in an electric surface, and a lead film 10 and a tin film 11 are fused. A chip-side solder 12 of almost globular shape is formed. An alumina-ceramic substrate side solder 13 consisting of 50wt% lead and 50wt% tin is formed on the surface of an alumina-ceramic substrate side soldered electrode 5. When the above is heated up again to the temperature a little higher than the liquid- phase temperature of the solder consisting of 50wt% lead and 50wt% tin in the furnace in the state wherein the chip-side solder 12 and the alumina-ceramic substrate side solder 13, a package structure is completed.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体基体と誘電体基板間を電気的かつネ）械
的゛に結合するための多数の微小はんだ群の組成を両角
）シて、改良された耐熱疲労寿命の付与されたパッケー
ジも・Ｖ遺体に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention provides compositions of a large number of micro solder groups for electrically and mechanically bonding between a semiconductor substrate and a dielectric substrate, Packages with improved thermal fatigue life also relate to V bodies.

〔発明の背景〕[Background of the invention]

半導体基体を誘電体基板に結合するに適する方法は、（
１）米国特許公報第３４２９０４０号に開示されている
ように、約５ないし４０重量％錫及び９５ないし６０重
量％鉛のはんだ組成物を溶融させて相互に接続する。こ
こで示されている組成のはんだは鉛の比率が錫よりも多
くやわらかい性質をもち、半導体基体と誘電体基板の熱
膨張係数の差に基づく熱歪を有効に吸収できると考えら
れている。A suitable method for bonding a semiconductor body to a dielectric substrate is (
1) Melting and interconnecting a solder composition of about 5 to 40 weight percent tin and 95 to 60 weight percent lead as disclosed in U.S. Pat. No. 3,429,040. The solder with the composition shown here has a higher proportion of lead than tin and is softer, and is thought to be able to effectively absorb thermal strain caused by the difference in coefficient of thermal expansion between the semiconductor substrate and the dielectric substrate.

半導体基体を鉛ベースはんだを用いてその支持基板に結
合する技術は最も一般的に行なわれており、例えば（２
）特開昭５１−１３０２８５号公報に接着面にニッケル
層をもつ半導体チップと金ＦＡＲ支持体とを１．０〜２
０重量％の銀と１．５〜４．５重ｔチの錫と９３，５〜
９７．５重量％の鉛とからなるはんだで接着したダイポ
ンディング構造が開示されている。The most common technique is to bond a semiconductor substrate to its supporting substrate using lead-based solder, for example (2
) Japanese Unexamined Patent Publication No. 51-130285 discloses that a semiconductor chip having a nickel layer on the adhesive surface and a gold FAR support are
0% by weight of silver and 1.5-4.5% by weight of tin and 93,5~
A solder-bonded die-bonded structure comprising 97.5% lead by weight is disclosed.

また、３６ないし４０重量％の鉛と６４ないし６０重ｉ
ｌｌの錫とからなるはんだは共晶系はんだと呼ばれ、超
塑性現象のために半２６体基体と支持基板の熱膨張係数
の差に基づく熱歪を有効に吸収できると考えられている
。このような考え方で半導体基体を共晶系はんだを用い
てその支持基板に結合する技術も一般的に行なわれてお
り、例えば（３）Ｓｏｌｉｄ　３ｔａｔｅ　Ｔｅｃｈｎ
ｏｌｏｇｙ、　Ｊｕｌｙ、　５４（１９７０）　　にお
けるｆ）、　Ｂｏｓｗｅｌｌによる「Ｍｅｃｈａｎｉｃ
ａｌ　］）ｅｓｉｇｎ　ｏｆ　Ｃｈｉｐ　Ｃｏｍｐｏｎ
ｅｎｔｓｆｏｒ　　”）’ｌｉｐ”　ａｎｄ　５ｈｏｒ
ｔ　Ｂｅａｍ−ＬｅａｄＭｏｕｎｔｉｎｇＪと題する論
文において、２端子コンデンサ素子を４０重量％の鉛と
６０Ｍ量チの錫とからなるはんだによシアルミナ基板上
の配線にはんだ付した構造が開示されている。Also, 36 to 40% by weight of lead and 64 to 60% by weight
Solder consisting of 1/1 of tin is called eutectic solder, and is thought to be able to effectively absorb thermal strain due to the difference in thermal expansion coefficient between the semi-26 body substrate and the supporting substrate due to the superplastic phenomenon. Based on this idea, a technique is also commonly used to bond a semiconductor substrate to its supporting substrate using eutectic solder, such as (3) Solid 3tate Technique.
f) in “Mechanic” by Boswell, July 54 (1970).
al])sign of Chip Compon
entsfor ”)'lip” and 5hor
In an article titled t Beam-Lead Mounting J, a structure is disclosed in which a two-terminal capacitor element is soldered to wiring on a sialumina substrate using a solder consisting of 40% by weight lead and 60M tin.

以上の引例で示したように、半導体基体と誘電体基板間
を微細かつ多数の微小はんだ群を用いて電気的かつ機械
的に結合するパッケージ構造体における微小はんだ群の
組成としては、鉛ペース系あるいは共晶系のはんだに限
られている。鉛ペース系及び共晶系のいずれにも属さな
い鉛−錫系のはんだは、信頼性の点で鉛ペース系あるい
は共晶系のはんだに比べて劣ると考えられ、従来の知見
に基づく常識では使用を避けるのが一般的であったため
である。即ち、鉛ベース系あるいは共晶系を外れる組成
域、例えば、５０％量チの鉛と５０重？ｔ　％の錫とか
らなるはんだでは、初晶のα固溶体の存在比率が減ると
ともにα固溶体間粒界に共晶組織が存在して粒界変形性
能を低下させ、また微細な共晶組織中に超塑性作用を阻
害する初晶α固溶体が存在することによって塑性変形性
能が低下し、接続部を担うはんだ自体または接続部に連
なって配置されている被接続部材が損傷を受ける懸念が
あったからである。このような背景によシ、鉛ベース系
または共晶系以外の組成域に属するはんだを使用した場
合の接続プロセスの検討も十分でなく、工業的に成立つ
プロセスが確立されていない。As shown in the above cited examples, the composition of the micro solder group in a package structure that electrically and mechanically connects the semiconductor substrate and the dielectric substrate using a large number of fine solder groups is lead-based. Or it is limited to eutectic solder. Lead-tin solder, which does not belong to either lead-based or eutectic systems, is considered to be inferior to lead-based or eutectic-based solders in terms of reliability; This is because its use was generally avoided. That is, the composition range outside the lead-based system or eutectic system, for example, 50% lead and 50% lead. In a solder consisting of t% tin, the abundance ratio of the primary α solid solution decreases, and a eutectic structure exists at grain boundaries between the α solid solutions, reducing grain boundary deformation performance. This was because there was a concern that the presence of primary α solid solution, which inhibits superplasticity, would reduce plastic deformation performance and damage the solder itself that plays a role in the connection or the connected components that are connected to the connection. be. Against this background, there has not been sufficient study on the connection process when using a solder belonging to a composition range other than lead-based or eutectic, and an industrially viable process has not been established.

〔発明の目的〕[Purpose of the invention]

本発明の目的は半導体基体と誘電体基板間を電気的かつ
機械的に結合するための多数の微小はんだ群の組成を調
節して、改良された耐熱疲労寿命の付与されたパッケー
ジ構造体を提供することにある。An object of the present invention is to provide a package structure with improved thermal fatigue life by adjusting the composition of a large number of micro solder groups for electrically and mechanically bonding a semiconductor substrate and a dielectric substrate. It's about doing.

〔発明の概要〕[Summary of the invention]

本発明０半導体パ′ヶ″″″′構造体は・錫が重量　　
　　　　１比で４０％を越え６０チ未満含有され、残部
が実質的に鉛であシ、かつ、大きな粒径のα初晶の周囲
を比較的大きな粒径の共晶が包囲する組織を呈するはん
だを用いた微細、かつ、多数の微小はんだ群により半導
体シイ（体と誘電体基板間を電気的かつ機械的に結合し
た半導体パッケージ構造体である。The structure of the present invention has a structure in which the weight of tin is
Solder containing more than 40% and less than 60% lead in terms of ratio of 1 to 1, the remainder being substantially lead, and exhibiting a structure in which α primary crystals with a large particle size are surrounded by eutectic crystals with a relatively large particle size. It is a semiconductor package structure that electrically and mechanically connects a semiconductor body and a dielectric substrate using a large number of fine solder groups.

発明者らは種々検討した結果、鉛と錫を主成分とするは
んだ材を用いて半導体基体と誘電体基板間を電気的かつ
機械的に結合して得られたパッケージ構造体は、はんだ
組成が鉛５０重量％、錫５０重Ｊｌｆ、ではんだが大き
な粒径のα初晶の周囲を比較的大きな粒径の共晶が包囲
する好ましい組織を呈する場合に優れた耐熱波°労寿命
特性を示すことを確認した。ここで言う好ましい組織は
、組成が錫の重量比で４０％を越え６０チ未満であり残
部が実質的に鉛であるはんだ材を半導体基体と誘電体基
板間に介装し、はんだ材を溶融せしめた陵、少なくとも
、はんだ融液が完全に固化するまでの間選択された速度
、即ち、１２５ｔＺ’／分以下の速度で冷却することに
より実現される。As a result of various studies, the inventors found that a package structure obtained by electrically and mechanically bonding a semiconductor substrate and a dielectric substrate using a solder material whose main components are lead and tin has a solder composition. When the solder is made of 50 wt% lead and 50 wt Jlf tin and exhibits a favorable structure in which α primary crystals with a large grain size are surrounded by eutectic crystals with a relatively large grain size, excellent heat wave resistance and working life characteristics are exhibited. It was confirmed. The preferred structure mentioned here is that a solder material whose weight ratio of tin is more than 40% but less than 60% and the remainder is substantially lead is interposed between the semiconductor substrate and the dielectric substrate, and the solder material is melted. This is achieved by cooling the solder melt at a selected rate, at least until the solder melt is completely solidified, i.e., at a rate below 125 tZ'/min.

このようなはんだ付プロセスを選ぶ理由は、第一に、は
んだ材自体の破壊強度、あるいは、弾性応力範囲を高め
ることであり、第二に、はんだ層に塑性変形しにくい。The reason for choosing such a soldering process is, firstly, to increase the breaking strength or elastic stress range of the solder material itself, and secondly, to make the solder layer less likely to undergo plastic deformation.

又は、塑性変形を抑制する金属組織を導入することであ
る。この第−及び第二の事項が達成されることによって
、半導体パッケージ構造体で最も款らかい部材でろ）応
力集中とこれば伴う塑性変形が顕著なはんだ層の剛性を
高め、同層の応力を分散させて塑性変形量を軽減し、疲
労寿命性能を向上させる。Another method is to introduce a metal structure that suppresses plastic deformation. By achieving the first and second points, the stiffness of the solder layer (which is the most flexible member in the semiconductor package structure), where stress concentration and associated plastic deformation are noticeable, is increased, and the stress in the same layer is reduced. Dispersion reduces the amount of plastic deformation and improves fatigue life performance.

〔発明の実施例〕 本発明の実施例を第１図から＠５図に従って説明する。[Embodiments of the invention] Embodiments of the present invention will be described according to FIGS. 1 to 5.

第１図に示すように、本発明によるパッケージ構造体は
アルミナセラミック基板２とシリコンチップ１とを複数
個の°はんだ３により結合した構造体である。はんだ３
によシ結合させるためにシリコンチップ１及びアルミナ
セラミック基板２には、それぞれ、シリコンチップ側は
んだ付電極４及びアルミナセラミック基板側はんだ付電
極５が形成されている。本発明の実施列ではシリコンチ
ップ１の寸法は一辺５Ｉ＋ＩＩ＋の正方形、はんだ３の
数は一辺当り２０個、合計８０個、シリコンチツブ側は
んだ行電極４及びアルミナセラミック基板側はんだ行電
極５はそれぞれ直径１００μｍ１最小ピツチ２００μｍ
である。As shown in FIG. 1, the package structure according to the present invention is a structure in which an alumina ceramic substrate 2 and a silicon chip 1 are bonded together by a plurality of solders 3. Solder 3
For better bonding, a silicon chip side soldering electrode 4 and an alumina ceramic substrate side soldering electrode 5 are formed on the silicon chip 1 and the alumina ceramic substrate 2, respectively. In the embodiment of the present invention, the size of the silicon chip 1 is a square with sides 5I+II+, the number of solders 3 is 20 per side, 80 in total, and the solder row electrodes 4 on the silicon chip side and the solder row electrodes 5 on the alumina ceramic substrate each have a diameter of 100 μm1. Minimum pitch 200μm
It is.

ここで、本発明によるパッケージ構造体の製造工程を第
２図に従って説明する。Here, the manufacturing process of the package structure according to the present invention will be explained with reference to FIG.

（ａ）　　すでに、トランジスタ、ダイオード等が形成
されたシリコン基板６上に配線のだめのアルミニウム配
線膜８が絶縁のための５ｊＣｈパツシベーシヨン膜７を
はさんで形成され、外部との接続のために穴をあけた８
７０２パツシベー７ヨン膜９が形成されている。この孔
をおおうようにクロム０．１８ｍ１銅１μｍ１金０．１
μｍの複合膜を金属マスクを介して蒸着し、シリコンチ
ップ側はんだ行電極４を形成する。蒸着温度は、クロム
及び銅については膜の密着性を増すために３５００．ま
た金では金の拡散を防止するために１００Ｃとしている
。それぞれの膜の役割について簡単に１悦明するっクロ
ムは下地のアルミニウム配線膜８及び５ｉ０２パツシベ
ーシヨン膜９との密着及びはんだ３とアルミニウム配線
膜８との反応防止、銅ははんだ３との接着、金は銅の酸
化防止のために用いられる。(a) On a silicon substrate 6 on which transistors, diodes, etc. have already been formed, an aluminum wiring film 8 for wiring is formed with a 5JCh passivation film 7 for insulation in between, and holes are formed for connection with the outside. Opened 8
A 702 passivation film 9 is formed. Cover this hole with 0.18 m of chromium, 1 μm of copper, and 0.1 m of gold.
A composite film having a thickness of μm is deposited through a metal mask to form solder row electrodes 4 on the silicon chip side. The deposition temperature was 3500°C for chromium and copper to increase film adhesion. For gold, the temperature is set at 100C to prevent gold from spreading. Briefly explain the role of each film.Chromium adheres to the underlying aluminum wiring film 8 and 5i02 passivation film 9 and prevents reaction between the solder 3 and the aluminum wiring film 8.Copper adheres to the solder 3. Gold is used to prevent copper from oxidizing.

（ｂ）　　はんだを蒸着法によりシリコンチップ側はん
だ行電極４の上に形成する。蒸着順序は鉛膜１０→錫膜
１１である。必要なはんだ体積は９ＸＩＯ−’ｘ３であ
る。ここで、はんだの組成を鉛５０重量％、錫５０重量
％とするため鉛膜１０の膜厚を錫膜１１の膜厚の約半分
にしなければならないっこれは、鉛の比重が約１１であ
るのに対して錫の比重が約６であるだめである。(b) Solder is formed on the silicon chip side solder row electrodes 4 by vapor deposition. The deposition order is lead film 10→tin film 11. The required solder volume is 9XIO-'x3. Here, in order to make the solder composition 50% by weight of lead and 50% by weight of tin, the thickness of the lead film 10 must be approximately half the thickness of the tin film 11. This means that the specific gravity of lead is approximately 11. However, the specific gravity of tin is about 6.

（Ｃ）　　鉛膜１０及び４膜１１の形成されたンリコン
基板６を電気炉に入れ、鉛膜１０及び・錫膜１１を溶融
する。鉛と錫との共晶温度は約１８３Ｃであるので、約
１８３ｔｌｌ’を越えると徐々に鉛膜１０及び錫膜１１
がお互いの界面から溶融し始める。鉛５０重量％、錫５
０重量％のはんだの液相温度は約２１５Ｃであり、この
温度を越え臂 ると図に示すよりにほぼ球形のチップ側はんだ１２が形
成される。(C) The silicon substrate 6 on which the lead film 10 and the fourth film 11 have been formed is placed in an electric furnace, and the lead film 10 and the tin film 11 are melted. Since the eutectic temperature of lead and tin is about 183C, when it exceeds about 183tll', the lead film 10 and the tin film 11 gradually change.
begin to melt from their interface. 50% lead by weight, 5% tin
The liquidus temperature of 0% by weight solder is approximately 215C, and when this temperature is exceeded, a substantially spherical chip-side solder 12 is formed as shown in the figure.

（ｄ）　　アルミナ−ニラミック基板２には、グリーン
シート法によりアルミナセラミック基板側はんだ行電極
５が形成されており、その表面には鉛５０重量％、錫５
０重量−のアルミナセラミック基板側はんだ１３が形成
されている。チップ側はんだ１２がすでに形成されてい
る７リコン基板６をダイサーを用いてシリコンチップ１
に分離し、ハーフミラ−を用いてアルミナセラミック基
板側はんだ１３がすでに形成されているアルミナセラミ
ック基板２に位置合せする。その泌、シリコンチップ１
とアルミナセラミック基板２がチップ側はんだ１２とア
ルミナセラミック基板側はんだ１３とで接触した′１ま
、再度、炉中で鉛５０重骨チ、錫５０重量％のはんだの
１皮相＋！＋Ａ度より少し高いｉＡＡ度まで加熱すると
８ｒ！１図に示すようなパッケージ構造体が完成する。(d) The alumina ceramic substrate side solder row electrode 5 is formed on the alumina-niramic substrate 2 by the green sheet method, and the surface thereof is made of 50% by weight of lead and 5% by weight of tin.
A zero weight alumina ceramic substrate side solder 13 is formed. A silicon chip 1 is attached to the silicon substrate 6 on which the chip-side solder 12 has already been formed using a dicer.
Then, using a half mirror, the alumina ceramic substrate side solder 13 is aligned to the alumina ceramic substrate 2 on which the solder 13 has already been formed. The secretion, silicon chip 1
When the alumina ceramic substrate 2 was brought into contact with the chip-side solder 12 and the alumina ceramic substrate-side solder 13, the solder of 50% lead and 50% tin was applied again in the furnace. When heated to iAA degree, which is slightly higher than +A degree, it is 8r! A package structure as shown in Figure 1 is completed.

不実施レリによれば、はんだ３を鉛９５重量％、錫５重
量％のはんだで形成した従来のパッケージ（１“り；立
体に比べて一５５′Ｃ〜１５０１１：”、１時間ｌサイ
クルの温度タイクル試験による熱疲労寿命は約９倍と）
ＮＬｌ的に向上した。たたし、錫の含有量が増したため
はんだ３とシリコンチップ側はんだ対電極４中の銅との
反応が従来のパッケージ構造体に比べて著しくなる懸念
が生じる。そこで鉛９５重量％１、錫５重量％のはんだ
と鉛５０重量％、錫５０重１ｔチのはんだの銅への侵食
量を調べた。その箱果、第３図に示すように同一温度で
比較すると鉛５０重量％、錫５０！［）チはんだの方が
侵食量は多いが、鉛５０重量％、錫５０重量％はんだは
液相温度が鉛９５重量％、錫５重賛チはんだより約１０
０Ｃ低いので液相温度より５００高い温度（はんだ付の
作業温度としては大体この程度の温度が選ばれる）で比
較するとわずかの増加であり、銅の膜厚である１μｍに
は充分のゆとりがあることがわかった。According to the non-implemented report, the solder 3 was made of 95% lead by weight and 5% tin by weight in a conventional package (1"); Thermal fatigue life according to temperature cycle test is approximately 9 times longer)
Improved in terms of NLl. However, due to the increased tin content, there is a concern that the reaction between the solder 3 and the copper in the solder counter electrode 4 on the silicon chip side will be more significant than in the conventional package structure. Therefore, the amount of corrosion of copper by solder containing 95% lead and 5% tin by weight and solder containing 50% lead and 50% tin by 1 ton was investigated. As shown in Figure 3, when compared at the same temperature, the box fruit contains 50% lead and 50% tin! [)Although the amount of corrosion is higher with 50% lead and 50% tin solder, the liquidus temperature is about 10% lower than that of 95% lead and 50% tin solder.
Since it is 0C lower, it is a slight increase compared to a temperature 500 degrees higher than the liquidus temperature (about this temperature is usually chosen as the working temperature for soldering), and there is plenty of room for the copper film thickness of 1μm. I understand.

鉛５０重量％、錫５０重量％はんだがこのように良好な
耐熱疲労特性を示した理由について第５図を用いて説明
する。第５１’；４ｆは本発明によるパッケージ構造体
を括々の冷却速度ではんだ付した場合のせん断強さ及び
はん１との組成を示したものである。ここで、第５図（
ａ）に示すように本実ａＰＪのはんだＭｌ＠は大きな粒
径のα初晶（図中の黒い領域）の周囲を比較的大きな粒
径の共晶が包囲する形態をなしている。これに対して、
第５図（ｂ）に示すように、はんだの冷却速度が大きい
と、比較的小さい粒径のα初晶（図中の黒い領域）の周
囲を微細な共晶が包囲する形態となる。同図Φ）に示す
ように比較的小さい粒径のα初晶（図中の黒い領域）の
周囲を微１ｊ口な共晶が包囲する形態の場合には、すで
に述べた超塑性現象のために、はんだの塑性変形態が大
きいが、同図（ａ）に示すように、大きな粒径のα初晶
（図中の黒い領域）の周囲を比較的大きな粒径の共晶が
包囲する形態では、初品のα晶に共晶組織が食いこみは
んだの変形態が阻害され、共Ｐａ組織の超！Ｉｌ性現象
も初晶のα晶に阻害されるため、はんだの塑性変形態が
小さくなシ、熱疲労寿命を廷ばしたためである。このよ
うなはんだの性質は、ｉｔ来、半導体チップの接続には
好ましくないと考えられていた。ところが、はんだの・
周性変形通を犬きクシて；Ａ歪とすべてはんだに待たせ
るという従来の設計より、むしろ、はんだの塑性変形態
を制限して熱歪をはんだと周囲の部材で分担する設計の
方が良好な耐熱疲労特性を示すことがわかった。さらに
、同図（ａ）に示すように大きな粒径のα初晶（図中の
黒い領域）の周囲を比較的大きな粒径の共晶が包囲する
形態では、はんだの強度も大きく、さらに熱疲労寿命を
延ばしている。図から明らかなように、はんだの強度を
安定して大きくするには冷却速度を約１２５０／分以下
にしなければならない。The reason why the 50 weight % lead and 50 weight % tin solder exhibited such good thermal fatigue resistance will be explained with reference to FIG. 51'; 4f shows the shear strength and composition with solder 1 when the package structure according to the present invention is soldered at a batch cooling rate. Here, Figure 5 (
As shown in a), the solder Ml@ of the actual aPJ has a form in which α primary crystals with a large particle size (black area in the figure) are surrounded by eutectic crystals with a relatively large particle size. On the contrary,
As shown in FIG. 5(b), when the cooling rate of the solder is high, a fine eutectic crystal surrounds α primary crystals (black areas in the figure) having a relatively small particle size. As shown in Φ) in the same figure, in the case of a relatively small-sized α primary crystal (black area in the figure) surrounded by a microscopic eutectic, due to the superplastic phenomenon mentioned above, In this case, the plastic deformation of the solder is large, but as shown in Figure (a), a relatively large grain size eutectic surrounds a large grain size α primary crystal (black area in the figure). In this case, the eutectic structure bites into the α crystal of the initial product, inhibiting the deformation of the solder, and the super! This is because the Il-like phenomenon is also inhibited by the primary α-crystal, so the plastic deformation of the solder is small and the thermal fatigue life is lengthened. Such properties of solder have long been thought to be unfavorable for connecting semiconductor chips. However, the solder...
Rather than the conventional design that avoids circumferential deformation and makes the solder wait for all the A strain, it is better to limit the plastic deformation of the solder and share the thermal strain between the solder and surrounding components. It was found that it exhibited good thermal fatigue resistance. Furthermore, as shown in Figure (a), in a form in which a relatively large grain size eutectic surrounds a large grain size α primary crystal (the black area in the figure), the solder strength is high and the temperature increases even further. Extends fatigue life. As is clear from the figure, in order to stably increase the strength of the solder, the cooling rate must be approximately 1250/min or less.

ここで、本実施例ではシリコンチップ側はんだ付電極４
にクロム、銅及び金の複合膜を使ったが、クロムと同じ
働きをする金属としてチタン、銅と同じ働きをする金属
としてニッケルを使用しても同じ結果が得られることは
もちろんである。また、シリコンチップ側はんだ付電極
４をマスク蒸着法で形成したが、もちろん全面蒸着後に
エツチングを施こして電極パターンを形成してもよい。Here, in this embodiment, the silicon chip side soldered electrode 4
Although a composite film of chromium, copper, and gold was used for this purpose, it goes without saying that the same results can be obtained by using titanium, which is a metal that has the same function as chromium, and nickel, which is a metal that has the same function as copper. Furthermore, although the silicon chip side solder electrodes 4 are formed by mask vapor deposition, it goes without saying that the electrode pattern may be formed by performing etching after the entire surface vapor deposition.

さら　　　　　　１に、蒸着でなく、その他の方法（例
えば、スパッタリング）で形成してもよい。チップ側は
んだ１２の形成法は、蒸着法に限らずめっき法を採用し
てもよいことも当然である。また、チップ側はんだ１２
とアルミナセラミック基板側はんだ１３の組成は錫が４
０重量％を越え、６０重量％未満で残部が実質的に鉛で
あれば、すでに述べたように、はんだ付の冷却速度を約
１２５Ｇ／分以下にすることで、鉛９５重量％、錫５重
量％はんだより大きい熱疲労寿命かえられる（第４図参
照）。Furthermore, first, it may be formed by other methods (for example, sputtering) instead of vapor deposition. It goes without saying that the method for forming the chip-side solder 12 is not limited to the vapor deposition method, but may also be a plating method. In addition, the chip side solder 12
The composition of the solder 13 on the alumina ceramic board side is 4% tin.
If it exceeds 0% by weight and less than 60% by weight and the balance is substantially lead, as mentioned above, by setting the cooling rate for soldering to about 125G/min or less, 95% by weight of lead and 5% of tin can be reduced. It has a greater thermal fatigue life than solder by weight (see Figure 4).

〔発明の効果〕〔Effect of the invention〕

本発明によれば、半導体基体と誘電体基板間を眠気的、
かつ、機械的に結合するための微細、かつ、多数の微小
はんだ群の組成は錫が４０重量％を趣え、６０重祉チ未
満で残部が実質的に鉛であり、大きな粒径のα初晶の周
囲を比較的大きな粒径の共晶が包囲する組織を呈してい
れば鉛９５重（′ｉｉ：チ、錫５重量％はんだよシ大き
い熱疲労寿命かえられる。According to the present invention, between the semiconductor substrate and the dielectric substrate,
Moreover, the composition of the fine and large number of microscopic solder groups for mechanical bonding is approximately 40% by weight of tin, less than 60% by weight, and the remainder is substantially lead, with α of large particle size. If the primary crystal is surrounded by a eutectic with a relatively large grain size, the thermal fatigue life will be longer than that of a 5% tin solder.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明による一実施例の断面図、第２図は本発
明による実施列の製造工程を示す断面図、第３図は本発
明による実施タリと従来列のはんだによる侵食量を比較
するグラフ、第４図は本発明の効果を示すグ２）、第５
図は本発明の効果を示すグラフである。 ■・・・シリコンチップ、２・・・アルミナセラミック
基板、３・・・はんだ、４．５・・・はんだ付電極。Fig. 1 is a cross-sectional view of one embodiment of the present invention, Fig. 2 is a cross-sectional view showing the manufacturing process of an embodiment row according to the present invention, and Fig. 3 is a comparison of the amount of erosion by solder between the embodiment of the present invention and a conventional row. Graphs 2) and 5 show the effects of the present invention.
The figure is a graph showing the effects of the present invention. ■...Silicon chip, 2...Alumina ceramic substrate, 3...Solder, 4.5...Soldered electrode.

Claims (1)

【特許請求の範囲】 １、半導体基体と誘電体基板間を複数個の微小はんだ群
により電気的、かつ、機械的に結合する半導体パッケー
ジ構造体において、 前記微小はんだ群の組成が錫の重量比で４０％を越え６
０％未満であり、残部が実質的に鉛であることを特徴と
する半導体パッケージ構造体。[Claims] 1. A semiconductor package structure in which a semiconductor substrate and a dielectric substrate are electrically and mechanically coupled by a plurality of micro solder groups, wherein the composition of the micro solder groups is a weight ratio of tin. over 40%6
1. A semiconductor package structure characterized in that lead is less than 0% and the remainder is substantially lead.
JP20170884A 1984-07-03 1984-09-28 Semiconductor package structure Pending JPS6180828A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP20170884A JPS6180828A (en) 1984-09-28 1984-09-28 Semiconductor package structure
DE3523808A DE3523808C3 (en) 1984-07-03 1985-07-03 Process for soldering parts of an electronic arrangement made of different materials and its use

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20170884A JPS6180828A (en) 1984-09-28 1984-09-28 Semiconductor package structure

Publications (1)

Publication Number Publication Date
JPS6180828A true JPS6180828A (en) 1986-04-24

Family

ID=16445607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20170884A Pending JPS6180828A (en) 1984-07-03 1984-09-28 Semiconductor package structure

Country Status (1)

Country Link
JP (1) JPS6180828A (en)

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