JPS6171654A - Method of solder film adhesion to dip type ic - Google Patents
Method of solder film adhesion to dip type icInfo
- Publication number
- JPS6171654A JPS6171654A JP59195092A JP19509284A JPS6171654A JP S6171654 A JPS6171654 A JP S6171654A JP 59195092 A JP59195092 A JP 59195092A JP 19509284 A JP19509284 A JP 19509284A JP S6171654 A JPS6171654 A JP S6171654A
- Authority
- JP
- Japan
- Prior art keywords
- flux
- lead terminals
- excess amount
- solder
- dipping process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 25
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 16
- 230000004907 flux Effects 0.000 claims abstract description 27
- 230000008569 process Effects 0.000 claims abstract description 17
- 238000007598 dipping method Methods 0.000 claims abstract description 8
- 238000001179 sorption measurement Methods 0.000 abstract description 3
- 238000004804 winding Methods 0.000 abstract description 2
- 239000006185 dispersion Substances 0.000 abstract 1
- 230000009471 action Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000004209 hair Anatomy 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4835—Cleaning, e.g. removing of solder
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、Ｄ工Ｐ型ＩＣのリード端子に薄く半田の被
膜を付設形成するだめの方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming a thin solder coating on lead terminals of a D-type P-type IC.
上記半田被膜形成は、後にＩＣをプリント基板に半田付
けする際の半田の付着性を高めるために施こされる前処
理工程であり、従来は、先ずフラックスディッピング工
程でフラックスをリード端子に付着させ、次に半田ディ
ノビング工程でり−ド端子に半田被膜を付着させる方式
がとられている０
〔発明が解決しようとする問題点〕
ところが、第４図に示すように、ＤＩＰ型ＩＣ１は、パ
ッケージ２の両側から出たリード端子３群が下方に大き
く屈折された形態となっているために、フラックスディ
ッピング工程でフラックスが余分に付着して第５図に示
すように、リード端子３の屈折基部や下端に余剰フラッ
クス４が残存してしまうことがある。The above-mentioned solder film formation is a pretreatment process performed to improve the adhesion of solder when soldering the IC to a printed circuit board later. Conventionally, flux was first attached to the lead terminals in a flux dipping process. Then, a method is adopted in which a solder film is attached to the lead terminal in a soldering process.0 [Problems to be Solved by the Invention] However, as shown in FIG. Since the 3 groups of lead terminals coming out from both sides of the lead terminal 2 are bent greatly downward, excess flux adheres during the flux dipping process, causing the bent base of the lead terminal 3 to become attached as shown in FIG. Surplus flux 4 may remain at the lower end.
そして、このように余剰フラックスが残存したま＼で半
田ディッピング工程に移されると、フラックス自体の温
度が常温であるのに対して半田（／１２６０°Ｃ程度の
高温であるために、両者の温度差が原因で半田粒が生じ
、これが飛散してパッケージ部分に付着して外観不良を
きたしたり、リード端子間の絶縁不良をもたらし、製品
の歩留りを低減する問題があった。When the surplus flux is transferred to the solder dipping process while it remains, the temperature of the solder (about 1260°C) is high, while the flux itself is at room temperature. Due to the difference, solder grains are generated, which scatter and adhere to the package part, resulting in poor appearance, poor insulation between lead terminals, and a reduction in product yield.
上記問題を解決するために、本発明では第１図に示すよ
うに、フラノクスデイノビング工程と半田テイノピング
工程との間に、余剰フラックス吸着除去工程を導入し、
かつ、この除去工程としてリード端子に密植ブラシを接
触させる方式を採用した。In order to solve the above problem, in the present invention, as shown in FIG. 1, an excess flux adsorption removal process is introduced between the furanox deinobing process and the solder deinoping process,
In addition, for this removal process, a method was adopted in which a densely planted brush was brought into contact with the lead terminals.
リード端子にブラシを接触させると、プラン間の毛細管
現象で余剰フラックスが吸着され、周囲に飛び散らされ
ることなく静かに除去されることになる。When the brush is brought into contact with the lead terminal, excess flux is adsorbed by capillary action between the plans and is gently removed without being scattered around.
第２図及び第３図に余剰フラックス除去手段の一例が示
される。ワークとしてのＤ工Ｐ型ＩＣ１をワークキャリ
ア５に吸引チャック等の適宜手段を用いて保持され、リ
ード端子３を下向きにした姿勢で図中左方に一定速度で
送られる。ワーク移動径路の下側には、ベルト６にリー
ド端子３よりも伎い細毛を密植したブラシ７が平行に巻
回張設され、その毛先がリード端子３の基部に達するよ
う配備され、端子基部の屈折部や端子下端に残存した余
剰フラックスを毛細管現象てブラシ７内（で吸着除去す
るよう構成されている。又、上記プラン７は一定時間ご
と例適当ストロークで回動するか、連続的に微速で回動
させて、新し１ハブラン部分を順次作用させる。又、ブ
ラン７自体を清掃するためて、プランベルトの巻回径路
中に、ブラシ７に機械的振動を与えてフラックスをはら
い落とす手段や、吸引除去する手段、もしくはフラック
ス溶解洗浄手段などのプラン清掃機構８を配備しておく
と、長時間の連続運転が可能になる。An example of surplus flux removal means is shown in FIGS. 2 and 3. A D-type P-type IC 1 as a workpiece is held on a workpiece carrier 5 using an appropriate means such as a suction chuck, and is sent to the left in the figure at a constant speed with the lead terminal 3 facing downward. Below the workpiece movement path, a brush 7 in which fine hairs thicker than the lead terminals 3 are densely planted is wound around the belt 6 in parallel, and the brush 7 is arranged so that the tips of the bristles reach the base of the lead terminals 3. The brush 7 is configured to adsorb and remove excess flux remaining at the bent portion of the base or the lower end of the terminal by capillary action within the brush 7. Also, the plan 7 is rotated at regular intervals, for example, with an appropriate stroke, or is rotated continuously. The brush 7 is rotated at a slow speed to act on the new hub run parts one after another.Also, in order to clean the hub run 7 itself, mechanical vibration is applied to the brush 7 during the winding path of the plan belt to remove the flux. If a plan cleaning mechanism 8 such as a dropping means, a suction removing means, or a flux dissolving and cleaning means is provided, continuous operation for a long period of time becomes possible.
尚、上記実施例はワークを連続移送しながらの余剰フラ
ックス除去手段の一例を示したが、単一もしくは複数の
ワークを保持したキャリアを静置しであるブラフ上に下
降接触、もしくは逆にプランを上昇して接触させる、等
の間欠的なプラノ接触形態をとることも可能である。Although the above embodiment shows an example of a means for removing surplus flux while continuously transporting the workpieces, it is also possible to lower the carrier holding a single workpiece or a plurality of workpieces and bring it into contact with the bluff, or conversely, to remove surplus flux by moving the workpieces continuously. It is also possible to use an intermittent form of plano contact, such as by raising the surface of the contact surface.
以上説明したように、本発明ではリード端子に付着残存
した余剰フラックスを除去するのに、ブラシとの接触に
よる成層除去方式を採用したので、他の方法による短い
保全間隔及び必要フラックスの除去といった問題もなく
、余剰フラックスのみを静かに確実に除去することが可
能となり、後の半田デイノピング工程でのトラブルを無
くすことができた。As explained above, in the present invention, in order to remove excess flux remaining on the lead terminal, a stratified layer removal method using contact with a brush is adopted. This made it possible to quietly and reliably remove only the excess flux, eliminating troubles in the subsequent solder denoping process.
第１図は本発明方法の処理工程のフローチャート、第２
図は余剰フラックス除去手段の一例を示す側面図、第３
図はその正面図、第４図はＤ工Ｐ型ＩＣの斜視図、第５
図は余剰フラックスの付着残存したＩＣの正面図である
。
３・・リード端子、７・・プラン。
出 願 人 ローム株式会社
代 理 人 弁理士岡田和秀FIG. 1 is a flowchart of the processing steps of the method of the present invention, and FIG.
The figure is a side view showing an example of a means for removing surplus flux.
The figure is a front view, Figure 4 is a perspective view of the D type P type IC, and Figure 5 is a perspective view of the D type P type IC.
The figure is a front view of an IC to which excess flux remains attached. 3. Lead terminal, 7. Plan. Applicant: ROHM Co., Ltd. Agent: Kazuhide Okada, patent attorney
Claims (1)
スディッピング工程と、リード端子３を密植したブラシ
７に接触させて余剰フラックスをブラシ７に吸着させる
工程と、リード端子３に半田被膜を付着させる半田ディ
ッピング工程とからなるＤＩＰ型ＩＣの半田被膜付着方
法。(1) A flux dipping process in which flux is attached to the lead terminals 3, a process in which the lead terminals 3 are brought into contact with the densely planted brushes 7 to adsorb excess flux to the brushes 7, and a solder dipping process in which a solder film is attached to the lead terminals 3. A method for attaching a solder film to a DIP type IC, which comprises the steps of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59195092A JPS6171654A (en) | 1984-09-17 | 1984-09-17 | Method of solder film adhesion to dip type ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59195092A JPS6171654A (en) | 1984-09-17 | 1984-09-17 | Method of solder film adhesion to dip type ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6171654A true JPS6171654A (en) | 1986-04-12 |
Family
ID=16335397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59195092A Pending JPS6171654A (en) | 1984-09-17 | 1984-09-17 | Method of solder film adhesion to dip type ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6171654A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5517669B2 (en) * | 1972-03-16 | 1980-05-13 | ||
| JPS5637913U (en) * | 1979-09-03 | 1981-04-10 |
-
1984
- 1984-09-17 JP JP59195092A patent/JPS6171654A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5517669B2 (en) * | 1972-03-16 | 1980-05-13 | ||
| JPS5637913U (en) * | 1979-09-03 | 1981-04-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6066500A (en) | Part mounting device | |
| JPS6171654A (en) | Method of solder film adhesion to dip type ic | |
| US4125216A (en) | Apparatus for accomplishing solder bonding | |
| US4491084A (en) | Apparatus for solder tinning of component leads | |
| US20040003891A1 (en) | Apparatus and method for application of adhesive substances to objects | |
| JP2596647B2 (en) | Cleaning device for conductive paste transfer pin or semiconductor chip collet pin | |
| JPH04210267A (en) | Coating device of conductive paste for connecting external terminal | |
| JPH06215991A (en) | Apparatus for applying metal paste to terminal part of chip | |
| CN213770854U (en) | Wire take-up device for conical take-up reel | |
| US6322855B1 (en) | Method and apparatus for coating conductive metal onto an electrode for surface mounting chip components | |
| JPH0237492Y2 (en) | ||
| JPH032581B2 (en) | ||
| JPS58142556A (en) | Coating method of solder to lead conductor of semiconductor device | |
| JPS6111287U (en) | Automatic terminal crimping device for covered wires | |
| JPH0685062U (en) | Coating device | |
| JPS6171866A (en) | Method for applying coating material for electronic parts | |
| JPH05190403A (en) | Method and apparatus for solder coating of axial lead component | |
| JP3020797U (en) | Solder oxide film removal device | |
| JPH06215918A (en) | Electrode paint applicator for strip-shaped board | |
| JPH10314634A (en) | Coating device | |
| JPH01246839A (en) | Die bonding | |
| JPH02135180A (en) | Method for applying photoresist | |
| JPS6092627A (en) | Mounting method of chip | |
| JPH0213552A (en) | Feeding device for part | |
| GB2222788A (en) | Coating electronic parts |