JPS6167247A - 混成集積回路 - Google Patents

混成集積回路

Info

Publication number
JPS6167247A
JPS6167247A JP59189145A JP18914584A JPS6167247A JP S6167247 A JPS6167247 A JP S6167247A JP 59189145 A JP59189145 A JP 59189145A JP 18914584 A JP18914584 A JP 18914584A JP S6167247 A JPS6167247 A JP S6167247A
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
protection material
resin
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59189145A
Other languages
English (en)
Inventor
Yuji Goto
優治 後藤
Fumiyoshi Matsumura
松村　文好
Masao Ushigome
牛込　雅夫
Shigenori Yamaoka
重徳 山岡
Shigehiko Sakura
桜　茂彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Sumitomo Bakelite Co Ltd
Original Assignee
NEC Corp
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Sumitomo Bakelite Co Ltd filed Critical NEC Corp
Priority to JP59189145A priority Critical patent/JPS6167247A/ja
Publication of JPS6167247A publication Critical patent/JPS6167247A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （技術分野） 本発明は混成集積回路に関し、とくにその回路保護材料
とその応用に関するものでろる。
（従来技術） 混成集積回路に於て、現在、もっとも一般的な構造は外
装材料にエポキシ粉体塗装を用いたものである。この構
造に関して、内包される回路には受動部品、能動部品、
更に端子、接続線等の構造材が様々な形状で搭載されて
いる。このような混成集積回路を完成させるためには、
製造工程、及び使用環境の種々の条件によシ発生する湿
度及び熱的ストレスによって、搭載部品や回路基板等が
劣化しないように保護しなければならない。この保護材
料として、従来一般的に用いられてきたものは、シリコ
ン樹脂である。シリコン樹脂を保護材料として観た場合
、電気的には安定であるという利点があるが、湿度環境
に弱く電子部品、特に半導体チア１表面がアルミニウム
電極の場合は、電極の腐食をひきおこしやすい。また、
シリコン樹脂の密着性が弱いために、保護材料の外装と
して用いられるエポキシ樹脂が熱的ストレスにより割れ
やすいという現象がひきおこす。この傾向は電子部品の
高密度化、高信頼度化がますます要求される今後におい
て重要な問題となっている。
（発明の目的） 本発明の目的は上記の不都合を解決する構成を提供する
ことにある。
（発明の構成） 本発明の構成は、従来、一般的に用いられていたシリコ
ン系樹脂による混成集積回路の中間保護をポリブタジェ
ン系の樹脂によって行うものでめる０ （発明の作用） 第１図に示すように混成集積回路の中間保護材料２は緩
衝剤としての効果として回路側に対しては、湿度及び熱
的ストレスよシ保護をしながらも適度の’ＦＥＮ力を保
つことが必要でおシ、エポキシ樹脂等の外装材１に対し
ても、混成集積回路全体としての機械的強度が保たれる
よう密層することが必要でめる。また半導体チップ５は
シリコン樹脂３でプリコート嘔れている。
（発明の効果） 本発明のポリブタジェン系樹脂によると樹脂材料の性質
から吸湿性、水透過性、密着性がすぐれてｊ？、ｏ、’
Ｅた％搭載部品として使用される高集積度ＩＣ素子に対
しても十分な不純物対策がなさｎたものでるる。
本発明に於けるポリブタジェン系樹脂とは、ブタジェン
を単独重合、又は他の重合性成分と共重合させたポリマ
ー及び該ポリマーに反応性官能基を導入したポリマー及
び前述した官能基導入ポリマーの炭素間二重結合を全部
又は一部分水素還元したポリマーを意味する。このポリ
ブタジェン系樹脂は、直鎖状構造であっても、三次元網
状構造であってもよく、エラストマーであればよい。
本発明の結果、湿度ストレスの耐性１判断に用いられる
グレアシャー・り、カー・テス）　（Ｐ、Ｃ，Ｔ　）に
於てシリコン系樹脂による中間保護材料の１０倍以上の
寿命特性となシ、また、熱的ストレスの耐性１判断に用
いられる温度サイクル・テス）　（Ｔ。
Ｃ）に於ても１０倍以上の寿命特性が借られている０ （発明のまとめ） 混成集積回路の中間保護材料（緩衝剤）としては、シリ
コン糸の樹脂が一般的でめったが、信頼性品質の要求が
高するにつれて湿度的、熱的な限界があることが判明し
た。本発明によって、上記の欠陥に対して一応の対策が
行われるので、混成集積（ロ）路の利用範囲の拡大、信
頼性品質の向上が期待出来る。
【図面の簡単な説明】
第１図は本発明に二る混成集積回路の一実施例の構造を
示す概略断面図である。 １・・・・・・外装材料、２・・・・・・中間保護材料
（緩衝剤）、３・・・・・・半導体素子の保護材料、４
・・・・・・混成集積回路回路基板。

Claims (1)

    【特許請求の範囲】
  1. 　基板上に部品を搭載して中間保護材料を介して外装し
    た混成集積回路において、前記中間保護材料としてポリ
    ブタジエン系樹脂を用いることを特徴とする混成集積回
    路。
JP59189145A 1984-09-10 1984-09-10 混成集積回路 Pending JPS6167247A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59189145A JPS6167247A (ja) 1984-09-10 1984-09-10 混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59189145A JPS6167247A (ja) 1984-09-10 1984-09-10 混成集積回路

Publications (1)

Publication Number Publication Date
JPS6167247A true JPS6167247A (ja) 1986-04-07

Family

ID=16236169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59189145A Pending JPS6167247A (ja) 1984-09-10 1984-09-10 混成集積回路

Country Status (1)

Country Link
JP (1) JPS6167247A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1995015579A1 (fr) * 1993-11-30 1995-06-08 Giat Industries Procede d'encapsulation de composants ou de modules electroniques et dispositfs encapsules par ledit procede
US6191492B1 (en) * 1988-08-26 2001-02-20 Semiconductor Energy Laboratory Co., Ltd. Electronic device including a densified region
US6756670B1 (en) 1988-08-26 2004-06-29 Semiconductor Energy Laboratory Co., Ltd. Electronic device and its manufacturing method
US6888259B2 (en) * 2001-06-07 2005-05-03 Denso Corporation Potted hybrid integrated circuit
WO2018066453A1 (ja) * 2016-10-05 2018-04-12 ミネベアミツミ株式会社 平面スイッチ

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6191492B1 (en) * 1988-08-26 2001-02-20 Semiconductor Energy Laboratory Co., Ltd. Electronic device including a densified region
US6756670B1 (en) 1988-08-26 2004-06-29 Semiconductor Energy Laboratory Co., Ltd. Electronic device and its manufacturing method
WO1995015579A1 (fr) * 1993-11-30 1995-06-08 Giat Industries Procede d'encapsulation de composants ou de modules electroniques et dispositfs encapsules par ledit procede
FR2713396A1 (fr) * 1993-11-30 1995-06-09 Giat Ind Sa Procédé d'encapsulation de composants ou de modules électroniques et composants ou modules électroniques encapsulés par ledit procédé.
US6888259B2 (en) * 2001-06-07 2005-05-03 Denso Corporation Potted hybrid integrated circuit
WO2018066453A1 (ja) * 2016-10-05 2018-04-12 ミネベアミツミ株式会社 平面スイッチ

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