JPH0456339B2 - - Google Patents
Info
- Publication number
- JPH0456339B2 JPH0456339B2 JP60162541A JP16254185A JPH0456339B2 JP H0456339 B2 JPH0456339 B2 JP H0456339B2 JP 60162541 A JP60162541 A JP 60162541A JP 16254185 A JP16254185 A JP 16254185A JP H0456339 B2 JPH0456339 B2 JP H0456339B2
- Authority
- JP
- Japan
- Prior art keywords
- partial product
- input
- column
- bit
- adder
- Prior art date
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- 238000000034 method Methods 0.000 claims description 18
- 230000000295 complement effect Effects 0.000 claims description 13
- 241000030538 Thecla Species 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
- G06F7/5306—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products
- G06F7/5312—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with row wise addition of partial products using carry save adders
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、二進数のデータをオペランドとする
並列乗算器に係り、特に変形ブース（Booth）の
アルゴリズムによる並列乗算器における部分積加
算回路に関するもので、８×８ビツトあるいはそ
れ以上の大規模な乗算器を１チツプの集積回路で
実現する場合に使用されるものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a parallel multiplier that uses binary data as an operand, and particularly to a partial product addition circuit in a parallel multiplier using a modified Booth algorithm. This is used when a large scale multiplier of 8 x 8 bits or more is implemented on a single chip integrated circuit.
従来、二進数の並列乗算を高速に実現するため
に種々の方式が提案されており、これらの方式は
「日経エレクトロニクス」1978年５月29日号P.76
〜89とか「コンピユータの高速演算方式」堀越監
訳、近代科学社、1980年、P.129〜213などに詳述
されている。これらのうちの一方式である変形二
次のBoothのアルゴリズムによる並列乗算器は、
ｎ×ｎビツトの乗算における部分積の数がｎ／２で
済み、たとえば、８ビツト×８ビツトの乗算器に
おける部分積を加算する回路として従来は第２図
に示すように構成されている。即ち、全加算器
FA…がアレイ状に配置されており、各列におけ
る下位２ビツトの全加算器はリツプルキヤリー方
式が採用されており、下位列で生成された和出力
信号は上位列の同じ桁に入力すると共に下位列で
生成されたキヤリー信号は上位列の１桁上位ビツ
トに入力するキヤリーセーブ方式が採用されてお
り、最終列はキヤリールツクアヘツド方式
（CLA方式、桁上げ先見方式）の加算器１が採用
されている。上記部分積加算回路において、最下
位列〜最上位列のｍ個（本例では４個）の部分積
入力X0〜X3を加算するためには全加算器列とし
て（ｍ−１）個あればよく、全加算器列をｍ個使
用した構成に比べて高速化、チツプ面積の小型化
が可能である。上記部分積入力X0〜X3は、被乗
数データＸに対する５種の部分積Ｘ，−Ｘ，2X，
−2X，０（または１）が乗算データＹを所定の論
理式に基いてデコードするデコーダ（図示せず）
の出力により選択回路（図示せず）で択一的に選
択したものである。図中〇印は、個々の選択回路
の選択出力（Xiビツト、iビツト、Xi-1ビツト、
Xi-1ビツト、“０”または“１”のいずれか１つ
の出力）である。そして、上記部分積入力（部分
積選択出力）X0〜X3と共に、部分積入力の符号
ビツトの処理のために必要な１ビツトの付加信号
SBが入力するようになつており、負の部分積入
力（−Ｘまたは−2X）の選択時には正の部分積
（Ｘまたは2X）の各ビツトを反転させた部分積入
力の最下位ビツト（LSB）に「２の補数」生成
用の信号CB0〜CB3（いずれも「１」）が加えられ
るようになつている。この場合、CB0以外の「２
の補数」生成用信号CB1〜CB3は、負符号の部分
積入力が入力する列より１つ上位の列における上
記部分積入力の最下位ビツトに相当するビツト位
置の全加算器に入力する（上位列がCLA方式加
算器１である場合にはそのキヤリー入力端Cioに
入力する）ようになつている。
In the past, various methods have been proposed to realize parallel multiplication of binary numbers at high speed, and these methods are described in "Nikkei Electronics" May 29, 1978 issue, p. 76.
~89, ``High-speed calculation method for computers,'' translated by Horikoshi, Kindai Kagakusha, 1980, pages 129-213. One of these methods, a parallel multiplier based on modified quadratic Booth's algorithm, is
The number of partial products in n.times.n bit multiplication is n/2, and for example, a circuit for adding partial products in an 8 bit.times.8 bit multiplier has conventionally been constructed as shown in FIG. i.e. full adder
FA... are arranged in an array, and the full adder for the lower two bits in each column uses a ripple carry method, and the sum output signal generated in the lower column is input to the same digit in the upper column. A carry save method is adopted in which the carry signal generated in the lower row is input to the upper bit of the upper digit in the upper row, and the last row is added to adder 1 of the carry look ahead method (CLA method, carry look ahead method). has been adopted. In the above partial product addition circuit, in order to add m (4 in this example) partial product inputs X 0 to X 3 from the lowest column to the highest column, (m-1) are used as a full adder array. It is only necessary to use m full adder arrays, and the speed can be increased and the chip area can be reduced compared to a configuration using m full adder arrays. The above partial product inputs X 0 to X 3 are five types of partial products X, -X, 2X,
-2X, 0 (or 1) is a decoder (not shown) that decodes the multiplied data Y based on a predetermined logical formula
The selection circuit (not shown) selectively selects the output from the selection circuit (not shown). The ○ marks in the figure indicate the selection outputs of the individual selection circuits (X i bit, i bit, X i-1 bit,
X i-1 bits, either "0" or "1" output). Along with the above partial product inputs (partial product selection outputs) X 0 to X 3 , a 1-bit additional signal necessary for processing the sign bit of the partial product input is added.
When the negative partial product input (-X or -2X) is selected, the least significant bit (LSB) of the partial product input is input by inverting each bit of the positive partial product (X or 2X). ) are added with signals CB 0 to CB 3 (all "1") for "two's complement" generation. In this case, “2” other than CB 0
The signals CB 1 to CB 3 for generating the complement of the partial product are input to the full adder at the bit position corresponding to the least significant bit of the partial product input in the column one higher than the column to which the partial product input with a negative sign is input. (If the upper row is CLA type adder 1, it is input to its carry input terminal Cio ).
ところで、上記従来の部分積加算回路において
は、全加算器アレイの各列の下位２ビツト分はリ
ツプルキヤリー方式にによりキヤリー信号が伝搬
されるので、乗算時間が増大するという欠点があ
つた。これを避けるため、各列の下位２ビツトの
加算をCLA方式で行なうものとすれば、回路の
ハードウエア量が増大し、集積回路化に際して全
加算器アレイにおける回路パターンの規則性が低
くなり、設計コストが高くなる。また、各列とも
キヤリーセーブ方式を採用するものとすれば、最
終列のCLA方式加算器１としてビツト数を下位
２ビツト分増やす必要が生じるので、そのキヤリ
ー入力端Cioに「２の補数」生成用信号CB3を入
力するためのパターンレイアウトが困難になる。
By the way, in the above-mentioned conventional partial product adder circuit, a carry signal is propagated for the lower two bits of each column of the full adder array by the ripple carry method, which has the disadvantage that the multiplication time increases. In order to avoid this, if the addition of the lower two bits of each column is performed using the CLA method, the amount of circuit hardware will increase, and the regularity of the circuit pattern in the full adder array will decrease when integrated circuits are integrated. Design cost increases. Furthermore, if the carry-save method is adopted for each column, it is necessary to increase the number of bits by the lower 2 bits of the CLA method adder 1 in the last column, so a "two's complement" number is generated at the carry input terminal C io. The pattern layout for inputting the signal CB 3 becomes difficult.
本発明は上記の事情に鑑みてなされたもので、
部分積加算回路の回路パターンの規則性が高くて
パターン設計が容易になり、乗算速度の高速化を
図り得る変形Boothのアルゴリズムによる並列乗
算器を提供するものである。
The present invention was made in view of the above circumstances, and
The present invention provides a parallel multiplier based on a modified Booth's algorithm that has a highly regular circuit pattern of a partial product addition circuit, facilitates pattern design, and can increase multiplication speed.
即ち、本発明は、変形Boothのアルゴリズムに
よる並列乗算器において、それぞれ部分積選択出
力が入力する各列加算器をキヤリーセーブ方式に
より構成し、上記部分積選択出力が負の部分積で
ある場合にその最下位ビツトに加えるべき「２の
補数」生成用信号を、最下位列加算器における上
記負の部分積選択出力の最下位ビツトに相当する
ビツト位置に入力するように構成してなることを
特徴とするものである。
That is, in the present invention, in a parallel multiplier based on a modified Booth's algorithm, each column adder to which a partial product selection output is input is constructed using a carry save method, and when the partial product selection output is a negative partial product, The ``2's complement'' generation signal to be added to the least significant bit is input to the bit position corresponding to the least significant bit of the negative partial product selection output in the least significant column adder. This is a characteristic feature.
これによつて部分積加算動作の高速化による乗
算動作の高速化が可能になり、各列加算器を構成
する全加算器のアレイは集積回路化に際して回路
パターンの規則性が高くなり、パターン設計が容
易になる。 This makes it possible to speed up the multiplication operation by increasing the speed of the partial product addition operation, and the array of full adders that make up each column adder has a highly regular circuit pattern when integrated circuits, and the pattern design becomes easier.
以下、図面を参照して本発明の一実施例を詳細
に説明する。
Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第１図は変形二次のBoothのアルゴリズムによ
る、たとえば８ビツト×８ビツトの並列乗算器に
おける部分積加算回路を示している。即ち、３入
力２出力の全加算器FA…がアレイ状に配置され
ており、この全加算器アレイの各列はリツプルキ
ヤリー方式が採用されることなく、下位列で生成
されたキヤリー信号が上位列の１桁上位ビツトに
入力するキヤリーセーブ方式が採用されており、
最終列にはCLA方式加算器１１が用いられてい
る。そして、１列目（最下位列）の全加算器FA
…には、最下位ビツトから所定の上位ビツトまで
第１の部分積入力X0が入力し、３ビツト目から
所定の上位ビツトまで第２の部分積入力X1が入
力する。２列目の全加算器FA…には、最下位ビ
ツトから所定の上位ビツトまでの前記１列目の全
加算器FA…からのキヤリー信号、和出力信号が
入力し、４ビツト目から所定の上位ビツトまで第
３の部分積入力X2が入力する。３列目の全加算
器FA…には、最下位ビツトから所定の上位ビツ
トまで前記２列目の全加算器FA…からのキヤリ
ー信号、和出力信号が入力し、５ビツト目から所
定の上位ビツトまで第４の部分積入力X3が入力
する。CLA方式加算器１１には、上記３列目の
全加算器FA…のキヤリー信号、和出力信号が入
力する。上記各部分積入力X0〜X3は、被乗数デ
ータに対する５種の部分積Ｘ，−Ｘ，2X，−2X，
０（または１）が乗数データＹを所定の論理式に
基いてデコードするデコーダ（図示せず）の出力
により選択回路（図示せず）で択一的に選択した
ものである。そして、上記部分積入力（部分積選
択出力）X0〜X3と共に、部分積入力の符号ビツ
トの処理のために必要な１ビツトの付加信号SB
が入力するようになつており、負の部分積入力
（−Ｘまたは−2X）の選択時には正の部分積（Ｘ
または2X）の各ビツトを反転させた部分積入力
の最下位ビツトに「２の補数」生成用信号CB0〜
CB3が加えられるようになつている。この場合、
部分積入力X0〜X3に各対応する「２の補数」生
成用信号CB0〜CB3は、全て１列目の全加算器
FA…のうち上記部分積入力X0〜X3の最下位ビツ
トに相当するビツト位置に加えられるようになつ
ている。即ち、１列目の全加算器FA…において、
最下位ビツトに第１の部分積入力X0に対する
「２の補数」生成用信号CB0が入力し、３ビツト
目に第２の部分積入力X1に対する「２の補数」
生成用信号CB1が入力し、５ビツト目に第３の部
分積入力X2に対する「２の補数」生成用信号
CB2が入力し、７ビツト目に第４の部分積入力
X3に対する「２の補数」生成用信号CB3が入力
する。 FIG. 1 shows a partial product addition circuit in, for example, an 8-bit by 8-bit parallel multiplier based on the modified quadratic Booth's algorithm. That is, full adders FA with 3 inputs and 2 outputs are arranged in an array, and the ripple carry method is not adopted in each column of this full adder array, and the carry signal generated in the lower column is sent to the upper column. A carry-save method is adopted in which data is input to the uppermost bit of the column.
A CLA type adder 11 is used in the last column. Then, the first column (lowest column) full adder FA
The first partial product input X 0 is input from the least significant bit to a predetermined upper bit, and the second partial product input X 1 is input from the third bit to a predetermined upper bit. The carry signal and sum output signal from the first column full adder FA from the least significant bit to a predetermined upper bit are input to the second column full adder FA... The third partial product input X2 is input up to the upper bits. The carry signal and sum output signal from the full adder FA in the second column are inputted to the full adder FA in the third column from the least significant bit to a predetermined upper bit, and from the fifth bit to a predetermined upper bit. The fourth partial product input X3 is input up to the bit. The CLA type adder 11 receives the carry signal and sum output signal of the third column full adder FA. The above partial product inputs X 0 to X 3 are five types of partial products X, −X, 2X, −2X,
0 (or 1) is alternatively selected by a selection circuit (not shown) based on the output of a decoder (not shown) that decodes the multiplier data Y based on a predetermined logical formula. Along with the above partial product inputs (partial product selection outputs) X 0 to X 3 , a 1-bit additional signal SB is required for processing the sign bit of the partial product input.
is input, and when negative partial product input (-X or -2X) is selected, positive partial product (X
or 2
CB 3 is about to be added. in this case,
The "2's complement" generation signals CB 0 to CB 3 corresponding to the partial product inputs X 0 to X 3 are all generated by the full adder in the first column.
Of the FA..., it is added to the bit position corresponding to the least significant bit of the partial product inputs X0 to X3 . That is, in the first column full adder FA...
The "two's complement" generation signal CB 0 for the first partial product input X 0 is input to the least significant bit, and the "two's complement" generation signal for the second partial product input X 1 is input to the third bit.
The generation signal CB 1 is input, and the "2's complement" generation signal for the third partial product input X 2 is input at the 5th bit.
CB 2 is input, and the 4th partial product is input at the 7th bit.
A "2's complement" generation signal CB 3 for X 3 is input.
上記部分積加算回路においては、「２の補数」
生成用信号CB0〜CB3が１列目の全加算器FA…
のうち対応する部分積入力X0〜X3の最下位ビツ
トに相当するビツト位置に加えられるので、加算
結果として従来例と同様に所要の部分積加算出力
が得られる。この場合、全加算器アレイの各列と
もリツプルキヤリー方式によらずキヤリーセーブ
方式による加算が行なわれるので、高速の乗算動
作が行なれることになる。また、「２の補数」生
成用信号CB0〜CB3を全加算器アレイの１列目に
入力し、各列をキヤリーセーブ方式の回路で構成
したので、集積回路化に際して回路パターンの規
則性が高くなり、パターン設計が容易になる。 In the above partial product addition circuit, "2's complement"
The generation signals CB 0 to CB 3 are sent to the first column full adder FA...
Since it is added to the bit position corresponding to the least significant bit of the corresponding partial product inputs X0 to X3 , the desired partial product addition output can be obtained as the addition result, as in the conventional example. In this case, since addition is performed in each column of the full adder array using the carry save method instead of the ripple carry method, high-speed multiplication operations can be performed. In addition, the "2's complement" generation signals CB 0 to CB 3 are input to the first column of the full adder array, and each column is configured with a carry-save circuit, so the regularity of the circuit pattern is improved when integrated circuits are integrated. This makes pattern design easier.
なお、上記全加算器アレイのうち半加算器で代
替し得る一部の全加算器（たとえば図中＊印を付
したもの）については、半加算器HAに置き換え
てもよい。 Note that some of the full adders (for example, those marked * in the figure) that can be replaced with half adders in the full adder array may be replaced with half adders HA.
上述したように本発明によれば、部分積加算回
路の回路パターンの規則性が高くてパターン設計
が容易になり、乗算速度の高速化を図ることがで
き、１チツプの集積回路化に適した変形Boothの
アルゴリズムによる並列乗算器を実現することが
できる。
As described above, according to the present invention, the circuit pattern of the partial product addition circuit has high regularity, making pattern design easy, increasing the multiplication speed, and making it suitable for one-chip integrated circuits. A parallel multiplier using a modified Booth's algorithm can be realized.
第１図は本発明の並列乗算器の一実施例の要部
を示すブロツク図、第２図は従来の並列乗算器の
一部を示すブロツク図である。
FA…全加算器、HA…半加算器、X0〜X3…部
分積選択出力、CB0〜CB3…「２の補数」生成用
信号。
FIG. 1 is a block diagram showing a main part of an embodiment of a parallel multiplier according to the present invention, and FIG. 2 is a block diagram showing a part of a conventional parallel multiplier. FA...full adder, HA...half adder, X0 to X3 ...partial product selection output, CB0 to CB3 ...signal for "two's complement" generation.
Claims (1)
並列乗算器において、それぞれ部分積選択出力が
入力する各列加算器をキヤリーセーブ方式により
構成し、上記部分積選択出力が負の部分積である
場合にその最下位ビツトに加えるべき「２の補
数」生成用信号を、最下位列加算器における上記
負の部分積選択出力の最下位ビツトに相当するビ
ツト位置に入力するように構成してなることを特
徴とする並列乗算器。 ２ 前記各列加算器を構成する複数の全加算器は
アレイ状に規則的に配置されてなることを特徴と
する前記特許請求の範囲第１項記載の並列乗算
器。 ３ 前記複数の全加算器は、一部が半加算器によ
り置き換えられることを特徴とする前記特許請求
の範囲第２項記載の並列乗算器。 ４ 最終段の加算器としてキヤリールツクアヘツ
ド方式加算器が用いられてなることを特徴とする
前記特許請求の範囲第１項記載の並列乗算器。[Claims] 1. In a parallel multiplier based on a modified Booth algorithm, each column adder to which a partial product selection output is input is constructed using a carry-save method, and the partial product selection output is a negative partial product. The ``two's complement'' generation signal to be added to the least significant bit in a certain case is configured to be input to the bit position corresponding to the least significant bit of the negative partial product selection output in the least significant column adder. A parallel multiplier that is characterized by the following: 2. The parallel multiplier according to claim 1, wherein the plurality of full adders constituting each column adder are regularly arranged in an array. 3. The parallel multiplier according to claim 2, wherein some of the plurality of full adders are replaced by half adders. 4. The parallel multiplier according to claim 1, wherein a carrier load type adder is used as the final stage adder.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60162541A JPS6222146A (en) | 1985-07-23 | 1985-07-23 | Parallel multiplier |
| EP86110067A EP0210579B1 (en) | 1985-07-23 | 1986-07-22 | Parallel multiplicator |
| DE8686110067T DE3686681T2 (en) | 1985-07-23 | 1986-07-22 | PARALLEL MULTIPLIER. |
| US06/888,080 US4791601A (en) | 1985-07-23 | 1986-07-22 | Parallel multiplier with a modified booth algorithm |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60162541A JPS6222146A (en) | 1985-07-23 | 1985-07-23 | Parallel multiplier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6222146A JPS6222146A (en) | 1987-01-30 |
| JPH0456339B2 true JPH0456339B2 (en) | 1992-09-08 |
Family
ID=15756565
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60162541A Granted JPS6222146A (en) | 1985-07-23 | 1985-07-23 | Parallel multiplier |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4791601A (en) |
| EP (1) | EP0210579B1 (en) |
| JP (1) | JPS6222146A (en) |
| DE (1) | DE3686681T2 (en) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5153847A (en) * | 1986-06-27 | 1992-10-06 | Matsushita Electric Industrial Co., Ltd. | Arithmetic processor using signed digit representation of internal operands |
| JPH07111678B2 (en) * | 1987-05-29 | 1995-11-29 | 松下電器産業株式会社 | Adder |
| US5206825A (en) * | 1987-05-27 | 1993-04-27 | Matsushita Electric Industrial Co., Ltd. | Arithmetic processor using signed-digit representation of external operands |
| JPS6453228A (en) * | 1987-08-24 | 1989-03-01 | Mitsubishi Electric Corp | Logic circuit for multiplier |
| KR920003908B1 (en) * | 1987-11-19 | 1992-05-18 | 미쓰비시뎅끼 가부시끼가이샤 | Multiplier |
| JPH07120272B2 (en) * | 1988-04-12 | 1995-12-20 | 日本電気株式会社 | Arithmetic operation circuit |
| JPH0776914B2 (en) * | 1988-10-18 | 1995-08-16 | 三菱電機株式会社 | Multiplication circuit |
| US5038315A (en) * | 1989-05-15 | 1991-08-06 | At&T Bell Laboratories | Multiplier circuit |
| US5262976A (en) * | 1989-11-13 | 1993-11-16 | Harris Corporation | Plural-bit recoding multiplier |
| US5412591A (en) * | 1990-08-09 | 1995-05-02 | Vlsi Technology, Inc. | Schematic compiler for a multi-format high speed multiplier |
| US5291431A (en) * | 1991-06-03 | 1994-03-01 | General Electric Company | Array multiplier adapted for tiled layout by silicon compiler |
| US5251167A (en) * | 1991-11-15 | 1993-10-05 | Amdahl Corporation | Method and apparatus for processing sign-extension bits generated by modified booth algorithm |
| US5361220A (en) * | 1991-11-29 | 1994-11-01 | Fuji Photo Film Co., Ltd. | Discrete cosine transformation with reduced components |
| US5477479A (en) * | 1993-03-08 | 1995-12-19 | Nkk Corporation | Multiplying system having multi-stages for processing a digital signal based on the Booth's algorithm |
| US5576765A (en) * | 1994-03-17 | 1996-11-19 | International Business Machines, Corporation | Video decoder |
| KR960042334A (en) * | 1995-05-15 | 1996-12-21 | 김주용 | Parallel Independent Multibit Adder |
| JP3351672B2 (en) * | 1995-12-20 | 2002-12-03 | 株式会社東芝 | Adder |
| JPH09269891A (en) * | 1996-04-01 | 1997-10-14 | Hitachi Ltd | Method and device for adding partial product, method and device for multiplying floating point, and method and device for floating point product-sum operation |
| US6183122B1 (en) * | 1997-09-04 | 2001-02-06 | Cirrus Logic, Inc. | Multiplier sign extension |
| US6687722B1 (en) * | 2000-03-16 | 2004-02-03 | Agere Systems, Inc. | High-speed/low power finite impulse response filter |
| GB0317570D0 (en) * | 2003-07-26 | 2003-08-27 | Koninkl Philips Electronics Nv | Long-integer multiplier |
| JP4170267B2 (en) * | 2004-07-09 | 2008-10-22 | Ｎｅｃエレクトロニクス株式会社 | Multiplication remainder calculator and information processing apparatus |
| JP4180024B2 (en) * | 2004-07-09 | 2008-11-12 | Ｎｅｃエレクトロニクス株式会社 | Multiplication remainder calculator and information processing apparatus |
| US7424507B1 (en) * | 2004-09-30 | 2008-09-09 | National Semiconductor Corporation | High speed, low power, pipelined zero crossing detector that utilizes carry save adders |
| US10831445B1 (en) * | 2018-09-20 | 2020-11-10 | Groq, Inc. | Multimodal digital multiplication circuits and methods |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5663649A (en) * | 1979-10-26 | 1981-05-30 | Nec Corp | Parallel multiplication apparatus |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4153938A (en) * | 1977-08-18 | 1979-05-08 | Monolithic Memories Inc. | High speed combinatorial digital multiplier |
| US4484301A (en) * | 1981-03-10 | 1984-11-20 | Sperry Corporation | Array multiplier operating in one's complement format |
| US4646257A (en) * | 1983-10-03 | 1987-02-24 | Texas Instruments Incorporated | Digital multiplication circuit for use in a microprocessor |
| US4575812A (en) * | 1984-05-31 | 1986-03-11 | Motorola, Inc. | X×Y Bit array multiplier/accumulator circuit |
-
1985
- 1985-07-23 JP JP60162541A patent/JPS6222146A/en active Granted
-
1986
- 1986-07-22 EP EP86110067A patent/EP0210579B1/en not_active Expired
- 1986-07-22 US US06/888,080 patent/US4791601A/en not_active Expired - Lifetime
- 1986-07-22 DE DE8686110067T patent/DE3686681T2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5663649A (en) * | 1979-10-26 | 1981-05-30 | Nec Corp | Parallel multiplication apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6222146A (en) | 1987-01-30 |
| DE3686681T2 (en) | 1993-02-04 |
| DE3686681D1 (en) | 1992-10-15 |
| EP0210579A3 (en) | 1990-01-10 |
| US4791601A (en) | 1988-12-13 |
| EP0210579B1 (en) | 1992-09-09 |
| EP0210579A2 (en) | 1987-02-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |