JPS6161671U - - Google Patents
Info
- Publication number
- JPS6161671U JPS6161671U JP14481584U JP14481584U JPS6161671U JP S6161671 U JPS6161671 U JP S6161671U JP 14481584 U JP14481584 U JP 14481584U JP 14481584 U JP14481584 U JP 14481584U JP S6161671 U JPS6161671 U JP S6161671U
- Authority
- JP
- Japan
- Prior art keywords
- tape
- digital data
- recording
- data
- head
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Digital Magnetic Recording (AREA)
Description
第１図はこの考案に係るデータ記録システムの
エラー検出回路の一実施例を示す構成図、第２図
及び第３図はそれぞれ同実施例の要部を示すブロ
ツク構成図及び同実施例の動作を説明するための
フローチヤート、第４図はこの考案の他の実施例
を示すブロツク構成図、第５図及び第６図はそれ
ぞれ従来のデータ記録システムを示す構成図及び
その動作を説明するためのフローチヤートである
。
１１……演算処理装置本体、１２……接続線、
１３……カセツトテープレコーダ、１４……演算
処理装置本体、１５……接続線、１６……カセツ
トテープレコーダ、１７……検出回路、１８……
消去ヘツド、１９……記録ヘツド、２０……再生
ヘツド、２１……テープ、２２，２３……増幅器
、２４……フイルタ回路、２５……遅延回路、２
６……積分回路、２７……比較器、２８……積分
回路、２９……表示回路、３０……ノツト回路、
３１……加算器、３２……表示回路。
FIG. 1 is a block diagram showing an embodiment of an error detection circuit of a data recording system according to this invention, and FIGS. 2 and 3 are block diagrams showing main parts of the embodiment and the operation of the embodiment, respectively. FIG. 4 is a block diagram showing another embodiment of the invention, and FIGS. 5 and 6 are block diagrams showing a conventional data recording system and explaining its operation. This is a flowchart. 11...Arithmetic processing unit main body, 12...Connection line,
13...Cassette tape recorder, 14...Arithmetic processing unit main body, 15...Connection line, 16...Cassette tape recorder, 17...Detection circuit, 18...
Erasing head, 19...Recording head, 20...Reproducing head, 21...Tape, 22, 23...Amplifier, 24...Filter circuit, 25...Delay circuit, 2
6...Integrator circuit, 27...Comparator, 28...Integrator circuit, 29...Display circuit, 30...Not circuit,
31... Adder, 32... Display circuit.
Claims (1)
テープに記録してなるデータ記録システムにおい
て、記録ヘツド及び該記録ヘツドよりもテープ走
行下流側に位置する再生ヘツドを有し前記記録ヘ
ツドを介して前記デジタルデータを前記テープに
記録している状態で該記録されたデジタルデータ
を前記再生ヘツドで読み出し可能なテープレコー
ダと、このテープレコーダの記録状態で再生され
た前記デジタルデータに基づいて前記演算処理装
置から出力されたデジタルデータの前記テープへ
の書き込みエラーを検出する検出回路とを具備し
てなることを特徴とするデータ記録システムのエ
ラー検出回路。 A data recording system in which digital data output from an arithmetic processing unit is recorded on a tape includes a recording head and a reproduction head located downstream of the recording head in tape travel, and the digital data is recorded via the recording head. a tape recorder capable of reading the recorded digital data with the playback head while recording the data on the tape; and an output from the arithmetic processing unit based on the digital data played back in the recording state of the tape recorder. 1. An error detection circuit for a data recording system, comprising: a detection circuit for detecting an error in writing digital data onto the tape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14481584U JPS6161671U (en) | 1984-09-25 | 1984-09-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14481584U JPS6161671U (en) | 1984-09-25 | 1984-09-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6161671U true JPS6161671U (en) | 1986-04-25 |
Family
ID=30703079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14481584U Pending JPS6161671U (en) | 1984-09-25 | 1984-09-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6161671U (en) |
-
1984
- 1984-09-25 JP JP14481584U patent/JPS6161671U/ja active Pending
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