JPS6159769A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6159769A JPS6159769A JP59181080A JP18108084A JPS6159769A JP S6159769 A JPS6159769 A JP S6159769A JP 59181080 A JP59181080 A JP 59181080A JP 18108084 A JP18108084 A JP 18108084A JP S6159769 A JPS6159769 A JP S6159769A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- manufacturing
- ion
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に係り、特に相補型MO
3集積回路(0MO3−I C>の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device.
3 integrated circuit (0MO3-IC>).
cMos−xcはpチャネルトランジスタとnチャネル
トランジスタを並設し、相補的に回路を構成することに
より、静的な消費電力を低減することができる。そのた
め大規模集積回路(LSI)には特に多用されている。cMos-xc can reduce static power consumption by arranging a p-channel transistor and an n-channel transistor in parallel and configuring a circuit in a complementary manner. Therefore, it is particularly frequently used in large-scale integrated circuits (LSI).
従来の0MO5−ICの製造においては、例えばn型珪
素(SL)基板を用いて、所定の領域にp型不純物を導
入し通常pウェルと呼ばれるp型頭域をつくり、ここに
nチャネルトランジスタを形成し、n型珪素基板上にp
チャネルトランジスタを形成する。In the conventional manufacturing of 0MO5-IC, for example, an n-type silicon (SL) substrate is used, p-type impurities are introduced into a predetermined region to create a p-type head region usually called a p-well, and an n-channel transistor is installed in this region. formed on an n-type silicon substrate.
Form a channel transistor.
このpウェルはnチャネルトランジスタのしきい値電圧
の制御上キャリア濃度をあまり大きくできないのでウェ
ル抵抗を上げないために、またnチャネルトランジスタ
のドレインの耐圧を保つためにウェルの深さを深くする
。従ってウェルは通常イオン注入等により深さ3〜5μ
mに形成する。Since the carrier concentration of this p-well cannot be increased too much in order to control the threshold voltage of the n-channel transistor, the depth of the well is made deep in order not to increase the well resistance and to maintain the breakdown voltage of the drain of the n-channel transistor. Therefore, the well is usually formed to a depth of 3 to 5 μm by ion implantation, etc.
Form into m.
このように深いウェルを形成すると、微細制御が難しく
、また集積度の向上も困難である。When such deep wells are formed, fine control is difficult and it is also difficult to improve the degree of integration.
高集積化のためウェルを浅くするとウェル抵抗が大きく
なり、寄生バイポーラトランジスタの影響によりウェル
が基板に対して導通状態になる、所謂ラッチアップが生
じ易くなる。When the well is made shallow for higher integration, the well resistance increases, and so-called latch-up, in which the well becomes conductive to the substrate due to the influence of a parasitic bipolar transistor, tends to occur.
これらを解決する手段としてエピタキシャル成長層の使
用が注目されている。The use of epitaxial growth layers is attracting attention as a means to solve these problems.
第2図(a)乃至(C)は従来例によるエピタキシャル
成長層を用いた0MO3−ICの製造方法を工程順に示
す断面図である。FIGS. 2(a) to 2(C) are cross-sectional views showing, in order of steps, a conventional method for manufacturing an OMO3-IC using an epitaxial growth layer.
この方法は本発明人により特願昭58−234581号
明細書に開示され、低温減圧エピタキシャル成長を用い
ることにより、高集積化の可能な、ラッチアップの生じ
ない0MO3−ICの開発を可能にしたものである。This method was disclosed in Japanese Patent Application No. 58-234581 by the present inventor, and by using low-temperature, reduced-pressure epitaxial growth, it was possible to develop an 0MO3-IC that can be highly integrated and does not cause latch-up. It is.
第2図(a)において、比抵抗10Ωcmのn型St基
板1の所定領域に選択的に硼素(B)をイオン注入し、
他の領域に選択的に砒素(As)または燐(P)をイオ
ン注入して表面から2000〜3000人の厚さにp+
型の不純物理没頭域2とn゛型の不純物理没頭域3を形
成する。In FIG. 2(a), boron (B) ions are selectively implanted into a predetermined region of an n-type St substrate 1 with a specific resistance of 10 Ωcm,
Arsenic (As) or phosphorus (P) is selectively implanted into other regions to a thickness of 2,000 to 3,000 p+ from the surface.
A type impure physics immersion area 2 and an n-type impure physics immersion area 3 are formed.
埋没領域の形成は、レジストをマスクにしてエネルギ5
0〜1OOkeV、 ドーズ量1013〜10110
l4”程度のイオン注入により行う。The buried region is formed using energy 5 using the resist as a mask.
0~1OOkeV, dose 1013~10110
This is done by ion implantation of approximately 14".
第2図(b)において、低温減圧エピタキシャル成長法
により厚さ1μmの半導体層4を成長する。In FIG. 2(b), a semiconductor layer 4 having a thickness of 1 μm is grown by low-temperature, reduced-pressure epitaxial growth.
エピタキシャル成長は、成長温度1000℃以下の低温
で、減圧度数Torr以下で、反応ガスとしてジクロル
シラン(SiHtCh)等を用いて分解成長させて行う
。The epitaxial growth is performed by decomposition growth using dichlorosilane (SiHtCh) or the like as a reaction gas at a low temperature of 1000° C. or less and a reduced pressure of Torr or less.
成長と同時にp°型の不純物理没頭域2の上にはp型頭
域4p 、n”型の不純物理没頭域3の上にはn型領域
4nが形成される。これは埋没領域2と3からのバック
拡散と、蒸発した不純物ガスによるオートドーピングと
によって埋没領域と同じ不純物型の領域が成長するもの
である。At the same time as the growth, a p-type head region 4p is formed on the p°-type impurity physical immersion region 2, and an n-type region 4n is formed on the n''-type impurity physical immersion region 3. A region of the same impurity type as the buried region grows by back diffusion from 3 and autodoping by the evaporated impurity gas.
それぞれの領域4pと4nは深さ1μm程度と浅いため
、面積を小さくして微細な領域を形成することができる
。Since each of the regions 4p and 4n has a shallow depth of about 1 μm, it is possible to reduce the area and form a fine region.
第2図(C)は公知の製法でp型M域4pとn型領域4
nとに、それぞれ微細なnチャネルトランジスタ5とp
チャネルトランジスタ6を形成することができる。FIG. 2(C) shows a p-type M region 4p and an n-type region 4 using a known manufacturing method.
microscopic n-channel transistors 5 and p, respectively.
A channel transistor 6 can be formed.
以上のようにして低温減圧エピタキシャル成長を用いて
微細なウェルを形成し、0MO5−ICの高集積化を可
能とする。As described above, fine wells are formed using low-temperature, reduced-pressure epitaxial growth, making it possible to achieve high integration of 0MO5-ICs.
しかしながら上記の従来例による0MO5−ICの製法
においては、n型基板にpウェルの形成が主体で、ウェ
ル形成に使用する不純物Bは拡散係数が大きいので濃度
制御が難しく、ウェルの厚さをlpm以下にすることは
できなかった。However, in the conventional manufacturing method of 0MO5-IC described above, the main process is to form a p-well on an n-type substrate, and since the impurity B used to form the well has a large diffusion coefficient, it is difficult to control the concentration, and the thickness of the well is limited to lpm. I couldn't do less.
C問題点を解決するための手!’J)
上記問題点の解決は、p型半導体基板にn型不純物理没
頭域を設け、該p型半導体基板上に半導体層をエピタキ
シャル成長し、前記n型不純物理没碩域上にn型半導体
層を形成する本発明による半導体装置の製造方法により
達成される。A way to solve problem C! 'J) The solution to the above problem is to provide an n-type impurity physically immersed region in a p-type semiconductor substrate, epitaxially grow a semiconductor layer on the p-type semiconductor substrate, and place an n-type semiconductor on the n-type impurity physically immersed region. This is achieved by the method of manufacturing a semiconductor device according to the present invention in which a layer is formed.
一般にn型不純物にはAsや、Pのように拡散係数の小
さいものがあるので、これを用いてn4型埋没領域をつ
くり、この上にエピタキシャルを成長させて0MO3−
ICを製造すれば、極めて薄いエビクキシャル層に素子
を形成することができる。In general, n-type impurities include those with small diffusion coefficients such as As and P, so these are used to create an n4-type buried region, and epitaxial growth is made on top of this.
When manufacturing ICs, devices can be formed in extremely thin eviaxial layers.
第1図(a)乃至(C1は本発明によるエピタキシャル
成長層を用いた0MO5−ICの製造方法を工程順に示
す断面図である。FIGS. 1(a) to (C1) are cross-sectional views showing, in order of steps, a method for manufacturing an OMO5-IC using an epitaxially grown layer according to the present invention.
第1図(a)において、B ドープのキャリア濃度10
”cm−’のp型Si基板11の所定領域にレジストを
マスクにして選択的にBイオンを100keV 、 ド
ーズ量10”co+−”で注入し、他の領域に選択的に
Asまたはアンチモン(Sb)イオンを180keV、
ドーズ量5×’ 10” 〜I XIO鳳’cm−
”’?!注入して表面から3000人程度0厚さにp゛
型の不純物理没頭域12とn°型の不純物埋没911M
13を形成する。In FIG. 1(a), the carrier concentration of B dope is 10
Using a resist as a mask, B ions are selectively implanted at a dose of 10"co+-" at 100keV into a predetermined region of the "cm-" p-type Si substrate 11, and As or antimony (Sb) is selectively implanted into other regions. ) ions at 180 keV,
Dose amount 5×' 10” ~I XIO Otori'cm-
``'?! Injecting p゛ type impurity physical immersion region 12 and n° type impurity buried 911M from the surface to a thickness of about 3000 mm
form 13.
この場合p9型埋没領域12は本質的には不要であるが
、基板に低抵抗のものを用いた関係で製造条件を整える
必要上形成するものである。In this case, the p9 type buried region 12 is essentially unnecessary, but it is formed because it is necessary to adjust the manufacturing conditions since a low resistance substrate is used.
第1図(blにおいて、低温減圧エピタキシャル成長法
により厚さ0.5〜1μmの半導体N14を成長する。In FIG. 1 (bl), a semiconductor N14 having a thickness of 0.5 to 1 μm is grown by a low-temperature reduced pressure epitaxial growth method.
エピタキシャル成長は、成長温度1000℃以下の低
温で、減圧度数Torr以下で、反応ガスとしてSiH
gC11等を用いて分解成長させて行う。Epitaxial growth is performed at a low growth temperature of 1000°C or less, at a reduced pressure of Torr or less, and using SiH as a reaction gas.
This is done by decomposition growth using gC11 or the like.
成長と同時にp°型の不純物理没頭域12の上にはp型
頭域14p、n”型の不純物理没頭域13の上にはn型
領域14nが形成される。これは埋没領域12と13か
らのバック拡散と、蒸発した不純物ガスによるオートド
ーピングとによって埋没領域と同じ不純物型の領域が成
長するものである。At the same time as the growth, a p-type head region 14p is formed on the p°-type impurity physical immersion region 12, and an n-type region 14n is formed on the n''-type impurity physical immersion region 13. A region of the same impurity type as the buried region grows by back diffusion from 13 and autodoping by the evaporated impurity gas.
それぞれの領域14pと14nは深さ0.5〜IIJm
と従来例より一層浅いため、さらに面積を小さくして微
細な領域を形成することができる。Each region 14p and 14n has a depth of 0.5 to IIJm
Since it is shallower than the conventional example, it is possible to further reduce the area and form a fine region.
つぎにしきい値調整のために、p型頭域14pにはBイ
オンを60keV 、 ドーズ量3 X 10” c+
a−”で注入し、n型領域14nにはPイオンを100
keV、ドーズ量3 X 10” cm−”で注入する
。Next, for threshold adjustment, B ions were applied to the p-type head region 14p at 60 keV, with a dose of 3 x 10” c+
a-", and 100 P ions were implanted into the n-type region 14n.
keV and a dose of 3 x 10"cm-".
第1図(C)において、公知の製法でp型頭域14pと
n型領域14nとに、それぞれ微細なnチャネルトラン
ジスタ15とpチャネルトランジスタ16を形成するこ
とができる。17はゲート酸化膜、18はゲートを示す
。In FIG. 1C, a fine n-channel transistor 15 and a fine p-channel transistor 16 can be formed in the p-type head region 14p and the n-type region 14n, respectively, by a known manufacturing method. 17 is a gate oxide film, and 18 is a gate.
以上のようにして低温減圧エピタキシャル成長を用いて
従来例より微細なウェルを形成し、0MO3−I Cの
高集積化を一層進めることができる。As described above, a finer well than the conventional example can be formed using low-temperature, reduced-pressure epitaxial growth, and higher integration of OMO3-IC can be further promoted.
以上詳細に説明したように本発明によれば、エピタキシ
ャル成長層を使用した0MO3−ICの製法において、
p型基板にnウェルの形成を主体としてウェルの厚さを
1μm以下にすることができるため、素子の微細化に有
効であり、エピタキシャル成長の生産性を向上する製造
方法を得ることができる。As explained in detail above, according to the present invention, in the method for manufacturing 0MO3-IC using an epitaxial growth layer,
Since the thickness of the well can be reduced to 1 μm or less by mainly forming an n-well on a p-type substrate, it is possible to obtain a manufacturing method that is effective for miniaturizing elements and improving productivity of epitaxial growth.
第1図(a)乃至(C)は本発明によるエピタキシャル
成長層を用いた0MO3−ICの製造方法を工程順に示
す断面図、
第2図(a)乃至(C)は従来例によるエピタキシャル
成長層を用いた0MO3−ICの製造方法を工程順に示
す断面図である。
図において、
11はp型Si基板、
12はp゛型型埋領領域13はn゛型型埋領領域14は
エピタキシャル成長半導体層、
14pはp型頭域、 14nはn型領域、15はn
チャネルトランジスタ、
16はpチャネルトランジスタ、
1.7はゲート酸化膜、 18はゲートを示す。
f−を唄 専2閉
山 (91
(b、 、 (b+(C1
(C)FIGS. 1(a) to (C) are cross-sectional views showing the manufacturing method of 0MO3-IC using an epitaxially grown layer according to the present invention in order of steps, and FIGS. 2(a) to (C) are sectional views using an epitaxially grown layer according to the conventional example. FIG. 3 is a cross-sectional view showing the manufacturing method of OMO3-IC in order of steps. In the figure, 11 is a p-type Si substrate, 12 is a p-type buried region 13, an n-type buried region 14 is an epitaxially grown semiconductor layer, 14p is a p-type head region, 14n is an n-type region, and 15 is an n-type semiconductor layer.
A channel transistor, 16 is a p-channel transistor, 1.7 is a gate oxide film, and 18 is a gate. Sing f- Sen2 closed mine (91 (b, , (b+(C1
(C)
Claims (1)
半導体基板上に半導体層をエピタキシャル成長し、前記
n型不純物埋没領域上にn型半導体層を形成することを
特徴とする半導体装置の製造方法。Manufacturing a semiconductor device, comprising providing an n-type impurity buried region in a p-type semiconductor substrate, epitaxially growing a semiconductor layer on the p-type semiconductor substrate, and forming an n-type semiconductor layer on the n-type impurity buried region. Method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59181080A JPS6159769A (en) | 1984-08-30 | 1984-08-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59181080A JPS6159769A (en) | 1984-08-30 | 1984-08-30 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6159769A true JPS6159769A (en) | 1986-03-27 |
Family
ID=16094457
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59181080A Pending JPS6159769A (en) | 1984-08-30 | 1984-08-30 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6159769A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5575265A (en) * | 1978-12-01 | 1980-06-06 | Fujitsu Ltd | Complementary type field-effect metal-insulator- semiconductor device |
JPS5593269A (en) * | 1979-01-09 | 1980-07-15 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPS5694670A (en) * | 1979-12-27 | 1981-07-31 | Fujitsu Ltd | Complementary type mis semiconductor device |
-
1984
- 1984-08-30 JP JP59181080A patent/JPS6159769A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5575265A (en) * | 1978-12-01 | 1980-06-06 | Fujitsu Ltd | Complementary type field-effect metal-insulator- semiconductor device |
JPS5593269A (en) * | 1979-01-09 | 1980-07-15 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
JPS5694670A (en) * | 1979-12-27 | 1981-07-31 | Fujitsu Ltd | Complementary type mis semiconductor device |
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