JPS6156456A - Solid-state image pickup device - Google Patents
Solid-state image pickup deviceInfo
- Publication number
- JPS6156456A JPS6156456A JP59179749A JP17974984A JPS6156456A JP S6156456 A JPS6156456 A JP S6156456A JP 59179749 A JP59179749 A JP 59179749A JP 17974984 A JP17974984 A JP 17974984A JP S6156456 A JPS6156456 A JP S6156456A
- Authority
- JP
- Japan
- Prior art keywords
- region
- gate
- drain
- source
- regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005036 potential barrier Methods 0.000 claims description 14
- 238000003384 imaging method Methods 0.000 claims description 5
- 239000002800 charge carrier Substances 0.000 claims 5
- 238000006243 chemical reaction Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 14
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000002955 isolation Methods 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 230000035945 sensitivity Effects 0.000 description 5
- 241000238557 Decapoda Species 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 230000001066 destructive effect Effects 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- ALEDXSBPMQVUIV-HZJYTTRNSA-N 3-[(8z,11z)-heptadeca-8,11-dienyl]benzene-1,2-diol Chemical compound CCCCC\C=C/C\C=C/CCCCCCCC1=CC=CC(O)=C1O ALEDXSBPMQVUIV-HZJYTTRNSA-N 0.000 description 1
- 241001212789 Dynamis Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14679—Junction field effect transistor [JFET] imagers; static induction transistor [SIT] imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/7722—Field effect transistors using static field induced regions, e.g. SIT, PBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/112—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor
- H01L31/1124—Devices with PN homojunction gate
- H01L31/1126—Devices with PN homojunction gate the device being a field-effect phototransistor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Ceramic Engineering (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明に感度増倍機能を有する固体撮像装置に関わる。[Detailed description of the invention] Industrial applications The present invention relates to a solid-state imaging device having a sensitivity multiplication function.
従来例の構成とその問題点
従来、感度増倍機能は光検出用のフォトダイオードをフ
ォトトランジスタとする事により実現しτいる。フォト
トランジスタに、バイポーラトランジスタ（ＢＰＴ）で
も、電界効果トランジスタ（ＦＥＴ）でも実現できるが
、性能的にＢＰＴ。Conventional structure and its problems Conventionally, the sensitivity multiplication function has been realized by using a phototransistor as a photodiode for light detection. The phototransistor can be implemented with a bipolar transistor (BPT) or a field effect transistor (FET), but BPT is preferable in terms of performance.
ＦＲＴを上回る静電誘導トランジスタ（ＳＩＴ）を用い
た固体撮像装置が提案されている。（特開昭５８−１０
５６７２号公報、特開昭５９−４５７１Ｂ１号公報を参
照） ＳＩＴをフォトトランジスタに利用すると、本
来の高いｇｍ （相互コンダクタンス）により、大きな
感度増倍機能が実現する。しかし、三極管で見られるよ
うな非飽和型の電圧・電流特性を示すため、電荷蓄積型
で用いる場合にＨＤＤＣ（ダイナミ、フク・ドレイン・
コンダクタンス）効果と呼ばれる好ましくない帰還効果
が生じ、ゲートの電位障壁が変調を受け、入射光の強度
により増倍率が変化するという問題が生じる。A solid-state imaging device using a static induction transistor (SIT), which is superior to FRT, has been proposed. (Unexamined Japanese Patent Publication No. 58-10
(See Japanese Patent Laid-Open No. 5672 and Japanese Patent Application Laid-Open No. 59-4571B1) When SIT is used in a phototransistor, a large sensitivity multiplication function can be realized due to its inherently high gm (mutual conductance). However, because it exhibits unsaturated voltage and current characteristics like those seen in a triode, HDDC (dynamis, hook, drain,
An undesirable feedback effect called the conductance effect occurs, causing a problem in that the potential barrier of the gate is modulated and the multiplication factor changes depending on the intensity of the incident light.
発明の目的
本発明に上記従来の問題点を解消し、入射光量に依存し
ない安定な増倍効果による高感度特性を有する固体撮像
装置の提供を目的とする。OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional problems and to provide a solid-state imaging device having high sensitivity characteristics due to a stable multiplication effect that does not depend on the amount of incident light.
発明の構成
本発明者により、ＳＩＴの大きなｇｍを維持したＩｉま
、理想的な飽和特性（従ってＤＤＣ効果に生じない。）
を実現する新しい５ＩＴ（これを旦ｈｉｅｌｄａｄユｄ
ｅａｌ ＪａｔｕｒｌＬｔ’＋５０ｐｅｒａｔｉｏｎ
−５ＩＴ、略して’５ＩＳＯ−３ＩＴ’と呼ぶ。）が提
案されている。（特許出願中）この’５ＩＳＯ−５ＩＴ
’のゲート領域を光によシ発生した正孔の蓄積領域とし
、この正孔の量に対応して電源（又１ＧＮＩ））Ｋ接続
されたソース領域から正孔のｍ倍の電子をドレイン領域
に集めるのが本発明の基本構成である。Structure of the Invention The present inventor has maintained a large gm of SIT, which has ideal saturation characteristics (therefore, no DDC effect occurs).
The new 5 IT that realizes
eal JaturLt'+50peration
-5IT, abbreviated as '5ISO-3IT'. ) has been proposed. (Patent pending) This '5ISO-5IT
The gate region of ' is used as an accumulation region for holes generated by light, and m times as many electrons as holes are transferred to the drain region from the source region connected to the power supply (also 1 GNI) corresponding to the amount of holes. The basic configuration of the present invention is to collect the following.
実施例の説明に入る前に’５ＩＳＯ−３工Ｔ’の説明を
行なう。第１図に横型に形成した接合ゲート型’５ＩＳ
Ｏ−３ＩＴ’の上面図（＆）、チャネル方向に沿ったλ
−λ′断面図（ｂ）、チャネル方向と直角な面に沿った
ｃ −ｃ’断面図（Ｃ）、チャネル方向と直角な面に沿
ったＤ −Ｄ’断面図（ｄ）及び’５ＩＳＯ−３工Ｔ’
の記号（６）を示す。Before going into the explanation of the embodiment, '5ISO-3 Engineering T' will be explained. Junction gate type '5IS formed horizontally in Figure 1
Top view of O-3IT'(&), λ along the channel direction
-λ' sectional view (b), c-c' sectional view (C) along the plane perpendicular to the channel direction, D-D' sectional view (d) along the plane perpendicular to the channel direction, and '5ISO- 3-engine T'
The symbol (6) is shown.
第１図において、Ｐ基板１０１（不純物密度Ｎ＝１０１
２〜１ ｏ” ｃｍ−Ｓ）上Ｋ、ｎ−ウェル１０２（Ｎ
＝１０１２〜１０”（’ｍ−３）が形成され、このｎ−
ウェル１０２内表面にソースのｎ＋領域１０３（Ｎ ＝
１０”〜１０２０ａｐｔ−’ ）、ドレインのｎ＋領
域１０４ （Ｎ＝１０”〜１０”ｆｆ１−３）、第１ゲ
ー ′ト（Ｇ１）（Ｄｐ＋領域１０５ （Ｎ＝１
０” 〜１０２０“−°）・第２ゲート（Ｇ２）（ＤＩ
）”領域°０６ ！（Ｎ＝１ｏ１７〜１０２
０ｃｌＲ−ｓ）、カ形ａすｆＥ、、７−ｙ。In FIG. 1, a P substrate 101 (impurity density N=101
2-1 o” cm-S) upper K, n-well 102 (N
= 1012~10''('m-3) is formed, and this n-
A source n+ region 103 (N =
10"~1020apt-'), drain n+ region 104 (N=10"~10"ff1-3), first gate (G1) (Dp+ region 105 (N=1
0" ~ 1020"-°)・Second gate (G2) (DI
)” area °06! (N=1o17~102
0clR-s), afE, 7-y.
電極１０７、ドレイン電極１０８、第１ゲート電極１０
９、第２ゲート電極１１ｏが絶縁膜１１１のコ／タクト
窓を通して、対応する領域とコンタクトされる。Electrode 107, drain electrode 108, first gate electrode 10
9. The second gate electrode 11o is contacted with the corresponding region through the contact/tact window of the insulating film 111.
第１図において、丸印１１２に第１ゲートのｐ＋領域１
０５によって形成される鞍部点状の電位障壁が存在する
領域で、′固有ゲート領域１１２′と以下呼称する。In FIG. 1, the p+ region 1 of the first gate is indicated by a circle 112.
05, where a saddle point-like potential barrier exists, which is hereinafter referred to as a 'specific gate region 112'.
また、第１ゲートの１対のｐ＋領域１０５５の間隔Ｗ。Also, the distance W between the pair of p+ regions 1055 of the first gate.
１を他のチャネル部よりも狭くする事により、固有ゲー
ト領域１１２内に第２図に示すような鞍部点状の電位障
壁２０１が実現され易くなシ、この電位障壁２０１の高
さによりソースのｎ＋領域１０３からドレイン側に注入
される電子の量が制御される。この時、ソースのｎ＋領
域１０３から固有ゲート領域１１２までの距離に十分小
さく設定することにより、ソースル固有ゲート領域間の
直列抵抗ＲＳげ極めて小さくなシ、相互コンダクタンス
ｇｍとの積に１以下となり、ＳＩＴ特有の大きなｇｍが
そのまま実現する。このままでに１固有ゲート領域１１
２の電位障壁２ｏ１に、第１ゲートのｐ＋領域１０５と
第２ゲートのｐ＋領域１０６の影響を受けるが、第２ゲ
ートのｐ＋領域１０６の電位を固定する事により、ソー
スのｎ＋領域１０３からドレインのｎ＋領域１０４に向
かう電子の注入量を入力信号に応じて実際に制御するの
に第１ゲートのｐ＋領域１０６の印加電圧となる。By making the potential barrier 1 narrower than the other channel portions, a saddle point-like potential barrier 201 as shown in FIG. The amount of electrons injected from n+ region 103 to the drain side is controlled. At this time, by setting the distance from the n+ region 103 of the source to the specific gate region 112 sufficiently small, the series resistance RS between the source specific gate regions becomes extremely small, and the product with the mutual conductance gm becomes 1 or less. The large GM characteristic of SIT is realized as is. As it is, 1 unique gate area 11
However, by fixing the potential of the p+ region 106 of the second gate, the potential barrier 2o1 of the source is influenced by the p+ region 105 of the first gate and the p+ region 106 of the second gate. The voltage applied to the p+ region 106 of the first gate is used to actually control the amount of electrons injected toward the n+ region 104 in accordance with the input signal.
さらに、交流的に接地された第２ゲートの１対のｐ＋領
域１０６の面隔Ｗ。２を、第１ゲートのｐ＋領域１０５
〜第２ゲートのｐ＋領域１０６間の距離り。０に対して
ＬｉｃＧ＞ ＷＯ２・・・・・・（１）とすることによ
り、ドレインのｎ＋領域１０４の電圧の影響が固有ゲー
ト領域１１２の電位障壁２０１に及ぶのに完全に遮へい
される。このようにして、固有ゲート領域１１２の電位
障壁２０１に第１ゲートのｐ＋領域１０６に印加された
電圧の静電誘導効果で制御され、しかも第２ゲートのｐ
＋領域１０６の遮へい効果により、ドレイン電圧にａ依
存しない事から、非飽和型ＳＩＴの高いｇｍを維持しな
がら、飽和電流特性が得られる。Furthermore, the plane distance W between the pair of p+ regions 106 of the second gate that is AC grounded. 2, the p+ region 105 of the first gate
~Distance between p+ regions 106 of the second gate. By setting LicG>WO2 (1) for 0, the influence of the voltage of the drain n+ region 104 on the potential barrier 201 of the specific gate region 112 is completely blocked. In this way, the potential barrier 201 of the intrinsic gate region 112 is controlled by the electrostatic induction effect of the voltage applied to the p+ region 106 of the first gate, and the p
Due to the shielding effect of the + region 106, a does not depend on the drain voltage, so that saturation current characteristics can be obtained while maintaining the high gm of a non-saturated SIT.
以上が’５ＩＳＯ−８ＩＴ’の原理であり、これを受光
素子として使うのが本発明であり、以下実施例を図面を
用いて説明する。The above is the principle of '5ISO-8IT', and the present invention uses this as a light receiving element.Examples will be described below with reference to the drawings.
本実施例でに、第１ゲート、第２ゲートを構成するｐ＋
領領域逆方向電圧を印加して制御する場合を主に説明す
るが、チャネル部（ｎ−ウェル１０２に相当する。）が
拡散電位だけでピンチオフするようにし、ゲートに順方
向電圧を印加して動作するエンハンスメントモードも可
能でめる。In this embodiment, the p+
Although we will mainly explain the case where control is performed by applying a reverse voltage to the region, the channel portion (corresponding to the n-well 102) is pinched off only by the diffusion potential, and a forward voltage is applied to the gate. An enhancement mode of operation is also available.
実施例の説明
第３図に、縦型に形成し北本発明の一実施例における’
５ＩＳＯ−３ＩＴ’型フォトトランジスタの一画素分の
上面図（＆）、水平方向ａ −ａ’断」残水平方向ｂ−
ｂ’断面（Ｑ）、垂直方向ａ −ｃ’断面（ｄ）、垂直
方向ｄ−ｄ’断面（＋５）を示す。DESCRIPTION OF THE EMBODIMENT FIG.
Top view of one pixel of 5ISO-3IT' type phototransistor (&), cross section in horizontal direction a-a', remaining in horizontal direction b-
b' section (Q), vertical direction a-c' section (d), and vertical direction dd' section (+5) are shown.
第３図において、ドレインのｎ＋基板３０１（不純物密
度Ｎ＝１０〜１０ ｏｎ ）上にｎ−エビ３０２（Ｎ
＝１ｏ１２〜１ｏ”ａｎ−’）７）＝形成され、第２ゲ
ートのｐ＋領域３０３（Ｎ＝１０１７〜１ｏ２０ｃｍ−
’ ）を形成後、再びｎ−ｚピ３０４（Ｎ＝ １０１２
〜１０” ａｎ−’ ）を形成し、コノｎ−エヒ３０４
表面に、ソースのｎ＋領域３０ｓ（Ｎ＝１ｏ” 〜２０
２０ｃｒｐｔ−Ｓ）、第１ ケー トノｐ” 領域３０
６（Ｎ＝１０ 〜１０ ｆｆ ）、画素分離用のｐ
＋領域３０７ （Ｎ＝１ｏ１７〜１ｏ２０ｏｎ−３）が
形成され、ソース電極３０８、第１ゲート電極３０９ｒ
ｓ絶縁膜３１０のコンタクト窓を通して対応する領域と
コンタクトする。In FIG. 3, an n- shrimp 302 (N
=1o12~1o"an-')7)=formed, the p+ region 303 of the second gate (N=1017~1o20cm-
) After forming nz pi 304 (N= 1012
~10” an-’), forming a 304
On the surface, there is a source n+ region 30s (N=1o" ~ 20
20crpt-S), 1st Ketonop” area 30
6 (N=10 to 10 ff), p for pixel separation
+ region 307 (N=1o17 to 1o20on-3) is formed, and the source electrode 308 and the first gate electrode 309r
Contact is made with the corresponding region through the contact window of the s insulating film 310.
第２ゲートのｐ＋領域３０３及びドレインのｎ＋領域３
０１［周辺部で対応する第２ゲート電極及びドレイン電
極とコンタクトされる。第３図において、丸印３１１σ
第１ゲートのｐ＋領域３０６によって形成される鞍部点
状の電位障壁が存在する領域で、′固有ゲート領域３１
１′と以下呼称する、この時、ソースル固有ゲート領域
間の距離を小さくしているため、この間の直列抵抗Ｒ８
に極めて小さくなり、相互フンダクタンスｇｍとの
・（積に１以下となり、非飽和型ＳＩＴの大き
なｇｍがそのまま実現する。Second gate p+ region 303 and drain n+ region 3
01 [Contacted with the corresponding second gate electrode and drain electrode at the periphery. In Figure 3, circle mark 311σ
A region where a saddle point-like potential barrier formed by the p+ region 306 of the first gate exists;
At this time, since the distance between the source cell specific gate regions, hereinafter referred to as 1', is reduced, the series resistance R8 between them is reduced.
becomes extremely small, and the mutual fundductance gm becomes extremely small.
・(The product is less than 1, and the large gm of the non-saturated SIT can be realized as is.
さらに、第２ゲートの１対のｐ＋領域３０３の間隔Ｗ。Furthermore, the distance W between the pair of p+ regions 303 of the second gate.
２と、第１ゲートのｐ＋領域３０６〜第２ゲートのｐ＋
領域３０３間の距離ＬＧＧ との間に、（１）式同様
ｅａａ ＞ ”Ｇ２ −１”（２）
が成立するよう寸法が決められる。しかも、第２ゲート
のｐ＋領域３０３［交流的に接地し、直流電圧が印加さ
れている。2 and the p+ region 306 of the first gate to the p+ region of the second gate
Between the distance LGG between the regions 303, eaa >"G2-1" (2) as in equation (1)
The dimensions are determined so that the following holds true. Furthermore, the p+ region 303 of the second gate is grounded in an AC manner, and a DC voltage is applied thereto.
以下、このように構成された本実施例の’５ＩＳｏ−Ｓ
ＩＴ’型フォトトランジスタ部の動作を説明する。本実
施例の読出し方法ａ′電子空乏動作′で行なう。Hereinafter, the '5ISo-S of this embodiment configured in this way will be explained.
The operation of the IT' type phototransistor section will be explained. The reading method of this embodiment is performed by a'electron depletion operation'.
第３図に示すように、第１ゲートのｐ＋領域３０６がソ
ースのｎ＋領域３０５を取囲む事によって、ソースのｎ
＋領域３０５の近傍の固有ゲート領域３１１のチャネル
電位が他のチャネル部分より低くなって、ソースのｎ＋
領域３０５からドレインのｎ＋領域３０１に向かって流
れる電子にとって第４図に示すような電位障壁４０１が
形成される。第３図のＫ −Ｋ’紗に沿ったエネルギー
バンド図と、Ｌ−Ｌ’線に沿ったエネルギーバンド図と
が第４図に示されている。As shown in FIG. 3, the p+ region 306 of the first gate surrounds the n+ region 305 of the source.
The channel potential of the specific gate region 311 near the + region 305 is lower than that of other channel parts, and the source n+
A potential barrier 401 as shown in FIG. 4 is formed for electrons flowing from the region 305 toward the n+ region 301 of the drain. FIG. 4 shows an energy band diagram along the line K-K' of FIG. 3 and an energy band diagram along the line LL'.
光に表面から侵入し、発生した電子・正孔対のうち電子
にポテンシャルレベルの深いドレインのｎ＋領域３０１
へ流れτいくが、正孔にフローティング状態になってい
るゲートのｐ＋領域３０６に大部分が蓄、積される。（
一部に画素分離用のｐ＋領域３０７に吸収される可能性
があるが、これを防ぐにσ、正のバイアス電圧を印加し
ておけばよいＱ ）
’５ＩＳＯ−３ＩＴ’型フォトトランジスタに第１ゲー
トのｐ＋領域３０６の拡散電位だけで高抵抗のチャネル
領域（これｎｎ″″エビ領域３０４の承で、一般に１領
域とも呼ぶ。）がほぼ空乏化し、正孔を蓄積する第１ゲ
ートのｐ＋領域３０６の周囲ａ空乏化された高抵抗領域
（ｉ領域）をはさんだ＃ ｐ ＋ ｉｎ ＋ ＃フォ
トダイオードとなっており、対生成した正孔に効率よく
第１ゲートのｐ＋領域３０６に流入する。Among the electron-hole pairs generated by light entering from the surface, the n+ region 301 of the drain has a deep potential level for electrons.
Most of the electrons are accumulated in the p+ region 306 of the gate, which is in a floating state due to holes. (
There is a possibility that some of it is absorbed by the p+ region 307 for pixel isolation, but to prevent this, it is sufficient to apply a positive bias voltage σ. The diffusion potential of the p+ region 306 of the gate alone causes the high-resistance channel region (this is the successor to the nn''" shrimp region 304, and is also generally called 1 region) to be almost depleted, and the p+ region of the first gate accumulates holes. It is a #p + in + # photodiode sandwiching a depleted high resistance region (i region) around the periphery of the photodiode 306, and the generated holes efficiently flow into the p+ region 306 of the first gate.
第４図に第３図の’５ＸＳＯ−３ＩＴ’型フォトトラン
ジスタの動作をポテンシャル分布で示したもので、第４
図（２Ｌ）に、第３図（ｂ）のＫ −Ｋ’線、Ｌ−Ｌ’
線に沿ったポテンシャル分布の様子を暗（Ｄａｒｋ）状
態を実線で示し、光検出の結果、第１ゲートのｐ＋領域
３０６にある程度正孔が蓄積されて、第１ゲートのｐ＋
領域３０６の電位が正に帯電した状態を破線で示し、読
出し状態を一点鎖線で示している。これらに対応する第
３図（ｂ）のＭ−Ｍ’線に沿ったポテンシャル分布が第
４図（ｂ）に示てれている。Figure 4 shows the operation of the '5XSO-3IT' type phototransistor in Figure 3 using potential distribution.
Figure (2L) shows the K-K' line and L-L' line of Figure 3(b).
The dark state of the potential distribution along the line is shown by a solid line, and as a result of photodetection, a certain amount of holes are accumulated in the p+ region 306 of the first gate, and the p+ region of the first gate is
A state where the potential of the region 306 is positively charged is shown by a broken line, and a read state is shown by a dashed line. The potential distribution along line MM' in FIG. 3(b) corresponding to these is shown in FIG. 4(b).
読出し時にに、パルスが第１ゲート電極３０９から第１
ゲートのｐ＋領域３０６に印加される。During readout, a pulse is applied from the first gate electrode 309 to the first gate electrode 309.
Applied to the p+ region 306 of the gate.
第１ゲートのｐ 領域３０６に印加されるパルス電圧が
不妊ければ高いゲート電位に蓄積された正孔に逃げにく
く、非破壊読出し動作となる。第１ゲートのｐ 領域３
０６に印加するパルス電圧が大きければ、第１ゲートの
ｐ＋領域３０６に蓄積でれた正孔にソースのｎ＋領域３
０１（又に画素分離用のｐ＋領域３０７）に掃出されて
、暗（Ｄａｒｋ）状態の実線で示したポテンシャル分布
に復帰する事になり、通常の破壊読出し動作となる。If the pulse voltage applied to the p-region 306 of the first gate is inefficient, holes accumulated at a high gate potential will have difficulty escaping, resulting in a non-destructive readout operation. P region 3 of first gate
If the pulse voltage applied to 06 is large, the holes accumulated in the p+ region 306 of the first gate will be absorbed by the n+ region 306 of the source.
01 (and the p+ region 307 for pixel isolation) and returns to the potential distribution shown by the solid line in the dark state, resulting in a normal destructive readout operation.
第１ゲートのｐ＋領域３０６に蓄積された光情報として
の正孔が印加パルスによってソースのｎ＋領域３０５に
移動する時、本来高いゲートポテンシャルレベルにある
ゲートのｐ＋領域３０６内に蓄積された正孔にとってに
、リースのｎ＋領域３０５に流入する為に拡散電位とい
う非常に高いポテンシャル障壁を越えなければならず、
一方ソースノｎ＋領域３０６の電子にとっては固有ゲー
ト領域３１１の低い電位障壁を越えればチャネルに注入
される訳で、この差に対応するように正孔のｍ倍の電子
注入が行なわれ大きな光増倍効果が実現する。この時、
ソースのｎ＋領域３０５がフローティング状態であれば
、′電子空乏′という状態で信号情報が保存される。こ
の時、従来の’Ｓ Ｉ Ｔ’であれば、ドレインのｎ＋
領域３０１の電圧の変動が固有ゲート領域３１１の電位
障壁Ｋ１１ｉ″ｆｈｆｃＦ＞・−”ＡＩ！ＥＫＧ ［７
？ｊＭ＋７ｔ［ｌ！ ｈ’ｖ４ 。When the holes as optical information accumulated in the p+ region 306 of the first gate move to the n+ region 305 of the source by the applied pulse, the holes accumulated in the p+ region 306 of the gate, which is originally at a high gate potential level, move to the n+ region 305 of the source. In order to flow into the n+ region 305 of the lease, it is necessary to overcome a very high potential barrier called the diffusion potential.
On the other hand, for electrons in the source n+ region 306, if they cross the low potential barrier of the intrinsic gate region 311, they are injected into the channel, and to correspond to this difference, m times as many electrons as holes are injected, resulting in a large photomultiplier. The effect is realized. At this time,
If the source n+ region 305 is in a floating state, signal information is stored in an ``electron depletion'' state. At this time, in the conventional 'S I T', the drain n+
The fluctuation of the voltage in the region 301 causes the potential barrier K11i″fhfcF>・−”AI! of the intrinsic gate region 311. EKG [7
? jM+7t[l! h'v4.
ン電圧の変動が光増倍率を変化させてしまう。ところが
本発明の＃５ＩＳＯ−３ＩＴ’に、第２ゲートのｐ＋領
域３０３の遮へい効果により、このような好ましくない
帰還作用に生じないので光の強度に依存しない増倍効果
が実現できる。Fluctuations in the voltage will change the light multiplication factor. However, in the #5ISO-3IT' of the present invention, due to the shielding effect of the p+ region 303 of the second gate, such undesirable feedback effects do not occur, so that a multiplication effect that does not depend on the intensity of light can be realized.
以上のような電子空乏動作をする’５ＸＳＯ−３ＩＴ’
型フォトトランジスタを二次元配列した回路構成を第６
図に示す。垂直走査回路５０１に’５ＩＳＯ−３ＩＴ’
型フォトトランジスタの第１ゲートのｐ＋領域３０６に
読出しパルスを印加し、光発して蓄積している正孔のｍ
倍の電子がソースからドレインに注入され電源Ｆ１に排
出される。この結果、ソースのｎ＋領域３０５及びこれ
に接続した垂直信号伝送＠５Ｑ２が電子空乏状態となる
。（第２ゲートのｐ＋領域３０３に電源ｚ２に接続され
る。）その後、水平走査回路５０３によって水平ＭＯＳ
スイッチが順次開閉することで、電源Ｅ３から電子が負
荷抵抗Ｒｃを流れて垂直信号伝送線５０２に注入する時
、信号電圧を発生するＯ
受光部のレイアウトに、第６図に示すように第３図のユ
ニットを二次元に配列したものである。'5XSO-3IT' which performs electron depletion operation as described above
The circuit configuration with a two-dimensional array of type phototransistors is shown in the sixth example.
As shown in the figure. '5ISO-3IT' in vertical scanning circuit 501
A read pulse is applied to the p+ region 306 of the first gate of the type phototransistor, and m of the holes emitted and accumulated is
Double the number of electrons is injected from the source to the drain and discharged to the power source F1. As a result, the n+ region 305 of the source and the vertical signal transmission @5Q2 connected thereto are in an electron-depleted state. (The p+ region 303 of the second gate is connected to the power supply z2.) After that, the horizontal scanning circuit 503 connects the horizontal MOS
By sequentially opening and closing the switches, when electrons from the power source E3 flow through the load resistor Rc and are injected into the vertical signal transmission line 502, a signal voltage is generated. This is a two-dimensional arrangement of the units shown in the figure.
以上のように、本実施例によれば、理想的な飽和電流特
性をもつ′Ｓ工５ｏ−８工Ｔ′型フォトトランジスタを
受光素子とする事により、入射光の強度に依らず安定な
増倍効果が実現できる。As described above, according to this embodiment, by using the 'S5O-8T' type phototransistor with ideal saturation current characteristics as the light receiving element, stable increase is achieved regardless of the intensity of the incident light. A double effect can be achieved.
以上に、電子空乏動作であるが、構造を一部変更すれば
、電子蓄積動作も可能でるる。この時の画素部分の構造
に第７図に上面図（ａ）、水平方向ａ＆／断面図（ｂ）
、水平方向ｂ −ｂ’断面図（Ｃ）、垂直方向Ｃ−Ｑ’
断面図（（１）、垂直方向ｄ −ｄ’断面図（ｄ）を示
す。The above is an electron depletion operation, but if the structure is partially changed, an electron accumulation operation is also possible. The structure of the pixel part at this time is shown in Figure 7, with a top view (a) and a horizontal cross-sectional view (a).
, horizontal direction b-b' sectional view (C), vertical direction C-Q'
Cross-sectional view ((1), vertical direction d-d' cross-sectional view (d) is shown.
第７図に示すように第３図のｎ 基板３０１のかわりに
ｐ基板７ｏ１（Ｎ＝１０１２〜１ｏ１７備−５）を用い
、ｐ基板７０１表面にドレインとなるｎ＋領域７０２を
垂直信号伝送線となるように形成する。この後、ｎ″″
エピ３０２を形成してから以降に第３図と全く同一で
ある。As shown in FIG. 7, a p-substrate 7o1 (N=1012 to 1o17-5) is used instead of the n-substrate 301 in FIG. Form it so that it becomes. After this, n″″
The process after forming the epitaxial layer 302 is exactly the same as that shown in FIG.
読出し動作も全く同様で、第３図と異なる点にドレイン
のｎ＋領域７０２に光生成した正孔のｍ倍の電子（これ
にソースのｎ＋領域３０６からチャネルへ注入される。The read operation is exactly the same, except that the difference from FIG. 3 is that electrons (m times as many electrons as holes photogenerated in the n+ region 702 of the drain) are injected into the channel from the n+ region 306 of the source.
）が信号電荷として蓄積するという事とこ′ｒＬに対応
して、第３図の信号伝送線として用いたソース電極３０
８に、電源供給のための配線にかわる。) is accumulated as a signal charge.
8, the wiring for power supply is replaced.
このように、電子蓄積動作をする’５ＩＳＯ−３Ｉ Ｔ
’型フォトトランジスタを二次元配列した回路構成を第
８図に示す。上述したように、第３図の垂直信号伝送線
５０２にソースに接続されていたが、第８図でに、ドレ
インに接続された垂直信号伝送線８０２を用い、ソース
に電源（ここでにＧＮＤ）に接続されている。In this way, the '5ISO-3I T
FIG. 8 shows a circuit configuration in which ' type phototransistors are two-dimensionally arranged. As mentioned above, the source was connected to the vertical signal transmission line 502 in FIG. 3, but in FIG. )It is connected to the.
この場合も、光強度に依存しない安定な増倍効果が可能
な上、水平走査回路をＣＯＤとした構成にも応用できる
特徴を有する。In this case as well, it is possible to achieve a stable multiplication effect that does not depend on the light intensity, and it also has the feature that it can be applied to a configuration in which the horizontal scanning circuit is a COD.
なお、上記実施例の各領域の極性を全て反転しても構わ
ないし、画素分離領域としては絶縁膜で構成しても構わ
ない。Note that the polarities of all the regions in the above embodiments may be reversed, and the pixel isolation region may be formed of an insulating film.
発明の効果
１ 本発明に、理想的な電流飽和特性を有
するフォトトランジスタを用いる事により、入射光量に
依存しない光増倍が可能となり、優れた高感度特性の撮
像素子を実現できるものである。Effect of the Invention 1 By using a phototransistor having ideal current saturation characteristics in the present invention, light multiplication that does not depend on the amount of incident light becomes possible, and an imaging device with excellent high sensitivity characteristics can be realized.
チャネル方向に沿った人−に断面図〆、チャネルと直角
な方向に沿ったｃ−ｃ’断面図ダ、チャ坏ルと直角な方
向に沿ったＤ−了断面図〆、等価記号目
〆、第２図Ｂ’５ＩＳＯ−３ＩＴ’（７）動作時のポテ
ンシャル分布図、第３図ａ Ｎａに電子空乏動作の’５
ＩＳＯ−８ＩＴ’型フォトトランジスタの上面図、水平
方向２Ｌ −＆’断面図、水平方向のｂ −ｂ筒面図、
垂直方向ａ −ｃ’断面図、垂直方向ｄ −ｄ′断面図
、第４図に’５ＩＳＯ−３ＩＴ’型フォトトランジスタ
のチャネル方向に沿っｔポテンシャル分布図〆、チャネ
ルと直角な方向に沿ったボテンシャル分布図ν、第５図
に電子空乏動作の’５ＩＳＯ−８ＩＴ’型フォトトラン
ジスタを用いた撮像素子構成図、第６図ａ−６に第５図
の各受光部のレイアウト図、第７図ａ”’−’ｅｒｒ電
子蓄積 １動作の’Ｓ Ｉ Ｓ Ｏ−３Ｉ
Ｔ’型フォトトランジスタの上面図〆、水平方向ａ−ａ
／断面図２．水平方向ｂ−ｂ’断面図４、垂直方向０−
Ｑ’断面図！、垂３０１・・・・・・ｎ＋基板（ドレ
イン）、３０２゜３０４・・・・・・ｎ−エビ、３０３
・・・・・・第２ゲート、３０５・・・・・・ソース、
３ｏ６・・・・・・ｌＥｌ ケ−）、３１１・・・・・
・固有ゲート。Cross-sectional view along the direction of the channel〆〆, CC' cross-sectional view along the direction perpendicular to the channel〆, D-cross-sectional view along the direction perpendicular to the channel〆〆, equivalent symbol 〆〆, Figure 2 B'5ISO-3IT' (7) Potential distribution diagram during operation, Figure 3a '5 of electron depletion operation in Na
A top view of an ISO-8IT' type phototransistor, a horizontal 2L-&' cross-sectional view, a horizontal b-b cylindrical view,
Vertical direction a-c' cross-sectional view, vertical direction d-d' cross-sectional view, t-potential distribution diagram along the channel direction of the '5ISO-3IT' type phototransistor, and the potential distribution along the direction perpendicular to the channel. Distribution diagram ν, Figure 5 is a configuration diagram of an image sensor using a '5ISO-8IT' type phototransistor with electron depletion operation, Figure 6 a-6 is a layout diagram of each light receiving section in Figure 5, and Figure 7 a. ”'-'errElectron accumulation 1 operation'S I S O-3I
Top view of T' type phototransistor, horizontal direction a-a
/Cross-sectional view 2. Horizontal direction bb' sectional view 4, vertical direction 0-
Q' cross section! , vertical 301...n+ substrate (drain), 302°304...n- shrimp, 303
...Second gate, 305...Source,
3o6...lEl ke-), 311...
・Unique gate.
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第２
図
第３図
第４図
（α）（ｂ）
第５図
Ｅ（、工↓
第８図Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 Figure 4 (α) (b) Figure 5 E (, ↓ Figure 8
Claims (1)
領域間に第１の電荷担体の通路となるチャネルを形成す
るための高抵抗半導体領域を備え、前記高抵抗半導体領
域内のソース領域近傍に、光生成した第２の電荷担体を
蓄積する第１のゲート領域を形成し、前記チャネルの前
記ソース領域近傍の電位に不均一な部分を設けて、主動
作領域において第１の電荷担体に対する電位障壁となし
、しかもソース領域から前記電位障壁までの直列抵抗Ｒ
＿Ｓが変換コンダクタンスＧｍに対しＲ＿Ｓ・Ｇｍ＜１
となし、かつ、前記第１のゲート領域近傍に第２のゲー
ト領域を形成し、前記第２のゲート領域で決まるチャネ
ル幅ｒ＿Ｇ＿２と第１ゲート領域〜第２ゲート領域間の
距離ｌ＿Ｇ＿Ｇとの間で、ｌ＿Ｇ＿Ｇ＞ｒ＿Ｇ＿２が成
立つように諸寸法を選定し、第２の電荷担体のｍ倍に相
当する第１の電荷担体が前記ソース領域から前記ドレイ
ン領域に注入されるようなフォトトランジスタを受光素
子とする事を特徴とする固体撮像装置。A source region, a drain region, and a high resistance semiconductor region for forming a channel serving as a passage for a first charge carrier between the source region and the drain region; forming a first gate region for accumulating second charge carriers, and providing a non-uniform portion of potential in the vicinity of the source region of the channel to act as a potential barrier to the first charge carriers in the main operating region; , and the series resistance R from the source region to the potential barrier
_S is R_S・Gm<1 for conversion conductance Gm
and a second gate region is formed near the first gate region, and between a channel width r_G_2 determined by the second gate region and a distance l_G_G between the first gate region and the second gate region. Then, various dimensions are selected so that l_G_G>r_G_2 holds, and a phototransistor is used to receive light such that first charge carriers equivalent to m times the number of second charge carriers are injected from the source region to the drain region. A solid-state imaging device characterized by an element.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59179749A JPS6156456A (en) | 1984-08-28 | 1984-08-28 | Solid-state image pickup device |
| US06/725,353 US4639753A (en) | 1984-04-19 | 1985-04-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59179749A JPS6156456A (en) | 1984-08-28 | 1984-08-28 | Solid-state image pickup device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6156456A true JPS6156456A (en) | 1986-03-22 |
Family
ID=16071199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59179749A Pending JPS6156456A (en) | 1984-04-19 | 1984-08-28 | Solid-state image pickup device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6156456A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5162887A (en) * | 1988-10-31 | 1992-11-10 | Texas Instruments Incorporated | Buried junction photodiode |
-
1984
- 1984-08-28 JP JP59179749A patent/JPS6156456A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5162887A (en) * | 1988-10-31 | 1992-11-10 | Texas Instruments Incorporated | Buried junction photodiode |
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