JPS6148992A - Method of producing hybrid integrated circuit - Google Patents
Method of producing hybrid integrated circuitInfo
- Publication number
- JPS6148992A JPS6148992A JP17089584A JP17089584A JPS6148992A JP S6148992 A JPS6148992 A JP S6148992A JP 17089584 A JP17089584 A JP 17089584A JP 17089584 A JP17089584 A JP 17089584A JP S6148992 A JPS6148992 A JP S6148992A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring pattern
- silver
- wiring
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（技術分野）
本発明は絶縁基板上に抵抗、コンデンサなどの受動素子
を膜技術に、より形成し、更にＩＣなどの能動素子を上
記基板に取付は各素子間を導体配線で相互接続を行なっ
て形成される混成集積回路の製造方法に関する。[Detailed Description of the Invention] (Technical Field) The present invention forms passive elements such as resistors and capacitors on an insulating substrate using film technology, and furthermore, attaches active elements such as ICs to the above substrate by connecting between each element. The present invention relates to a method of manufacturing a hybrid integrated circuit formed by interconnecting conductor wiring.
（従来技術）
混成集積回路に於いて、絶＆基板上の各素子間の接続導
体及び、部品接続導体となる導体配線は従来導電性とポ
ンディング性を兼ねそなえ、たアルミニウム膜や金膜が
多く用いられる。しかしアル、ミニラム膜に於いては良
好な導電性の配線膜を得るため５μｍ程度以上の厚みに
アルミニウム膜を成膜する必要があり、多大の成膜時間
を費すと共にパターンエツチングに於いても気泡残りな
どのため配線パターン間の短絡不良を、生じやすかった
。(Prior art) In hybrid integrated circuits, the conductor wiring that serves as the connection conductor between each element on the board and the component connection conductor has conventionally had both conductivity and bonding property, and aluminum film or gold film has been used. Often used. However, in the case of aluminum and mini-lamb films, in order to obtain a wiring film with good conductivity, it is necessary to form an aluminum film to a thickness of approximately 5 μm or more, which requires a large amount of film formation time and requires a lot of time in pattern etching. Short circuits between wiring patterns were likely to occur due to air bubbles remaining.
また、圧着方式の外部接続パターンに於いては酸化や腐
食の問題があった。一方、金膜については圧着方式の外
部接続パターンに於いては腐食性に対しては良好である
が、金はグ論貴金属であり、金の成膜による膜構成はコ
スト高にならざるを得なかった。Furthermore, there are problems with oxidation and corrosion in the external connection pattern of the crimp type. On the other hand, as for gold film, although it is good against corrosion in the external connection pattern of the pressure bonding method, gold is a precious metal, and the film structure by forming a gold film has to be expensive. There wasn't.
（発明の目的）
本発明の目的は、ポンディング性導電性、耐食性を共に
満足できる導体配線を安価に製造する事を含む混成集積
回路の製造方法を提供するにある。(Objective of the Invention) An object of the present invention is to provide a method for manufacturing a hybrid integrated circuit, which involves manufacturing at a low cost a conductor wiring that satisfies both bonding conductivity and corrosion resistance.
（発明の構成）
本発明の混成集積回路の製造方法はポンディング性を有
したアルミニウム膜と導体抵抗損失を低減ならしめるた
めにポンディングされる部分を除いたアルミニウム膜と
端子接続端子部のアルミニウム膜の上に銀ペーストをス
クリーン印刷し、焼成した後、前記アルミニウム膜と銀
膜の双方にオーバラップして、銅ペーストをスクリーン
印刷して焼成後、耐食性を必要とする端子部のみに金メ
ッキを施す事を特徴とする。(Structure of the Invention) The method for manufacturing a hybrid integrated circuit according to the present invention includes an aluminum film having a bonding property, an aluminum film excluding a portion to be bonded to reduce conductor resistance loss, and an aluminum film at a terminal connection terminal portion. After screen-printing a silver paste on the film and firing, screen-print a copper paste overlapping both the aluminum film and the silver film, and after firing, gold plating is applied only to the terminal parts that require corrosion resistance. It is characterized by giving.
（実施例） 以下図面を参照して本発明の実施例について説明する。(Example) Embodiments of the present invention will be described below with reference to the drawings.
第１図〜第６図は本発明を説明するための工程項の仕掛
品基板の断面図である。まず第１図の様にセラミックの
絶縁基板１の上に密着力強化のための下地膜としての五
酸化タンタル膜をスパッタリング法により２００ＯＡ層
に形成し、次いで前記五酸化メンタル膜の上に導体膜と
してのアルミニウム膜を６００ ＯＡ厚にスパッタリン
グ法により形成する。この様に金属膜が形成された絶縁
基板に対し、衆知のホトレジスト膜を用いて、リン酸系
のエツチング液でパターン形成し、第２図に示す配線パ
ターンの状態とする。次に前記のホトレジスト膜を剥離
した後、ポンディングされる部分を除いたアルミニウム
配線パターンでかつ、大電流が流れる配線パターンと圧
着用端子接続パターンに於いて、アサヒ化学研究所製銀
ペースト（商品名ＬＳ−５００）をスクリーン印刷し、
２００℃にて３０分間焼成して約８０μｍ厚の銀膜を得
た第３図の状態とする。次に上記銀膜配線パターンのう
ち、圧着接続端子パターンを除いたｆ！＆ｍ配線部分と
アルミニウム膜の双方にオーバーラツプしてアサと化学
研究所製鋼ペースト（商品名ＡＣＰ−０２０Ｊ）を前記
と同様の条件にてスクリーン印刷して８０μｍ厚みに焼
成し、第４図の状態とした。1 to 6 are cross-sectional views of work-in-progress substrates in process sections for explaining the present invention. First, as shown in FIG. 1, a tantalum pentoxide film is formed as a base film to strengthen adhesion on a ceramic insulating substrate 1 to a thickness of 200 OA by sputtering, and then a conductor film is formed on the pentoxide mental film. An aluminum film with a thickness of 600 OA is formed by sputtering. The insulating substrate on which the metal film has been formed in this way is patterned using a well-known photoresist film and a phosphoric acid-based etching solution to obtain the wiring pattern shown in FIG. Next, after peeling off the photoresist film, apply silver paste manufactured by Asahi Chemical Laboratory (commercial product LS-500) screen printed,
The silver film was baked at 200° C. for 30 minutes to obtain a silver film with a thickness of about 80 μm, as shown in FIG. Next, f! of the above silver film wiring patterns excluding the crimp connection terminal pattern! &m Overlapping both the wiring part and the aluminum film, Asato Kagaku Institute Steelmaking Paste (trade name ACP-020J) was screen printed under the same conditions as above and fired to a thickness of 80 μm, resulting in the state shown in Figure 4. did.
この時、銅ペーストは鋼の酸化を防ぐために還元作用を
有しており、同時にアルミニウム膜の酸化膜を還元して
銀膜とアルミニウム膜の導通性を良好ならしめるための
媒体の役目を°果すも□のである。At this time, the copper paste has a reducing effect to prevent oxidation of the steel, and at the same time serves as a medium to reduce the oxide film on the aluminum film and improve the conductivity between the silver film and the aluminum film. It is also □.
この後ポンディング部分と外部端子部分とを除いた部分
に従来のスクリーン印刷法により絶縁饗脂でオーバーニ
ーティングし、第５図に示す状態とする。読いて外部端
子パターンのａ藤のみの上に公知のメッキ技術を用いて
金メッキを約０．５μｍ厚に形成して第６図に示した構
造を得る。Thereafter, the parts excluding the bonding part and the external terminal part are overkneaded with an insulating resin by the conventional screen printing method, to obtain the state shown in FIG. 5. Gold plating is then formed to a thickness of about 0.5 .mu.m on only the external terminal pattern by using a known plating technique to obtain the structure shown in FIG.
（効果）
しかるべくして得られた導体配線パターンに於いては外
部端子との圧着接続に適した耐食性のちる部分と基板に
搭載されたＩＣチップとのワイヤポンディングに使用さ
れる部分と良導体配線ツクターンとの性質を兼ね備えた
導体配線ノ（ターン構成が、アルミニウムと銅および銀
と高価な金を最小限に使用するととくより安価に形成で
きる。(Effect) The conductor wiring pattern thus obtained has a corrosion-resistant part suitable for crimp connection with an external terminal, a part used for wire bonding with an IC chip mounted on the board, and a good conductor. A conductor wiring (turn configuration) that has the properties of a wiring turn can be formed at a lower cost, especially if aluminum, copper, silver, and expensive gold are used to a minimum.
第１図〜第６図は本発明の一実施例の製造工程を説明す
る断面図である。
１・・・・・・絶縁基板１．２・・・・・・五酸化タン
タル下地膜、３・・・・・・アルミニウム膜、４・・・
・・・銀印刷膜、５・・・・・・銅印刷膜、６・・・・
・・金メッキ腹、７・・・・・・保護樹脂、８・・・・
・・良導体を兼ね備えたポンディング可能な配線パター
ン、９・・・・・・圧着可能な外部接続配線）（ターン
。1 to 6 are cross-sectional views illustrating the manufacturing process of an embodiment of the present invention. 1...Insulating substrate 1.2...Tantalum pentoxide base film, 3...Aluminum film, 4...
...Silver printed film, 5...Copper printed film, 6...
...Gold plated belly, 7...Protective resin, 8...
...Pondable wiring pattern with good conductivity, 9...Crimpable external connection wiring) (turn.
Claims (1)
の下地膜を形成する工程と前記五酸化タンタル膜の上に
アルミニウム膜を形成する工程と前記アルミニウム膜を
エッチング等により所定の配線パターンに形成する工程
と次に前記配線パターンのうちポンディングされる部分
を除いた配線パターンに銀ペーストを印刷して焼成する
工程と前記銀膜配線パターンのうち圧着接続配線パター
ンを除いた銀膜配線部分とアルミニウム膜の双方にオー
バーラップして銅ペーストを印刷して焼成する工程と前
記銀膜配線部分に金メッキを施す工程とを有することを
特徴とする混成集積回路の製造方法。A step of forming a base film of tantalum pentoxide or the like to strengthen adhesion on an insulating substrate, a step of forming an aluminum film on the tantalum pentoxide film, and forming the aluminum film into a predetermined wiring pattern by etching or the like. Next, a step of printing and baking a silver paste on the wiring pattern excluding the bonded portion of the wiring pattern, and a step of printing and baking the silver film wiring pattern excluding the crimp connection wiring pattern of the silver film wiring pattern. 1. A method for manufacturing a hybrid integrated circuit, comprising the steps of: printing and firing a copper paste so as to overlap both the wiring portion and the aluminum film; and plating the silver film wiring portion with gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17089584A JPS6148992A (en) | 1984-08-16 | 1984-08-16 | Method of producing hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17089584A JPS6148992A (en) | 1984-08-16 | 1984-08-16 | Method of producing hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6148992A true JPS6148992A (en) | 1986-03-10 |
Family
ID=15913309
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17089584A Pending JPS6148992A (en) | 1984-08-16 | 1984-08-16 | Method of producing hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6148992A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0217271U (en) * | 1988-03-14 | 1990-02-05 |
-
1984
- 1984-08-16 JP JP17089584A patent/JPS6148992A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0217271U (en) * | 1988-03-14 | 1990-02-05 | ||
| JPH0543904Y2 (en) * | 1988-03-14 | 1993-11-05 |
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