JPS6148015A - Digital phase controller - Google Patents
Digital phase controllerInfo
- Publication number
- JPS6148015A JPS6148015A JP59170263A JP17026384A JPS6148015A JP S6148015 A JPS6148015 A JP S6148015A JP 59170263 A JP59170263 A JP 59170263A JP 17026384 A JP17026384 A JP 17026384A JP S6148015 A JPS6148015 A JP S6148015A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- runaway
- digital phase
- gamma
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/12—Regulating voltage or current wherein the variable actually regulated by the final control device is ac
- G05F1/40—Regulating voltage or current wherein the variable actually regulated by the final control device is ac using discharge tubes or semiconductor devices as final control devices
- G05F1/44—Regulating voltage or current wherein the variable actually regulated by the final control device is ac using discharge tubes or semiconductor devices as final control devices semiconductor devices only
- G05F1/45—Regulating voltage or current wherein the variable actually regulated by the final control device is ac using discharge tubes or semiconductor devices as final control devices semiconductor devices only being controlled rectifiers in series with the load
- G05F1/455—Regulating voltage or current wherein the variable actually regulated by the final control device is ac using discharge tubes or semiconductor devices as final control devices semiconductor devices only being controlled rectifiers in series with the load with phase control
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Voltage And Current In General (AREA)
- Control Of Electrical Variables (AREA)
- Control Of Direct Current Motors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は静止形電力変換器のディジタル制御装置に係わ
り、特にディジタル位相制御装置のＣＰＵ暴走時に電力
変換器主回路を保護するゲート制御回路に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital control device for a static power converter, and more particularly to a gate control circuit that protects the main circuit of a power converter when the CPU of a digital phase control device goes out of control.
従来の技術
近年、サイリスタ変換器等による電動機の可変速装置は
、マイクロコンピュータを制御中枢部とするディジタル
制御（ＤＤＯ）が急速に進み、旧来のアナログ制御に較
べて高速、高精度、調整不要化さらにはドリフトレス化
が実現されている。Conventional technology In recent years, digital control (DDO), which uses a microcomputer as the control center, has rapidly progressed for variable speed devices for electric motors using thyristor converters, etc., and compared to traditional analog control, it is faster, more accurate, and requires no adjustment. Furthermore, driftless technology has been achieved.
例えば、サイリスタレオナードの順変換部、−次電圧制
御装置などのコンバータは、その位相制御に旧来のアナ
ログ位相器に代えてマイクロコンピュータによυ点弧位
相を演算処理で求めるものがある。例えば、特開昭５８
−２０７８６７号公報、検印ほか「サイリスタ変換器デ
ィジタル制御用ゲートパルス発生方式」昭）０５７年電
気学会全国大会論文集、押出ほか「直流電動機の全ディ
ジタル制御」日立評論ＶＯＬ ６１ Ｎｏ １０ （１
９７９年１０月）、泉ほか「ＤＤＣによるサイリスタレ
オナードの制御」富士時報ＶＯＬ５４１４０１０ （１
９８１年１０月）がある。For example, some converters such as thyristor Leonard's forward converter and -order voltage control device use a microcomputer to calculate the υ firing phase in place of the conventional analog phase shifter for phase control. For example, JP-A-58
Publication No. 207867, stamp, etc. ``Gate pulse generation method for digital control of thyristor converter'' Proceedings of the 20057 National Conference of the Institute of Electrical Engineers of Japan, extrusion, etc. ``Full digital control of DC motors'' Hitachi Review VOL 61 No 10 (1
October 979), Izumi et al. “Control of Thyristor Leonard by DDC” Fuji Jiho VOL5414010 (1
October 981).
発明が解決しようとする問題点
従来の位相制御は旧来のアナログ位相器の信号処理方式
を基本にしたものが殆んどであシ、 ＣＰＵによる制御
角の演算及び演算結果をプログラマブルタイマ（例えば
インテル社製８２５３）ｉ使ってゲートパルス金発生さ
せる。ＯのようなＣＰＵによる位相制御ではＣＰＵの異
常等によりＣＰＵ暴走が発生したときの保護が難しくな
る。Problems to be Solved by the Invention Most of the conventional phase controls are based on the signal processing method of the old analog phase shifter. Generate gate pulse gold using 8253)i manufactured by Co., Ltd. With phase control by the CPU such as O, it is difficult to protect against CPU runaway due to CPU abnormality or the like.
例えば、サイリスタレオナード等の順変換器では、その
運転停止時に直流リアクトルや電動機のインダクタンス
分によるエネルギーの減衰を待ってゲートしゃ断を行な
う必要がある。このため、通常制御しゃ断（位相器のグ
ー＋１−転流余裕角ｒのリミット値までシフトさせる）
を行ない、 約２００ｍ ｓ前後の時間経過後にゲート
しゃ断七行なっている。従って、ＯＰＵ暴走時に位相器
のゲートを転流余裕角ｒまでシフトさせる時間とエネル
ギー減衰を待つ時間の合計になる大きな時間遅れが生じ
て主回路側のスイッチ素子破損になる虞れがあった。For example, in a forward converter such as a thyristor Leonard, when the converter is stopped, it is necessary to wait for the energy to decay due to the inductance of the DC reactor or electric motor before the gate is shut off. For this reason, normal control cutoff (shift to the limit value of phaser goo + 1 - commutation margin angle r)
After approximately 200ms had passed, the gate was shut off seven times. Therefore, when the OPU runs out of control, there is a large time delay, which is the sum of the time to shift the gate of the phase shifter to the commutation margin angle r and the time to wait for energy decay, which may result in damage to the switch element on the main circuit side.
問題点を解決するための手段と作用
本発明は、ハードウェア構成のｒリミット発生回路を設
け、暴走検出時にマイクロプロセッサ側のゲート信号出
力に代えて該γリミット発生回路の出力をゲート信号と
する切換えをし、この切換え後に所定時間でゲートしゃ
断をするゲート信号・制御回路を設け、暴走発生時の動
作不能ｔ ｒ ＩＪ ミツト発生回路でバックアップす
ることで電力変換器の保護を行なりようにしたものであ
る。Means and Effects for Solving Problems The present invention provides an r-limit generation circuit with a hardware configuration, and uses the output of the γ-limit generation circuit as a gate signal in place of the gate signal output on the microprocessor side when a runaway is detected. The power converter is protected by providing a gate signal/control circuit that switches the gate and shuts off the gate at a predetermined time after switching, and backs up the power converter with an inoperable tr IJ power generation circuit when runaway occurs. It is something.
実施例
第１図は本発明の一実施例を示すゲート制御回路図を示
す。マイクロプロセッサ１の暴走監視回路２は、ＣＰＵ
のクロック信号停止監視及び周知のウォッチドッグタイ
マによる異常弦視機能を有してマイクロプロセッサ１の
暴走（異常）を検出したときに暴走検出信号ＷＤＴｉ発
生する。ディジタル位相器３は、プログラマブルタイマ
（例えばインテル社製８２５３）により構成され、マイ
クロプロセッサ１が演算した位相制御角αのデータがカ
ウントレジスタに与えられ、このデータに応じたタイミ
ングのゲート信号を電力変換器のａ相電源に同期して出
力する。Embodiment FIG. 1 shows a gate control circuit diagram showing an embodiment of the present invention. The runaway monitoring circuit 2 of the microprocessor 1 is a CPU
When a runaway (abnormality) of the microprocessor 1 is detected, the runaway detection signal WDTi is generated. The digital phase shifter 3 is composed of a programmable timer (for example, Intel 8253), and the data of the phase control angle α calculated by the microprocessor 1 is given to the count register, and the gate signal at the timing according to this data is converted into power. Outputs in synchronization with the A-phase power supply of the device.
Ｉ ＩＪ ミツト発生回路４は、転流余裕角ｒＶｃ合わ
せたゲート信号を常時発生している。この回路４は例え
ば第２図に示すアナログ位相器により構成される。同図
において、アクティブフィルタ１１（ハ電力変換器の３
相電源、同期信号Ｕ、υ、旬から高調波成分金除去し、
この３相出力Ｕ、Ｖ、Ｖｌｆｒ設定器１２の設定値を比
較基準とするアナログ位相姦１３Ｕ 、 １３Ｖ 、
１３Ｗで比較することで該位相器１３Ｕ 、 １３Ｖ
、 １３ＷＯ出力にゲート信号ＧＵ、ＧＶ。I IJ The power generating circuit 4 constantly generates a gate signal that matches the commutation margin angle rVc. This circuit 4 is constituted by, for example, an analog phase shifter shown in FIG. In the figure, an active filter 11 (3) of a power converter is shown.
Remove harmonic components from the phase power supply, synchronization signals U, υ, and
The analog phase difference 13U, 13V, using the setting values of the three-phase output U, V, Vlfr setting device 12 as a comparison standard.
By comparing at 13W, the phase shifter 13U and 13V
, 13WO outputs gate signals GU, GV.
ＧＷを得、この反転出力として論理インノく一夕１＃。GW is obtained, and this inverted output is used as a logical inversion 1#.
１４Ｖ、１４Ｗにゲート信号ＧＸ 、ＧＹ 、ＧＺ’ｉ
得る。Gate signals GX, GY, GZ'i to 14V and 14W
obtain.
各部波形をＷＪ３図に示す。The waveforms of each part are shown in Figure WJ3.
ディジタル位相器３のゲート信号とγリミット発生回路
４のゲート信号はゲート出力バッファ５゜６の入力にさ
れ、該バッファによって一方のゲート信号が選択されて
ゲート出力バッファ７０入力にされる。ゲート出力バツ
ファ５．６及び７はそのイネーブル端子コ、へのローレ
ベル入力でゲート信号を出力し、ノ・イレペル入力で高
出力インピーダンスになる３ステートバツフアにされる
。そして、バッファ５のイネーブル端子に１への制御入
力は暴走検出信号ＶＤＴの反転信号が論理インバータ８
で与えられ、バッファ６のイネーブル端子Ｆ１％への制
御入力は暴走検出信号ＶＤＴが与えられる。従って正常
動作時にはバッファ５金通してディジタル位相器３から
の正規のゲート信号が取出され、暴走検出時にはバック
アロを通してγリミット発生回路４からのゲート信号が
取出される。The gate signal of the digital phase shifter 3 and the gate signal of the γ limit generating circuit 4 are input to a gate output buffer 5.6, and one gate signal is selected by the buffer and input to the gate output buffer 70. The gate output buffers 5.6 and 7 output a gate signal with a low level input to their enable terminals, and are made into three-state buffers having a high output impedance with a low level input. The control input to 1 at the enable terminal of the buffer 5 is that the inverted signal of the runaway detection signal VDT is input to the logic inverter 8.
The control input to the enable terminal F1% of the buffer 6 is given the runaway detection signal VDT. Therefore, during normal operation, the normal gate signal from the digital phase shifter 3 is taken out through the buffer 5, and when runaway is detected, the gate signal from the γ limit generation circuit 4 is taken out through the back arrow.
バッファ７のイネーブル端子Ｅ％には一１常時はと
ローベル入力が与えられ暴走検出信号ＶＤＴに対してタ
イマ９から所定時間遅れてノ・イレペル入力が与えられ
る。このタイマ９は電力変換器のりアクドルや負荷電動
機のインダクタンス分によるエネルギー減衰遅れを確保
する時間設定がなされ、該タイマ９の設定時間後にゲー
ト出力バツ７ア７の出力しゃ断を行なう。ゲート出力バ
ッファ７の出力はゲートドライバ１０を通して電力変換
器の各スイッチ素子にゲートパルスｔ−与、する。The enable terminal E% of the buffer 7 is always supplied with a low level input, and is supplied with a low level input after a predetermined time delay from the timer 9 with respect to the runaway detection signal VDT. This timer 9 is set to a time to ensure a delay in energy decay due to the inductance of the power converter accelerator and the load motor, and the output of the gate output 7a 7 is cut off after the time set by the timer 9. The output of the gate output buffer 7 is applied to each switch element of the power converter through a gate driver 10 with a gate pulse t-.
こうした傳成において、マイクロプロセッサ１の異常等
によってその暴走が発生すると、暴走監視回路２が動作
してその検出信号ＶＤＴがローレベルとなる。これによ
り、それまでディジタル位相器３の出力をゲートパルス
としていた動作からｒリミット発生回路４の出力をゲー
トパルスとする動作に切換えられ、このゲートパルス切
換えからタイマ９０時限（例えば２００ ｍｇ）後にゲ
ートパルスしゃ断が行なわれる。このように、マイクロ
プロセッサの暴走時には電力変換器の制御しゃ断（γリ
ミット１で制御角αを絞る）とゲートしゃ断が行なわれ
て電力変換器の保護を行なう。In such a development, if a runaway occurs due to an abnormality in the microprocessor 1, the runaway monitoring circuit 2 operates and its detection signal VDT becomes low level. As a result, the operation in which the output of the digital phase shifter 3 was used as the gate pulse is switched to the operation in which the output of the r limit generation circuit 4 is used as the gate pulse, and after the timer 90 time period (for example, 200 mg) after this gate pulse switch, the gate pulse is activated. Pulse cutoff is performed. In this manner, when the microprocessor goes out of control, the control of the power converter is cut off (the control angle α is narrowed down by γ limit 1) and the gate is cut off to protect the power converter.
発明の効果
本発明によれば、ディジタル位相制御装置にノ・−ドウ
エア構成のｒリミット発生回路をバックアップとして用
意し、マイクロプロセッサの暴走時にはγ１７ ミツト
発生回路のゲート信号に切換えて電力変換器を位相絞シ
込みをした後ゲートしゃ断するため、少しのハードウェ
ア増設で位相絞り込みを確実、迅速にして装置の信頼性
を大幅に向上できる効果がある。Effects of the Invention According to the present invention, an r-limit generation circuit having a hardware configuration is prepared as a backup for the digital phase control device, and when the microprocessor goes out of control, it is switched to the gate signal of the γ17 limit generation circuit to control the phase of the power converter. Since the gate is shut off after narrowing down, a small amount of additional hardware can ensure phase narrowing down quickly and reliably, greatly improving the reliability of the device.
また、γリミット発生回路はサイリスタレオナの
−ド正転、逆転側サイリスタへの切換時の制御しｌや折
用としても利用することができるし、また逆変換モード
（回生モード）で動作中の停電発生時の転流失敗保護用
のγリミットとしても利用できる。In addition, the γ limit generation circuit can be used to control the switching of the thyristor Leona to the forward and reverse thyristors, and can also be used for switching when the thyristor Leona is operating in the reverse conversion mode (regeneration mode). It can also be used as a gamma limit to protect against commutation failure in the event of a power outage.
第１図は本発明の一実施例を示すゲート制御回略図、・
窮２図は第１図におけるｒリミット発生回路４の具体的
回路図、第３図は第２図の各部波形図である。
１・・・マイクロプロセッサ、２・・・暴走監視回路、
３・・・ディジタル位相器、４・・・γリミット発生回
路、５．６．７・・・ゲート出力バツ７ア、９・・・タ
イマ、１０・・・ゲートドライバ、 １１・・・アクテ
ィブフィルタ、１２・・・γ設定器、１３Ｕ 、 １３
Ｖ 、 Ｌ３Ｗ・・・アナログ位相器。FIG. 1 is a gate control schematic diagram showing an embodiment of the present invention.
2 is a specific circuit diagram of the r limit generation circuit 4 in FIG. 1, and FIG. 3 is a waveform diagram of each part of FIG. 2. 1... Microprocessor, 2... Runaway monitoring circuit,
3...Digital phase shifter, 4...γ limit generation circuit, 5.6.7...Gate output x7a, 9...Timer, 10...Gate driver, 11...Active filter , 12...γ setting device, 13U, 13
V, L3W...Analog phase shifter.
Claims (1)
で演算した位相制御角をディジタル位相器に与え、該デ
ィジタル位相器からゲート信号を得るディジタル位相制
御装置において、電力変換器の各スイッチ素子の転流余
裕角を設定して該位相のゲート信号を常時発生するγリ
ミット発生回路と、マイクロプロセッサの暴走検出信号
によつて前記ディジタル位相器からのゲート信号に代え
て前記γリミット発生回路のゲート信号を電力変換器の
ゲートパルスとして出力し、該暴走検出信号が与えられ
た時点から所定時間後に前記ゲートパルスをしや断する
ゲート信号制御回路とを備えたことを特徴とするディジ
タル位相制御装置。For gate control of a static power converter, a digital phase control device applies a phase control angle calculated by a microprocessor to a digital phase shifter and obtains a gate signal from the digital phase shifter. a gamma limit generating circuit that always generates a gate signal of the phase by setting a margin angle; and a gamma limit generating circuit that generates a gate signal of the gamma limit generating circuit in place of the gate signal from the digital phase shifter in response to a runaway detection signal from a microprocessor. A digital phase control device comprising: a gate signal control circuit that outputs a gate pulse of a power converter and cuts off the gate pulse after a predetermined time from when the runaway detection signal is applied.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59170263A JPS6148015A (en) | 1984-08-15 | 1984-08-15 | Digital phase controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59170263A JPS6148015A (en) | 1984-08-15 | 1984-08-15 | Digital phase controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6148015A true JPS6148015A (en) | 1986-03-08 |
| JPH0542692B2 JPH0542692B2 (en) | 1993-06-29 |
Family
ID=15901691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59170263A Granted JPS6148015A (en) | 1984-08-15 | 1984-08-15 | Digital phase controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6148015A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022146966A1 (en) * | 2020-12-30 | 2022-07-07 | Texas Instruments Incorporated | Hardware based motor drive controller |
-
1984
- 1984-08-15 JP JP59170263A patent/JPS6148015A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022146966A1 (en) * | 2020-12-30 | 2022-07-07 | Texas Instruments Incorporated | Hardware based motor drive controller |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0542692B2 (en) | 1993-06-29 |
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