JPS6146074A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6146074A JPS6146074A JP16866184A JP16866184A JPS6146074A JP S6146074 A JPS6146074 A JP S6146074A JP 16866184 A JP16866184 A JP 16866184A JP 16866184 A JP16866184 A JP 16866184A JP S6146074 A JPS6146074 A JP S6146074A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- resist film
- electrode
- film
- coated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 238000001312 dry etching Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 4
- 238000010884 ion-beam technique Methods 0.000 abstract description 3
- 239000010931 gold Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004070 electrodeposition Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 238000005275 alloying Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Drying Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置、特に電界効果トランジスタＣＦＥ
Ｔ）の電極形成の製造方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, particularly a field effect transistor CFE.
The present invention relates to a manufacturing method for forming an electrode in T).
最近ガリウム砒素（ＧａＡｓ） Ｆ Ｅ Ｔ及びその集
積回路の特性として、高速、高利得が要求されており、
これらの特性を実現するためには、ＦＥＴの素子の微細
化が必要とされる。Recently, high speed and high gain are required as characteristics of gallium arsenide (GaAs) FETs and their integrated circuits.
In order to realize these characteristics, miniaturization of FET elements is required.
通常電極配置はソース電極とゲート電極間の電気抵抗を
小にして周波数特性や利得を上げるとともに、又ドレイ
ン電極とゲート電極間は印加される電圧に対し耐圧を有
する間隔が必要である。Normal electrode arrangement requires that the electrical resistance between the source electrode and the gate electrode be reduced to increase frequency characteristics and gain, and that there be a gap between the drain electrode and the gate electrode that can withstand the applied voltage.
このような構造を有する電極の形成については、例えば
高解像度のりソグラフィである電子ビーム露光法の利用
や、セルフアライメント法による電極形成法が行われて
いるが、一般に電極形成は、ソース電極とドレイン電極
を形成した後に、再度他のマスクを用いて、先に形成さ
れた両電極の間にゲート電極を形成するために、その結
果、ソース電極とゲート電極及びゲート電極とドレイン
電極の間隔を基板面内で或いは基板毎に正確に制御する
ことは困難であった。To form electrodes with such a structure, for example, the electron beam exposure method, which is high-resolution lithography, and the self-alignment method are used. After forming the electrode, use another mask again to form the gate electrode between the two previously formed electrodes, thereby adjusting the distance between the source electrode and the gate electrode and between the gate electrode and the drain electrode on the substrate. It has been difficult to accurately control within the plane or for each substrate.
一方セルファライメント法による電極形成法では、微少
なソース電極とゲート電極及びゲート電極とドレイン電
極の間隔を比較的高精度に形成することが可能であるが
、ソース電極とゲート電極間隔を小にして、ゲート電極
とドレイン電極の間隔を耐圧を考慮した適当な間隔で形
成する、所謂非対称の電極の形成は困難であり、これら
の適切な電極の相互間隔を有する電極形成法が望まれて
いる。On the other hand, in the electrode formation method using the self-alignment method, it is possible to form minute intervals between the source electrode and the gate electrode, and between the gate electrode and the drain electrode with relatively high precision. However, it is difficult to form so-called asymmetric electrodes in which the gate electrode and the drain electrode are formed at an appropriate interval in consideration of withstand voltage, and a method of forming electrodes having an appropriate mutual interval between these electrodes is desired.
第２図（ａ）〜第２図（Ｃ）はＦＥＴの従来の製造工程
の概要を説明する断面図であるが、第２図（ａ）でＧａ
Ａｓの半絶縁性基板１があり、その表面にＮ型のＧａＡ
ｓ層２を厚さが０．４μｍ程度形成し、その上に窒化シ
リコンＢ’Ａ３を厚みが０．３μｍ程度を形成して、更
にその上にレジスト膜４を被着して、ソース、ドレイン
の各電極領域をパターニングする。FIGS. 2(a) to 2(C) are cross-sectional views explaining the outline of the conventional manufacturing process of FET.
There is a semi-insulating substrate 1 made of As, and N-type GaA on its surface.
An s layer 2 is formed with a thickness of about 0.4 μm, and silicon nitride B'A3 is formed on it with a thickness of about 0.3 μm, and a resist film 4 is further deposited on it to form the source and drain. pattern each electrode region.
第２図（ｂｌは、窒化シリコン膜３を工・ノチングした
後に、金ゲルマウム（ＡｕＧｅ）２００人と金３０００
人とでなるＡｕＧｅ／ Ａｕ膜５を蒸着により被膜した
ものであって、この金ゲルマウム、金（＾ｕＧｅ／Ａｕ
）によりドレイン電極６とソース電極７が形成される。Figure 2 (bl) shows that after the silicon nitride film 3 was etched and notched, 200 gold germium (AuGe) and 3000 gold
The AuGe/Au film 5 made of humans is coated by vapor deposition, and this gold-germaum, gold (^uGe/Au
), a drain electrode 6 and a source electrode 7 are formed.
第２ｍｔｃ＋はレジスト膜４とその上に被着したＡｕＧ
ｅ／＾Ｕ膜５をアセトン液中で超音波により剥離した後
に、ゲート電極を形成するために、レジスト膜８を被着
してゲート電極を形成する位置のレジスト膜にパターニ
ング、エツチングによりゲート電極部が開口され、この
開口部にアルミニューム（ＡＩ） ９を蒸着してゲー
ト電極を形成したものであるが、このパターニングの際
のゲート位置の位置決めは、顕微鏡を使用して目視で行
われ、アライナ−により基板上で位置ぎめが行われる。The second mtc+ is the resist film 4 and the AuG deposited on it.
After peeling off the e/^U film 5 using ultrasonic waves in an acetone solution, a resist film 8 is applied to form the gate electrode by patterning and etching the resist film at the position where the gate electrode is to be formed. A gate electrode is formed by vapor depositing aluminum (AI) 9 into this opening, and the positioning of the gate during patterning is done visually using a microscope. Positioning is performed on the substrate by an aligner.
又、最近開発されたセルフアライメント法の一例として
、最初に＾ｌの電極を基板上に形成しておき、これに酸
化シリコン膜を形成して、ゲート電極の両端部の所定の
長さに酸化シリコンの長さを残しておいて、残りの酸化
シエリコンはドライエツチングによって除去した後に、
全表面にＡｕＧｅ／＾Ｕ膜を被着し、その後酸化シリコ
ンの上のＡｕＧｅ／Ａｕ１ｌを除去することにより、自
動的に酸化シリコンの長さに相当するゲート電極とソー
ス電極及びドレイン電極との間隔が決定される方法であ
るが、いずれも製造工程の複雑性と電極の位置決めの精
度について問題がある。In addition, as an example of a recently developed self-alignment method, an electrode is first formed on a substrate, a silicon oxide film is formed on this, and a silicon oxide film is oxidized to a predetermined length on both ends of the gate electrode. After leaving a length of silicon and removing the remaining silicon oxide by dry etching,
By depositing an AuGe/^U film on the entire surface and then removing the AuGe/Au film on the silicon oxide, the distance between the gate electrode and the source and drain electrodes is automatically adjusted to the length of the silicon oxide. However, both methods have problems with the complexity of the manufacturing process and the accuracy of electrode positioning.
上記従来の製造方法ではソース電極とドレイン電極を形
成した後に、再度別のマスクを用いてゲート電極を形成
するために、ソース電極とゲート電極及びゲート電極と
ドレイン電極の間隔を再現性が良く正確に制御すること
は困難であるし、又セルフアライメント法による電極形
成法は、ソース電極とゲート電極間隔を小にして、ゲー
ト電極とドレイン電極の間隔が適当に大きな間隔で形成
して非対称に形成することが困難であるという問題点が
ある。In the conventional manufacturing method described above, after forming the source electrode and drain electrode, a separate mask is used to form the gate electrode again. In addition, the electrode formation method using the self-alignment method reduces the gap between the source electrode and the gate electrode, and forms the gap between the gate electrode and the drain electrode with a suitably large gap to form them asymmetrically. The problem is that it is difficult to do so.
本発明は上記間Ｂ点を解消したＦＥＴの電極形成方法を
提供するもので、その手段は、半導体基板のチャンネル
層上に絶縁膜を形成して、該絶縁膜上でソース電極、ド
レイン電極、及びゲート電極を形成する位置に、同一マ
スクで同時にパターニングして開口した後、該ゲート電
極の位置を有機レジスト膜で被覆して該ソース電極と該
ドレイン電極用金属を被着し、次に全面に有機レジスト
膜を塗布して表面を平坦化して、上記絶縁膜の高さ迄ド
ライエツチングを行ない、次に該ゲート電極領域のレジ
スト膜を除去して、全面に、ゲート電極用金属を被着し
た後にその表面に有機レジスト膜で被覆して、その表面
を平坦化した後、上記絶縁膜の高さ迄ドライエツチング
を行ってゲート電極を形成することを特徴とする半導体
装置の製造方法によって達成できる。The present invention provides a method for forming electrodes of an FET that eliminates the above-mentioned point B. The method includes forming an insulating film on a channel layer of a semiconductor substrate, forming a source electrode, a drain electrode, and a drain electrode on the insulating film. After patterning and opening at the same time using the same mask at the positions where the gate electrode and the gate electrode are to be formed, the gate electrode position is covered with an organic resist film, the source electrode and the drain electrode metal are deposited, and then the entire surface is patterned. An organic resist film is applied to the surface to planarize the surface, dry etching is performed to the height of the insulating film, and then the resist film in the gate electrode area is removed and gate electrode metal is deposited on the entire surface. This is achieved by a method for manufacturing a semiconductor device, which comprises: coating the surface with an organic resist film, flattening the surface, and then performing dry etching to the height of the insulating film to form a gate electrode. can.
本発明は同一マスクを使用してＦＥＴのソース電極、ド
レイン電極、ゲート電極の位置を同時にパターニングす
ること、及び段差をレジストで平坦化してイオンビーム
エツチング電極金属を加工することを利用して、ソース
電極とゲート電極の間隔が小さく、ゲート電極にドレイ
ン電極の間隔を耐圧を考慮した適当な間隔で形成する、
所謂非対称形ＦＥＴを高精度微細寸法で再現性良く製造
できるように考慮がなされている。The present invention uses the same mask to pattern the positions of the source electrode, drain electrode, and gate electrode of the FET at the same time, and processes the electrode metal by ion beam etching by flattening the steps with a resist. The distance between the electrode and the gate electrode is small, and the distance between the gate electrode and the drain electrode is formed at an appropriate distance considering the withstand voltage.
Consideration has been given to manufacturing so-called asymmetric FETs with high precision and fine dimensions with good reproducibility.
第１図（ａ）〜第１図（８）は、本発明の詳細な説明す
る断面図であるが、第１図（ａ）は、半絶縁性基板１１
の上にＮ型のＧａＡｓ半導体層１２があり、その上に窒
化シリコン膜１３を０．３μｍ程度の厚みに形成して、
更にその上にレジス）ｌＩ＊１４で被覆したものである
。FIG. 1(a) to FIG. 1(8) are cross-sectional views explaining the present invention in detail, and FIG. 1(a) shows the semi-insulating substrate 11.
There is an N-type GaAs semiconductor layer 12 on top, and a silicon nitride film 13 is formed to a thickness of about 0.3 μm on top of the N-type GaAs semiconductor layer 12.
Furthermore, it was coated with resist) lI*14.
第１図（′ｂ）は、レジスト膜１４をパターニングによ
り、窒化シリコン膜１３にソース電極、ドレイン電極、
ゲート電極領域を同時にエツチングして開口した後に、
ゲート電極位置にレジスト膜１４を被覆して、表面全体
に蒸着法によって、Ａｕ／ＡｕＧｅ １５を０．３μｍ
程度の厚みに形成し、次に全面に５μｍ程度のかなり厚
いレジスト膜１６を被覆するが、この厚いレジスト膜１
６０目的は窒化シリコン膜１３や、レジスト膜１４によ
る凹凸を平坦化し、イオンエツチングをした際に全面が
平均してエツチングがなされるように考慮されたもので
ある。FIG. 1('b) shows that by patterning the resist film 14, the silicon nitride film 13 has a source electrode, a drain electrode,
After simultaneously etching and opening the gate electrode area,
A resist film 14 is coated on the gate electrode position, and Au/AuGe 15 is deposited to a thickness of 0.3 μm over the entire surface by vapor deposition.
Then, the entire surface is covered with a fairly thick resist film 16 of about 5 μm, but this thick resist film 1
The purpose of 60 is to flatten the unevenness caused by the silicon nitride film 13 and the resist film 14 so that when ion etching is performed, the entire surface is etched evenly.
第１図（Ｃ１は、レジスト膜１６とＡｕ／ＡｕＧｅ １
５とレジストＢｆＡ１４を順次表面から矢印のように、
窒化シリコン膜が露出する迄イオンエツチングした後、
残ったレジスト膜１４を剥離した状態を示したものであ
り、この工程では、Ａｕ／ＡｕＧｅの合金化、ソース電
極とドレイン電極間の電流測定、及びゲート電極開口部
のＧａＡｓ層の浅い化学エツチングも行われる。FIG. 1 (C1 is the resist film 16 and Au/AuGe 1
5 and resist BfA14 sequentially from the surface as shown by the arrow.
After ion etching until the silicon nitride film is exposed,
This figure shows the state in which the remaining resist film 14 has been peeled off, and in this process, alloying of Au/AuGe, current measurement between the source and drain electrodes, and shallow chemical etching of the GaAs layer at the gate electrode opening are also performed. It will be done.
第１図（ｄｌは、表面にゲート電極となるアルミニュー
ム２０を蒸着して、その上に表面が平坦になる程度にか
なり厚いレジスト膜２１を３μｍ程度に被着したもので
ある。In FIG. 1 (dl), aluminum 20, which will become a gate electrode, is vapor-deposited on the surface, and a fairly thick resist film 21 of about 3 μm is deposited thereon to make the surface flat.
第１図（ａ）は、厚いレジスト膜を上記と同様にイオン
ビームエツチングを行ない、レジストＩＰＪ２１とアル
ミニューム２０をエツチング除去したものであって、こ
れによりＦＥＴのソース電挽１７、ドレイン電極１８、
ゲート電極２２が正確な位置に形成できる。In FIG. 1(a), the thick resist film is subjected to ion beam etching in the same manner as described above, and the resist IPJ 21 and aluminum 20 are etched away.
Gate electrode 22 can be formed at an accurate position.
以上詳細に説明したように本発明によるＦＥＴの製造方
法を採用することにより、ＦＥＴが容易且つ高精度で製
造することができ効果大なるものがある。As explained above in detail, by employing the FET manufacturing method according to the present invention, FETs can be manufactured easily and with high precision, which has great effects.
第１図は本発明の製造工程を説明する断面図、第２図は
従来の製造工程を説明する断面図である。
図において、１１は半絶縁性基板、１２はＮ型のＧａＡ
ｓ半導体眉、１３は窒化シリコン膜、１４はレジスト１
１Ａ、１５はＡｕ／ＡｕＧｅ ％ １６はレジストＨ臭
、１７はソース電極、１８はドレイン電極、１９はゲー
ト電極の開口部、２０はアルミニューム、２１はレジス
ト膜、２２はゲー）Ｉｔ極をそれぞれ示している。
第１図FIG. 1 is a sectional view illustrating the manufacturing process of the present invention, and FIG. 2 is a sectional view illustrating the conventional manufacturing process. In the figure, 11 is a semi-insulating substrate, 12 is an N-type GaA
s semiconductor eyebrow, 13 is silicon nitride film, 14 is resist 1
1A, 15 are Au/AuGe %, 16 is the resist H odor, 17 is the source electrode, 18 is the drain electrode, 19 is the opening of the gate electrode, 20 is aluminum, 21 is the resist film, 22 is the gate) It electrode, respectively. It shows. Figure 1
Claims (1)
縁膜上でソース電極、ドレイン電極、及びゲート電極を
形成する位置に、同一マスクで同時にパターニングして
開口した後、該ゲート電極の位置を有機レジスト膜で被
覆して該ソース電極と該ドレイン電極用金属を被着し、
次に全面に有機レジスト膜を塗布して表面を平坦化して
、上記絶縁膜の高さ迄ドライエッチングを行ない、次に
該ゲート電極領域のレジスト膜を除去して、全面に、ゲ
ート電極用金属を被着した後にその表面に有機レジスト
膜で被覆して、その表面を平坦化した後、上記絶縁膜の
高さ迄ドライエッチングを行ってゲート電極を形成する
ことを特徴とする半導体装置の製造方法。An insulating film is formed on the channel layer of the semiconductor substrate, and openings are formed on the insulating film at the positions where the source electrode, drain electrode, and gate electrode are to be formed by simultaneous patterning using the same mask, and then the positions of the gate electrodes are formed. coated with an organic resist film to deposit metals for the source electrode and the drain electrode,
Next, an organic resist film is applied to the entire surface to planarize the surface, and dry etching is performed to the height of the insulating film.Then, the resist film in the gate electrode area is removed and the gate electrode metal is applied to the entire surface. After depositing the insulating film, the surface thereof is coated with an organic resist film, the surface is planarized, and then dry etching is performed to the height of the insulating film to form a gate electrode. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16866184A JPS6146074A (en) | 1984-08-10 | 1984-08-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16866184A JPS6146074A (en) | 1984-08-10 | 1984-08-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6146074A true JPS6146074A (en) | 1986-03-06 |
Family
ID=15872155
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16866184A Pending JPS6146074A (en) | 1984-08-10 | 1984-08-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6146074A (en) |
-
1984
- 1984-08-10 JP JP16866184A patent/JPS6146074A/en active Pending
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