JPS6144442A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6144442A
JPS6144442A JP16594984A JP16594984A JPS6144442A JP S6144442 A JPS6144442 A JP S6144442A JP 16594984 A JP16594984 A JP 16594984A JP 16594984 A JP16594984 A JP 16594984A JP S6144442 A JPS6144442 A JP S6144442A
Authority
JP
Japan
Prior art keywords
film
oxide film
nitride film
etched
films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16594984A
Other languages
Japanese (ja)
Inventor
Fumisato Tamura
文識 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16594984A priority Critical patent/JPS6144442A/en
Publication of JPS6144442A publication Critical patent/JPS6144442A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To prevent the generation of bird beaks by preventing the lateral diffusion of an oxidation seed at the time of selective oxidation by a method wherein the second Si nitride films are selectively formed in the parts of side etching of an oxide film located under a patterned Si nitride film. CONSTITUTION:An Si oxide film 2 and an Si nitride film 3 are grown on an Si substrate 1, and the films 3 and 2 are etched by using a photo resist 4 as a mask. Next, the resist 4 is removed and the film 2 is side-etched. If necessary, a thin oxide film 5 is formed. Then, the second Si nitride film 6 is formed, and the films 6 are selectively left at side-etched regions of the film 2 by etching, using the film 3 as a mask. Thereafter, the element isolating region is selectively oxidized in a direct manner or by using the films 3 and 6 after removal of the film 5, resulting in the formation of a relatively thick oxide film 7. This process can prevent bird beaks with a very small amount of the film 7 that intrudes under the film 6.

Description

【発明の詳細な説明】 （産業上の利用分野ン 本発明に、半導体装置の製造方法、特にシリコン基板を
選択的に酸化する工程を含む半導体装置の製造方法に関
するものでおる。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device including a step of selectively oxidizing a silicon substrate.

（従来の技術〕 従来１選択的にシリコン基板を酸化する際に発生するい
わゆるバーズビークと呼ばれる耐酸化性マスク下への酸
化物の食込み現象を抑制する方法として、緩衝用酸化膜
ｔｉ＆板に欠陥を発生させない程ＩｆＫ薄くしてゆく方
法や緩衝膜として、シリコン鼠化酸化膜ｔ−用いて、酸
化膜の横方向への拡散を抑制するなどの方法がおる。(Prior art) As a method of suppressing the so-called bird's beak, which occurs when oxidizing a silicon substrate selectively, in which the oxide penetrates under the oxidation-resistant mask, defects are created in the buffer oxide film Ti and plate. There are methods such as making IfK thin enough to prevent the occurrence of IfK, and using a silicon doped oxide film t- as a buffer film to suppress the lateral diffusion of the oxide film.

（発明が解決しようとする問題点） しかし、緩衝用酸化膜を最７ｒ　７ｔに薄くしてしまり
と１選択酸化し友後の工程でｌ子領域内の機能部形成の
ために、耐酸化性マスクとして用いたシリコン窒化膜を
選択的にエツチングすると藪。(Problem to be Solved by the Invention) However, the buffer oxide film is made as thin as 7R to 7T, and selective oxidation is performed on the edge and in the subsequent process, in order to form a functional part in the L element region, the oxidation resistance is When the silicon nitride film used as a mask is selectively etched, a thicket appears.

窒化膜を除去するときに、薄い酸化膜も除去されて、さ
らに基板に損傷を与えるという欠点がある。A drawback is that when removing the nitride film, the thin oxide film is also removed, further damaging the substrate.

これは主に微細加工のため異方性のある乾式エツチング
技術を用いるために生じるものと思われる。This appears to be mainly due to the use of anisotropic dry etching technology for microfabrication.

またシリコン窒化酸化膜を緩衝膜に用い次場合。In the following case, a silicon nitride oxide film is used as a buffer film.

緩衝膜の厚さ全ある程度以下にしなければバーズビーク
抑制に対して効果がなくな力、また効果がある程度に、
シリコン窒化酸化膜を薄くすると、基板に結晶欠陥が生
じやすくなるという欠点がある。Unless the total thickness of the buffer film is below a certain level, it will not be effective in suppressing bird's beak.
A drawback of thinning a silicon nitride oxide film is that crystal defects are more likely to occur in the substrate.

（問題点を解決するための手段） 本発明は、パターニングされたシリコン窒化膜下の酸化
膜のサイドエツチングした部分に直接。(Means for Solving the Problems) The present invention directly etches the side-etched portion of the oxide film under the patterned silicon nitride film.

或いはごく薄い酸化膜を介して、第２のシリコン窒化！
ＩＸ金選択的に形成することによって選択醸化時の酸化
種の窒化膜マスク下への横方向拡散全抑制し、さらに窒
化膜バタンの周辺以外の緩衝用酸化膜の厚さは従米通フ
にしておき、後工程の窒化膜エツチング加工時に影響全
与えない半導体装置の製造方法を得る。Or the second silicon nitride through a very thin oxide film!
By selectively forming IX gold, the lateral diffusion of oxidized species under the nitride film mask during selective fermentation is completely suppressed, and the thickness of the buffer oxide film other than the area around the nitride film button is kept to a standard level. Thus, a method of manufacturing a semiconductor device is obtained which does not affect the nitride film etching process in the subsequent process.

（実施例） 次に１図面を用いて本発明をよフ詳細に説明する。(Example) Next, the present invention will be explained in detail using one drawing.

まず、第２図を用いて１本発明に関わる従来の一般的な
製造方法について述べる。First, a conventional general manufacturing method related to the present invention will be described using FIG.

第２図ｔａ＞は、シリコン基板８の上に数１０＋１メー
トルの酸化膜９ｔ−介して、減圧ＣＶＤ＠を用いてシリ
コン窒化膜１０’ｉ−底長し、ホトエツチング技術を用
いて、シリコン窒化膜１０金選択的にエッチングして、
素子分離領域金形成し友ものである。第２図（ｂ）は同
図（ａｌの工程後、シリコン窒化ａｌｏｔｉｔｒＲ化性
ｉスクとして素子分離領域に比較的厚い酸化［１１を形
成したところでおり、シリコン窒化膜１０の周辺部の下
に大きなバーズビークが発生している。In Fig. 2, a silicon nitride film 10'i is formed on a silicon substrate 8 through an oxide film 9t of several tens of meters using low pressure CVD, and then a silicon nitride film 10'i is formed using a photoetching technique. Selectively etched with 10k gold,
It is useful for forming element isolation regions with gold. FIG. 2(b) shows the same figure (after the step of al), a relatively thick oxide [11] has been formed in the element isolation region as a silicon nitride alotitr-reducing mask, and a large Bird's beak is occurring.

第１図は本発明の一実施例Ｖｃよる製造方法をその工程
順に示し次ものである。FIG. 1 shows a manufacturing method according to an embodiment Vc of the present invention in the order of its steps.

第１図ｆａｔはシリコン基板１の上に酸化膜２を数１０
＋１メ一トル成長石せ、その上に減圧ＣＶＤ法により第
１のシリコン窒化膜３に成長させ、）くターニングした
後、ホトレジスト４をマスクとしてシリコン窒化ｐＡ３
と酸化膜２ｆｔエツチングしたものである。Figure 1 shows the number of oxide films 2 on the silicon substrate 1.
A first silicon nitride film 3 is grown on top of the +1 meter growth stone by low pressure CVD, and after turning, silicon nitride pA3 is grown using the photoresist 4 as a mask.
A 2ft oxide film was etched.

第１図（ｂｌはホトレジスト４の除去と酸化膜２のサイ
ドエツチングを順不同で行なうｔものであ）。FIG. 1 (bl is a diagram in which the removal of the photoresist 4 and the side etching of the oxide film 2 are performed in random order).

必要であれば数＋１メートル程度以下の酸化膜５を形成
する。酸化膜５の膜厚は、酸化ＰＡ２のサイドエツチン
グの量や後の選択酸化するときの処理温度や成長酸化膜
７の膜厚などの条件から基板に結晶欠ＩＩ！を発生させ
ない程度に決めるが、この条件を満ｆｃ丁場合は、酸化
膜５ｔ−形成しないこともあツクる。If necessary, an oxide film 5 having a thickness of several meters or less is formed. The thickness of the oxide film 5 is determined based on conditions such as the amount of side etching of the oxidized PA2, the treatment temperature during subsequent selective oxidation, and the thickness of the grown oxide film 7. However, if this condition is satisfied, the oxide film 5t may not be formed.

第１図ｆＣ１は上記工程金紗た後、第２のシリコン窒化
膜６ｔ−形成し九ところである。FIG. 1 fC1 shows a state in which a second silicon nitride film 6t is formed after the above-mentioned process is completed.

第１図ｔｄｌは、第１のシリコン窒化膜３をマスクトシ
テ、エッチングに工）酸化膜２のサイドエツチングされ
た領域に第２のシリコン窒化膜６金選択的に残したもの
である。In FIG. 1 tdl, the first silicon nitride film 3 is masked and etched, and the second silicon nitride film 6 is selectively left in the side-etched region of the oxide film 2.

＠１図１ｅ）は同図ｔｄｌの工程後、直接、或いは酸化
膜５をエツチングしてから第１のシリコン酸化膜３と第
２のシリコン窒化膜６ｔ−耐酸化性マスクとして素子分
離領域を選択的に酸化し、比較的厚い酸化ｇ７ｔ−形成
したものである。ｌＲ化膜７は、そのまｔ＋ｅ子間分間
分離用電体として用いられるほか、基板に段差をつける
ためにエツチングされた）することもある。@1 Figure 1e) shows that after the tdl process in the same figure, the first silicon oxide film 3 and the second silicon nitride film 6t are used as an oxidation-resistant mask to select the element isolation region either directly or after etching the oxide film 5. oxidized to form a relatively thick oxidized g7t-. The 1R film 7 is used as it is as an electric body for separating the t+e elements, and may also be etched to form a step on the substrate.

（発明の効果） 本発明によれば、シリコン窒化膜６の下に食い込んでい
る酸化膜７μきわめて少く、バーズビーク金有効に防止
することができる。(Effects of the Invention) According to the present invention, the amount of the oxide film 7μ digging into the silicon nitride film 6 is extremely small, and bird's beak gold can be effectively prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図心）〜（ｅｌは本発明の一実施例による製造工程
を示す各工程での断面図、第２図（ａｌ、　ｆｂｌは従
来の一般的な選択酸化工程の各工程での断面図である。 １．８・・・・・・シリ込ン基板、２，５，７，９．１
１・・・・・・シリコン酸化ｊＸ、　３．６．　１０・
・・・・・シリコン手続補正書（自発） ５９，１２．−７ 昭和　　年　　月　　日 １、事件の表示　　　昭和５９年特　許願第１６５９４
９号２、発明の名称　　　半導体装置の製造方法３、補
正をする者 事件との関係　　　　　　　出　願　人東京都港区芝五
丁目３３番１号 ４、代理人 〒１０８　　東京都港区芝五丁目３７番８号　住友三田
ビル日本電気株式会社内 ５、補正の対象 明細書の「発明の詳細な説明」の欄 ６、補正の内容 １）明細書筒２頁１３行目の「方法や緩衝膜として、」
を「方法や、緩衝膜として」に訂正する。 ２）明細書筒３頁２行目の「窒化膜を除去するときに、
」を削除する。 ３）８Ａ細誓書第４７行目の「数１０＋ＩＪを「数１０
ナノ」に訂正する。 ４）明細書第４頁２０行目の「１０＋１メートル」を「
１０ナノメートル」に訂正する。 ５）明細書第５頁７行目の「数＋１メートル」を「数１
０ナノメートル」に訂正する。 ６）　Ｆ！Ａｌｌ書第５頁１７行目の「工冨チング」を
「エツチング」に訂正する。 ７）明細書画６頁１行目の「第１のシリコン窒化膜」を
「第１のシリコン窒化膜」に訂正する。(1st centroid) to (el is a cross-sectional view at each step showing the manufacturing process according to an embodiment of the present invention, FIG. 2 (al, fbl is a cross-sectional view at each step of a conventional general selective oxidation process) 1.8...Cylinder board, 2, 5, 7, 9.1
1...Silicon oxide jX, 3.6. 10・
...Silicon procedure amendment (voluntary) 59,12. -7 Month, Day 1, 1978, Incident Indication 1982 Patent Application No. 16594
No. 9 No. 2, Title of the invention: Method for manufacturing semiconductor devices 3, Relationship with the amended case Applicant: 5-33-1-4, Shiba 5-chome, Minato-ku, Tokyo, Agent: 5-37 Shiba, Minato-ku, Tokyo 108 No. 8, Sumitomo Sanda Building, NEC Co., Ltd., 5, “Detailed Description of the Invention” column 6 of the specification to be amended, Contents of the amendment 1) “As a method and buffer film” on page 2, line 13 of the specification tube. ,”
should be corrected to "as a method or buffer membrane." 2) On page 3 of the specification tube, line 2, “When removing the nitride film,
” to be deleted. 3) In the 47th line of the 8A detailed oath, change the number 10 + IJ to the number 10
Corrected to "Nano". 4) Change “10+1 meter” on page 4, line 20 of the specification to “
Corrected to 10 nanometers. 5) Change “number + 1 meter” on page 5, line 7 of the specification to “number 1
Corrected to 0 nanometers. 6) F! On page 5, line 17 of the All Book, "Kufu-ching" is corrected to "etching". 7) Correct "first silicon nitride film" in the first line of page 6 of the specification to "first silicon nitride film."

Claims (1)

【特許請求の範囲】[Claims] 半導体装置の製造工程において、シリコン基板上に緩衝
用の第１の酸化膜を介して第１の窒化膜を形成し、該第
１の窒化膜および第１の酸化膜の一部をホトエッチング
により除去し、素子間分離領域のパターニングをする第
１の工程と、前記第１の酸化膜をサイドエッチングする
第２の工程と、前記第２の工程の後、直接或いは第１の
酸化膜よりさらに薄い第２の酸化膜を成長させてから、
第２の窒化膜を形成する第３の工程と、前記第１の窒化
膜をマスクとして前記第２の窒化膜をエッチングして、
前記第１の酸化膜をサイドエッチングした領域に、前記
第２の窒化膜を選択的に残す第４の工程と、前記第４の
工程後、直接或いは表出している前記第２の酸化膜を除
去してから、前記素子間分離領域を選択的に酸化する第
５の工程とを含むことを特徴とする半導体装置の製造方
法。In the manufacturing process of a semiconductor device, a first nitride film is formed on a silicon substrate via a first oxide film for buffering, and a part of the first nitride film and the first oxide film are photoetched. a first step of removing and patterning an inter-element isolation region; a second step of side etching the first oxide film; and after the second step, directly or further from the first oxide film. After growing a thin second oxide film,
a third step of forming a second nitride film; etching the second nitride film using the first nitride film as a mask;
a fourth step of selectively leaving the second nitride film in a region where the first oxide film is side-etched; a fifth step of selectively oxidizing the inter-element isolation region after removing the inter-element isolation region.
JP16594984A 1984-08-08 1984-08-08 Manufacture of semiconductor device Pending JPS6144442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16594984A JPS6144442A (en) 1984-08-08 1984-08-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16594984A JPS6144442A (en) 1984-08-08 1984-08-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6144442A true JPS6144442A (en) 1986-03-04

Family

ID=15822074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16594984A Pending JPS6144442A (en) 1984-08-08 1984-08-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6144442A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6213047A (en) * 1985-07-10 1987-01-21 Matsushita Electronics Corp Manufacture of semiconductor device
JPS62216246A (en) * 1986-03-17 1987-09-22 Nippon Texas Instr Kk Manufacture of semiconductor device
JPS63136548A (en) * 1986-11-27 1988-06-08 Toshiba Corp Manufacture of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6213047A (en) * 1985-07-10 1987-01-21 Matsushita Electronics Corp Manufacture of semiconductor device
JPS62216246A (en) * 1986-03-17 1987-09-22 Nippon Texas Instr Kk Manufacture of semiconductor device
JPS63136548A (en) * 1986-11-27 1988-06-08 Toshiba Corp Manufacture of semiconductor device
JPH0338733B2 (en) * 1986-11-27 1991-06-11 Tokyo Shibaura Electric Co

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