JPS6143441A - Testing process of semiconductor device - Google Patents
Testing process of semiconductor deviceInfo
- Publication number
- JPS6143441A JPS6143441A JP59166709A JP16670984A JPS6143441A JP S6143441 A JPS6143441 A JP S6143441A JP 59166709 A JP59166709 A JP 59166709A JP 16670984 A JP16670984 A JP 16670984A JP S6143441 A JPS6143441 A JP S6143441A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- wafer
- circuit element
- parallel
- abnormal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、クエハ状態での多数個同時測定（以下バラ
レルウェハテストという）を可能にし定半導体装置のテ
スト方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for testing fixed semiconductor devices that enables simultaneous measurement of multiple wafers in a wafer state (hereinafter referred to as parallel wafer testing).
従来のバラレルウェハテス）Ｙ第１図に示す。 Conventional parallel wafer tes) Y is shown in FIG.
第１図（ａ）はウェハ１の平面図であり、同図（ｂｌは
第１図（ａ）のＡ−Ａｉによる部分拡大断面図である。FIG. 1(a) is a plan view of the wafer 1, and FIG. 1(a) is a partially enlarged sectional view taken along line A-Ai in FIG. 1(a).
第１図において、１はクエハ、２はＰ型基板、３はＮ凰
拡散層、４はシリコン酸化膜、５はフルミニワム配線層
、６ａ、６ｂ、６ｃ（以下総称するときは６という。他
の符号についても同様とする。ンは第１番目の集積回路
素子の測定用固定プローブ、７ａ、７ｂ、７ｃは第２番
目の集積回路素子の測定用固定プローグ、９ａ、ａｂ、
８ｃは第３番目の集積回路素子の測定用固定グローブ、
９ｍ＋ ９ｂｅ ９ｃは第４番目の集積回路素子の
測定用固定プローブである。第１図（ｂ）は前記各測定
用固定プローグ６〜９とワエ・−１との構成乞原理的忙
示したもので、各測定用固定グローブ６〜９は各３ビン
のみを示している。実際の集積回路層を組合わせること
Ｋより集積回路素子′ｌ！！：構成している。In FIG. 1, 1 is a wafer, 2 is a P-type substrate, 3 is an N-type diffusion layer, 4 is a silicon oxide film, 5 is a full mini-wiring layer, 6a, 6b, 6c (hereinafter collectively referred to as 6. Other The same applies to the symbols.N is a fixed probe for measuring the first integrated circuit element, 7a, 7b, 7c is a fixed probe for measuring the second integrated circuit element, 9a, ab,
8c is a fixed glove for measuring the third integrated circuit element;
9m+9be 9c is a fixed probe for measuring the fourth integrated circuit element. FIG. 1(b) shows the basic configuration of each of the fixed measurement probes 6 to 9 and the wafer-1, and each of the measurement fixed probes 6 to 9 shows only three bottles each. . By combining the actual integrated circuit layers, the integrated circuit element'l! ! : Configured.
次にテストの操作について説明する。Next, the test operation will be explained.
−、ｌｌＫ集積回路素子の１個測定時には測定用固定プ
ローグは単独で接触するだ−げであるが、第１図（ｂ）
のよ５に４個の集積回路素子の測定時には各測定用固定
プローグ６〜９が同時に接触することになる。When measuring a single integrated circuit element, the fixed probe for measurement seems to come into contact alone, as shown in Figure 1(b).
When measuring four integrated circuit devices, each of the fixed measuring probes 6 to 9 comes into contact at the same time.
第１図においては、Ｐ型基板２に負方向の電圧を加え、
各測定用固定プローグ６〜９に正方向の電圧または負方
向の電圧またはＧＮＤＮペンの電圧を加えることにより
、集積回路素子のパラレルクエハテストが行われる。し
たがって、パランルウェハテストの時は、第１番目の集
積回路素子の測定用固定プローグ６ａがアルミニワム配
線層５を経由し、Ｐ型基板２忙電気的に導通していると
、Ｐ型基板２に加えらｎている負方向の電圧が第１番目
の集積回路素子の測定固定プローグ６ａＫ加えらｎてい
る電圧により変化するため、各測定用固定プローグＴ〜
９で測定しているウェハ１のうち入部のある周辺部分の
集積回路素子の測定が正常に行わｎないことがある。In FIG. 1, a negative voltage is applied to the P-type substrate 2,
By applying a positive voltage, a negative voltage, or a GNDN pen voltage to each of the measurement fixed probes 6 to 9, a parallel QF test of the integrated circuit device is performed. Therefore, during the parallel wafer test, if the measurement fixed probe 6a of the first integrated circuit element is electrically connected to the P-type substrate 2 via the aluminum wiring layer 5, the P-type substrate 2 Since the negative voltage applied to the first integrated circuit element varies depending on the voltage applied to the measurement fixed prong 6aK, each measurement fixed prog T~
In some cases, the measurement of the integrated circuit elements in the peripheral area of the wafer 1 where the inlet is measured in step 9 may not be carried out properly.
従来のパラレルウェハテストは前記のような方法で行わ
ｎるため、フェノ・周辺忙近い集積回路素子忙おいて「
良品」と判定さｎるべき集積回路素子ン「不良品」と誤
判定する可能性がある欠点がある。Conventional parallel wafer testing is performed using the method described above, so it is possible to
There is a drawback that an integrated circuit element that should be determined to be a "good product" may be erroneously determined to be a "defective product."
〔発明の概要〕
この発明は、上記のような従来のものの欠点？除去する
定めＫなさｒたもので、クエへ周辺でのパラレルウェハ
テストが測定可能なように、クエへ周辺の異常集積回路
素子の表面乞絶縁膜で覆ってからテストｖ行うよう忙し
たものである。以下、この発明を図面忙ついて説明する
。[Summary of the invention] Does this invention have any drawbacks of the conventional products as described above? There was no plan to remove the wafer, so in order to be able to perform parallel wafer tests around the wafer, I was busy covering the surface of the abnormal integrated circuit elements around the wafer with an insulating film before conducting the test. be. This invention will be explained below with reference to the drawings.
第２図はこの発明の一実施例で、第２図（ａ）はこの発
明のウェハ１１の平面図、第２図（ｂ）は同図（ａ）の
Ｂ−Ｂ＠による部分拡大図である。FIG. 2 shows an embodiment of the present invention. FIG. 2(a) is a plan view of a wafer 11 of the present invention, and FIG. 2(b) is a partially enlarged view taken along line B-B@ of FIG. 2(a). be.
第２図（ａ）、（ｂ） において、１１はウェハ、１２
はガラスコート膜を示している。In FIGS. 2(a) and (b), 11 is a wafer, 12
indicates a glass coated film.
第２図（ａ）、 （ｂ）のように、ウェハ１１周辺の異
常集積回路素子の表面？、ガラスコート膜１２で覆５こ
と忙より、第１番目の集積回路素子の測定用固定プロー
ブ６ａをアルミニワム配線層５より電気的ＫＰＪ縁して
いる。したがって、バラレルヮなくなるためフェノへ１
１周辺でのパラレルフェノ−テストが正常忙行わｎるこ
とＫなる。As shown in FIGS. 2(a) and 2(b), is the surface of the abnormal integrated circuit elements around the wafer 11? , the fixed probe 6 a for measurement of the first integrated circuit element is covered with a glass coat film 12 , and the electrical KPJ is connected to the aluminum wiring layer 5 . Therefore, in order to lose the balance, go to Feno1.
Parallel phenol tests around 1 were performed normally.
また、フェノ〜１１の周辺の異常集積回路素子の表面ｔ
ガラスコート膜１２で覆うことはガラスフートエツチン
グ用マスクの変更により容易にできる。In addition, the surface t of the abnormal integrated circuit element around Pheno~11
Covering with the glass coat film 12 can be easily done by changing the glass foot etching mask.
なお、上記実施例では、ガラスフート膜１２Ｙ用いたが
、ナイトライドフート膜などの電気的絶縁物でもよい。In the above embodiment, the glass foot film 12Y is used, but an electrical insulator such as a nitride foot film may be used.
また、Ｐ型基板２とＮ型拡散層３はＮ型基板とＰ型拡散
層でもよい。Further, the P type substrate 2 and the N type diffusion layer 3 may be an N type substrate and a P type diffusion layer.
以上説明したよ５Ｋ、この発明は、クエ・・周辺の異状
集積回路素子の表面を絶縁膜で覆うこと忙よりパラレル
ワエノ翫テスト時のフェノ−周辺の異常集積回路素子と
プルーグとＹ！電気的絶縁したので、ウェハ周辺部のパ
ラレルフェノ１テストの際の誤測定による集積回路素子
の損失ｔなく丁ことができる。また、バラレルワエノー
テストを行うことにより、集積回路素子１（ｌｌｉｌｖ
測定する場合よりもテスト費用を安価にできる利点があ
る。As explained above, this invention is based on covering the surface of abnormal integrated circuit elements in the surrounding area with an insulating film. Since it is electrically insulated, it is possible to remove the integrated circuit elements without loss due to erroneous measurements during parallel phenol testing of the periphery of the wafer. In addition, by performing a parallel test, the integrated circuit element 1 (llilv
It has the advantage that testing costs can be lower than when measuring.
第１図（ａ）、 （ｂ）は従来のパラレルウェハテスト
の構成図で、同図（ａ）はフェノへの平面図、同図（ｂ
）は同図（ａ）ＶＣおけるＡ−Ａ線による部分拡大断面
図、第２図（ａ）、 （ｂ）はこの発明の一実施例によ
るバラレルワエ／Ｓテストの構成図で、同図（ａ）＋！
この発明のフェノ−の平面図、同図（ｂ）は同図（ａ）
ＫおけるＢ−Ｂ線による部分拡大断面図である。
図中、２はＰ型基板、３はＮ型拡散層、４はシリコン酸
化膜、５はアルミニワム配線層、６（６ａ。
６ｂ、６ｃ）は第１番目の集積回路素子の測定用固定プ
ローグ、７ （７ａｌ ７ ｂ＋ ７ ｃ ）は第
２番目の集積回路素子の測定用固定プローグ、８（８ａ
。
８ｂ、８ｃ）は第°３番目の集積回路素子の測定用固定
プローグ、９（９ａ、９ｂ、９ｃ ）ｉ２第４番目の集
積回路素子の測定用固定プローグ、１１はクエハ、１２
はガラスコート膜である。
なお、図中の同一符号は同一または相当部分を示す。
代理人 大君 増雄 （外２名ン
ぐｒ
第１図
（ａ）Figures 1(a) and 1(b) are configuration diagrams of a conventional parallel wafer test.
) is a partial enlarged cross-sectional view taken along the line A-A in the VC in FIG. )+!
A plan view of the phenol of this invention, the same figure (b) is the same figure (a)
FIG. 3 is a partially enlarged cross-sectional view taken along line B-B at K. In the figure, 2 is a P-type substrate, 3 is an N-type diffusion layer, 4 is a silicon oxide film, 5 is an aluminum wiring layer, 6 (6a, 6b, 6c) is a fixed probe for measuring the first integrated circuit element, 7 (7al 7 b + 7 c) is a fixed probe for measuring the second integrated circuit element, 8 (8a
. 8b, 8c) are fixed probes for measurement of the third integrated circuit element; 9 (9a, 9b, 9c) i2 are fixed probes for measurement of the fourth integrated circuit element; 11 are quaternary probes; 12
is a glass coated film. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Ookimi (2 others) Figure 1 (a)
Claims (1)
プローブを用いて同時にテストする半導体装置のテスト
方法において、前記ウェハ周辺の異常集積回路素子の表
面を絶縁膜で覆つた後、テストを行うことを特徴とする
半導体装置のテスト方法。In a method for testing a semiconductor device in which a large number of integrated circuit elements are simultaneously tested in a wafer state using probes that contact each of them, the test is performed after covering the surface of the abnormal integrated circuit element around the wafer with an insulating film. Characteristic testing method for semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59166709A JPS6143441A (en) | 1984-08-07 | 1984-08-07 | Testing process of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59166709A JPS6143441A (en) | 1984-08-07 | 1984-08-07 | Testing process of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6143441A true JPS6143441A (en) | 1986-03-03 |
| JPH0262947B2 JPH0262947B2 (en) | 1990-12-27 |
Family
ID=15836304
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59166709A Granted JPS6143441A (en) | 1984-08-07 | 1984-08-07 | Testing process of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6143441A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015141985A (en) * | 2014-01-28 | 2015-08-03 | 株式会社東芝 | Inspection apparatus and inspection method |
| JP2016025250A (en) * | 2014-07-22 | 2016-02-08 | トヨタ自動車株式会社 | Method of manufacturing semiconductor device |
-
1984
- 1984-08-07 JP JP59166709A patent/JPS6143441A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015141985A (en) * | 2014-01-28 | 2015-08-03 | 株式会社東芝 | Inspection apparatus and inspection method |
| US10060967B2 (en) | 2014-01-28 | 2018-08-28 | Toshiba Memory Corporation | Testing apparatus and method for testing semiconductor chips |
| JP2016025250A (en) * | 2014-07-22 | 2016-02-08 | トヨタ自動車株式会社 | Method of manufacturing semiconductor device |
| US9633901B2 (en) | 2014-07-22 | 2017-04-25 | Toyota Jidosha Kabushiki Kaisha | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0262947B2 (en) | 1990-12-27 |
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