JPS6142846U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS6142846U
JPS6142846U JP1985101139U JP10113985U JPS6142846U JP S6142846 U JPS6142846 U JP S6142846U JP 1985101139 U JP1985101139 U JP 1985101139U JP 10113985 U JP10113985 U JP 10113985U JP S6142846 U JPS6142846 U JP S6142846U
Authority
JP
Japan
Prior art keywords
stage
lead
base body
aluminum layer
lid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985101139U
Other languages
Japanese (ja)
Inventor
禎一 遠藤
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP1985101139U priority Critical patent/JPS6142846U/en
Publication of JPS6142846U publication Critical patent/JPS6142846U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図ａ１第１図ｂは連接リードフレームの成形工程を
示すためのリードフレームの平面図、第２図ａ乃至第２
図Ｃは本考案による製造工程及び本考案一実施例の半導
体装置を示す説明図、第３図は最終工程前のリードフレ
ームの斜視図、第４図は本考案に係る半導体装置の斜視
図である。 １・・・リードフレーム用板、１ ａ， １ ｂ，
”・，ｎ・・・リードフレーム、２・・・鉄一ニッケル
合金板、３・・・アルミニウム層、４・・・グイステー
ジ、５・・・ボンデイングフィンガー、６・・・半導体
チップ、７，１１・・・低融点ガラス、８・・・アルミ
ニウム線、９・・・ベース、１０−・・キャップ、１５
ａ，１５ｂ， ・・・，１５ｎ・・・半導体装置。Figures 1a and 1b are plan views of the lead frame to show the process of forming the connected lead frame, and Figures 2a to 2
Figure C is an explanatory diagram showing the manufacturing process according to the present invention and a semiconductor device according to an embodiment of the present invention, Figure 3 is a perspective view of a lead frame before the final process, and Figure 4 is a perspective view of a semiconductor device according to the present invention. be. 1... Lead frame plate, 1 a, 1 b,
"・,n...Lead frame, 2...Iron-nickel alloy plate, 3...Aluminum layer, 4...Gui stage, 5...Bonding finger, 6...Semiconductor chip, 7, 11...Low melting point glass, 8...Aluminum wire, 9...Base, 10-...Cap, 15
a, 15b, ..., 15n... semiconductor device.

Claims (1)

【実用新案登録請求の範囲】 セラミックからなる基体及び蓋と、 該基体上に設けられたグイステージと、 該基体上であって該ダイステージの周縁に設けられたリ
ードとを有し、 前記グイステージ表面及び前記リードのボンデイング領
域表面にアルミニウム層が被着されており、 前記グイステージ表面のアルミニウム層上に半導体チッ
プが第１の低融点ガラスによって固着され、 該半導体チップと前記リードのボンデイング領域がアル
ミニウムのボンデイングワイヤで電気的に接続され、 前記リードが前記基体と蓋によって挾まれ、且つ前記基
板と蓋が第２の低融点ガラスによつそ接着されてなるこ
とを特徴とする半導体装置。[Claims for Utility Model Registration] A base body and a lid made of ceramic, a die stage provided on the base body, and a lead provided on the base body at the periphery of the die stage; An aluminum layer is deposited on the surface of the stage and the surface of the bonding region of the lead, a semiconductor chip is fixed on the aluminum layer on the surface of the stage with a first low melting point glass, and the bonding region of the semiconductor chip and the lead is bonded to the aluminum layer on the surface of the stage. are electrically connected to each other by an aluminum bonding wire, the leads are sandwiched between the base and the lid, and the substrate and the lid are adhered to a second low melting point glass. .
JP1985101139U 1985-07-04 1985-07-04 semiconductor equipment Pending JPS6142846U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985101139U JPS6142846U (en) 1985-07-04 1985-07-04 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985101139U JPS6142846U (en) 1985-07-04 1985-07-04 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS6142846U true JPS6142846U (en) 1986-03-19

Family

ID=30660580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985101139U Pending JPS6142846U (en) 1985-07-04 1985-07-04 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS6142846U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0235451U (en) * 1988-08-29 1990-03-07

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4936776A (en) * 1972-08-10 1974-04-05
JPS502232A (en) * 1973-04-30 1975-01-10
JPS503090U (en) * 1973-05-09 1975-01-13

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4936776A (en) * 1972-08-10 1974-04-05
JPS502232A (en) * 1973-04-30 1975-01-10
JPS503090U (en) * 1973-05-09 1975-01-13

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0235451U (en) * 1988-08-29 1990-03-07

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