JPS6142796A - Memory device - Google Patents
Memory deviceInfo
- Publication number
- JPS6142796A JPS6142796A JP59164388A JP16438884A JPS6142796A JP S6142796 A JPS6142796 A JP S6142796A JP 59164388 A JP59164388 A JP 59164388A JP 16438884 A JP16438884 A JP 16438884A JP S6142796 A JPS6142796 A JP S6142796A
- Authority
- JP
- Japan
- Prior art keywords
- storage
- refresh
- control part
- control unit
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は一定周期で記憶内容のリフレッシュ（ｒｅｆ
ｒｅｓｈ） ｆ必要とするダイナミックメモリ素子を使
用した記憶装置に関し、特に停電時における記憶内容の
保持に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] This invention refreshes (ref) memory contents at regular intervals.
This invention relates to a storage device using a dynamic memory element that requires resh) f, and in particular to retention of stored contents during a power outage.
従来この狸の装置として第１図に示すものがあった。図
において、＋Ｉ＋はダイナミックメモリ素子で（１ｑ成
された記憶部、（２）は記憶部全制御する記憶制御部、
（３１は記憶制御部（２）内に含まれ、ダイナミックメ
モリ素子を定期的にリフレッシュするリフレッシュ制御
部である。＋４１ 、 ［５１はそれぞれ信号を表し、
たとえば信号（４１は書込み／読出しの制御信号、アド
レス信号、データ信号から構成され、信号１５＋はリフ
レッシュのため順次変化するアドレス信号から構成され
る。Conventionally, there was a device for this raccoon dog as shown in Fig. 1. In the figure, +I+ is a dynamic memory element (1q storage unit), (2) is a storage control unit that controls all storage units,
(31 is a refresh control unit that is included in the storage control unit (2) and periodically refreshes the dynamic memory element. +41 and [51 each represent a signal;
For example, the signal (41) is composed of a write/read control signal, an address signal, and a data signal, and the signal 15+ is composed of an address signal that changes sequentially for refreshing.
ダイナミックメモリ素子では電荷によって情報を記憶し
ているので、時間と共にこの電荷が自然放電して記憶し
た情報が漸次不鮮明にな、るので、定期的に再充電しな
ければならない。この再充電は記憶装置＋１１内の任意
のアドレスからデータを読出しこの読出したデータをそ
のアドレスへ書込むことによって行われ、アドレスを順
次変化して行って、記憶装置（１１内のすべてのデータ
に対して再充電を行うことができる。このような動作全
リフレッシュと言い、この製作はリフレッシュ制御部（
３）によシ行われる。Since dynamic memory devices store information using electric charges, the electric charges naturally discharge over time and the stored information gradually becomes unclear, so they must be periodically recharged. This recharging is performed by reading data from an arbitrary address in the storage device +11 and writing the read data to that address. This type of operation is called a full refresh, and this production is performed by the refresh control unit (
3) It is carried out accordingly.
リフレッシュ制御部（３）を除く記憶制御部（２）では
記憶部［１１のアドレスを指定してそのアドレスに新し
いデータを誓込み、又はそのアドレスのデータを読出す
。The storage control unit (2) excluding the refresh control unit (3) specifies the address of the storage unit [11] and inserts new data into the address or reads data at the address.
したがって信号（４）に含まれるアドレス信号と信号（
５１に含まれるアドレス信号とは記憶制御部（２１内の
アドレスカウンタによって共通に生成される場合もちυ
、また、信号（４）によって記憶部（１）へアクセスし
ている間は信号［５１によってリフレッシュ全行わない
よう記憶制御部（２１内で制御する。Therefore, the address signal included in signal (4) and the signal (
The address signal included in 51 is the memory control unit (if it is commonly generated by the address counter in 21, υ
Also, while the storage unit (1) is being accessed using the signal (4), the storage control unit (21) controls the memory controller (21) so that the refresh is not performed at all using the signal [51].
停電時に、記憶部（υの記憶内容が消されないようにす
るためには、記憶部ｉｌ＋と記憶制御部（２）とへ電池
電源を供給し、周期的なリフレッシュの実行を継続しな
けれはならない。In order to prevent the memory contents of the storage unit (υ) from being erased during a power outage, it is necessary to supply battery power to the storage unit il+ and the storage control unit (2), and to continue performing periodic refreshes. .
従来の装置は以上のように構成されており、記憶ｆｌｕ
ｆｆ （１１１１部（２）には高速化のため仄Ｌ （ｅ
ｍｉｔｔ ｅｒｃｏｕｐｌｅｄ ｌｏｇｉｃ ）素子を
使用することもちゃ、これ圧電源供給するための電池電
源が複雑になシ、かつ容量も大きくなるという欠点があ
った。The conventional device is configured as described above, and the memory flu
ff (1111 part (2) has 仄L (e
However, the use of Mitt ercoupled logic (Mitt ercoupled logic) elements has the disadvantage that the battery power supply for supplying the voltage power is complicated and the capacity is also large.
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、この発明では記憶制御部とは別に
リフレッシュ制御部を設け、停電時には記憶部とリフレ
ッシュ制御部とにだけ電池電源を供給するようにして、
電源供給の設計を簡単にし、電池′［電源の消費を少な
くしたものである。This invention was made in order to eliminate the drawbacks of the conventional ones as described above.In this invention, a refresh control section is provided separately from the storage control section, and in the event of a power outage, battery power is supplied only to the storage section and the refresh control section. as if to supply;
It simplifies the power supply design and reduces battery consumption.
以下この発明の実施例を図面について説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第２図はこの発ＩＪＩＪの一実施例金示すブロック図で
。Figure 2 is a block diagram showing one embodiment of this IJIJ.
第１図と同一符号は同−又は相当部分を示し、（２ａ）
はリフレッシュ制御部を含まない記憶制御部、（３ａ）
は記憶制御部とは別に設けられたリフレッシュ制御部、
＋６１ Ｖｉ競合制御部、（７）はリフレッシュ要求信
号である。The same symbols as in Figure 1 indicate the same or equivalent parts, (2a)
is a storage control unit that does not include a refresh control unit, (3a)
is a refresh control unit provided separately from the storage control unit,
+61 Vi contention control unit, (7) is a refresh request signal.
リフレッシュ制御部（３＆）は記憶制御部（２ａ）から
分離して設けられているためリフレッシュ制御のために
必要なすべての機能を備えていなければならない。すな
わち、たとえば、信号（５）として送出する順次変化す
るアドレス信号を生成するためのアドレスカウンタ（こ
の明細書ではこのアドレスカウンタをリフレッシュカウ
ンタという）及びこのリフレッシュカウンタに入力する
クロックパルスを発生するクロック発振器はリフレッシ
ュ制御部（３ａ）に内蔵される。Since the refresh control section (3&) is provided separately from the storage control section (2a), it must have all the functions necessary for refresh control. That is, for example, an address counter (in this specification, this address counter is referred to as a refresh counter) for generating a sequentially changing address signal to be sent out as signal (5), and a clock oscillator that generates a clock pulse to be input to this refresh counter. is built in the refresh control section (3a).
競合制御部（６）はリフレッシュ制御部（３ａ）から記
憶部（１）へのアクセス安来信号であるリフレッシュ要
求信号（７）ヲ受けて、記憶制御部（２ａ）からのアク
セス要求との間の競合全制御し、優先すべきアクセス要
求に対し許可を与える。The contention control unit (6) receives a refresh request signal (7) which is an access signal from the refresh control unit (3a) to the storage unit (1), and performs a conflict between the refresh request signal (7) and the access request from the storage control unit (2a). Fully control contention and grant permission to priority access requests.
停電時の′１池′亀源は記憶部（１）とリフレッシュ制
御部（３ａ）だけに供給され、かつ競合制御部；６）は
機能を停止し、リフレッシュ制御部（３ａ）が随時記憶
部（１）にアクセスできるように接続される。At the time of a power outage, the '1 pond' source is supplied only to the storage unit (1) and the refresh control unit (3a), and the contention control unit (6) stops functioning, and the refresh control unit (3a) is supplied to the storage unit (3a) at any time. (1) is connected so that it can be accessed.
以上のようにこの発明によれば、停′亀時には記憶部と
リフレッシュ制御部だけに電池電源を供給するようにし
たので、電源回路が簡単になり、電池電源の消費を抑制
することができる。As described above, according to the present invention, battery power is supplied only to the storage section and the refresh control section during a power outage, so the power supply circuit can be simplified and the consumption of battery power can be suppressed.
第１図は従来の装置を示すブロック図、第２図はこの発
明の一実施例を示すブロック図である。
■・・・記憶部、（２ａ）・・・記憶制御部、（３ａ）
・・・リフレッシュ制御部、（６）・・・競合制御部。
尚、各図中同一符号は同−又は相当部分を示す。FIG. 1 is a block diagram showing a conventional device, and FIG. 2 is a block diagram showing an embodiment of the present invention. ■...Storage unit, (2a)...Storage control unit, (3a)
...Refresh control section, (6)...Conflict control section. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
ナミックメモリ素子を使用した記憶部、この記憶部に対
する情報の書込み及び読出しを制御する記憶制御部、 この記憶制御部とは別に設けられ、リフレッシュカウン
タと、このリフレッシュカウンタを駆動するクロック発
振器を内蔵して、上記記憶部の上記リフレッシュを実行
するリフレッシュ制御部、このリフレッシュ制御部から
上記記憶部に対するアクセス要求と上記記憶制御部から
上記記憶部に対するアクセス要求とを受けて、その競合
を制御する競合制御部、 停電時には上記記憶部及び上記リフレッシュ制御部へだ
け電池電源を供給し、かつ上記競合制御部の制御を停止
し上記リフレッシュ制御部から上記憶部へ随時アクセス
できるよう接続する手段を備えた記憶装置。[Scope of Claims] A storage section using a dynamic memory element that requires refreshment of storage contents at a constant cycle, a storage control section that controls writing and reading of information to and from this storage section, and a storage section provided separately from the storage control section. a refresh control unit that includes a refresh counter and a clock oscillator that drives the refresh counter and executes the refresh of the storage unit; an access request from the refresh control unit to the storage unit; a contention control unit that receives an access request to the storage unit and controls the contention thereof, and in the event of a power outage, supplies battery power only to the storage unit and the refresh control unit, stops control of the contention control unit, and performs the refresh control. A storage device equipped with a means for connecting the storage section to the upper storage section so that the upper storage section can be accessed at any time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59164388A JPS6142796A (en) | 1984-08-06 | 1984-08-06 | Memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59164388A JPS6142796A (en) | 1984-08-06 | 1984-08-06 | Memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6142796A true JPS6142796A (en) | 1986-03-01 |
Family
ID=15792172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59164388A Pending JPS6142796A (en) | 1984-08-06 | 1984-08-06 | Memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6142796A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009055055A (en) * | 2002-12-27 | 2009-03-12 | Kyushu Hitachi Maxell Ltd | Method of manufacturing semiconductor device |
| JP2009259210A (en) * | 2007-12-27 | 2009-11-05 | Huawei Technologies Co Ltd | Method, apparatus, logic device and storage system for power-fail protection |
-
1984
- 1984-08-06 JP JP59164388A patent/JPS6142796A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009055055A (en) * | 2002-12-27 | 2009-03-12 | Kyushu Hitachi Maxell Ltd | Method of manufacturing semiconductor device |
| JP2009259210A (en) * | 2007-12-27 | 2009-11-05 | Huawei Technologies Co Ltd | Method, apparatus, logic device and storage system for power-fail protection |
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