JPS6132550A - Semiconductor integerated circuit element - Google Patents
Semiconductor integerated circuit elementInfo
- Publication number
- JPS6132550A JPS6132550A JP15297884A JP15297884A JPS6132550A JP S6132550 A JPS6132550 A JP S6132550A JP 15297884 A JP15297884 A JP 15297884A JP 15297884 A JP15297884 A JP 15297884A JP S6132550 A JPS6132550 A JP S6132550A
- Authority
- JP
- Japan
- Prior art keywords
- coordinates
- defective
- circuit
- integrated circuit
- carved
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 230000002950 deficient Effects 0.000 abstract description 17
- 238000000034 method Methods 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract 1
- 239000000523 sample Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 235000014121 butter Nutrition 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、特に当該素子の不良解析に好適な半導体集積
回路素子の周辺パターンに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a peripheral pattern of a semiconductor integrated circuit element particularly suitable for failure analysis of the element.
近年半導体集積回路の高集積化に伴ない、これに作り込
まれる要素回路数は１００００００を越える集積回路素
子もめずらしくなってきた。とこ１ろが、このような半
導体集積回路素子の不良解析は、当該集積回路素子に存
在する不良要素回路の位置を探し当てることさえ非常に
困難な状況にある。In recent years, as semiconductor integrated circuits have become highly integrated, it has become rare for integrated circuit elements to have more than 1,000,000 element circuits built into them. However, in such failure analysis of semiconductor integrated circuit devices, it is extremely difficult to even locate the defective element circuits present in the integrated circuit device.
たとえば、２５６キロビツトのメモリ素子でｔＬテスタ
によって不良メモリセルの番地がわかったとしても、メ
モリセルの配列が５１２行×５１２列もあり、これを顕
微鏡下で数えた場合、長時間を要し、かつまちがえやす
い。For example, even if a tL tester were used to find the address of a defective memory cell in a 256 kilobit memory device, the memory cells are arranged in 512 rows by 512 columns, and it would take a long time to count them under a microscope. It's also easy to make mistakes.
これに対し、メモリセルの配列をいくつかの小配列ブロ
ックに分け、当該ブロック相互をある隔間に保つ配置に
することで、数えまちがいがなく、短時間で不良メモリ
セルを探し当てるこ″とができるという素子がある。In contrast, by dividing the memory cell array into several small array blocks and arranging the blocks to maintain a certain distance from each other, it is possible to detect defective memory cells in a short time without making any mistakes in counting. There is an element of being able to do it.
しかし、このような素子ではメモリセルの小配列ブロッ
ク間に設けた隔間の部分の面積が非効率的になり、同一
メモリサイズをもつ素子ではそれだけ素子面積が増加す
る。このことは。However, in such a device, the area of the space provided between the small array blocks of memory cells becomes inefficient, and the device area increases accordingly for devices having the same memory size. About this.
同一ウニへ面積から切り出せる素子数の減少や素子面積
の増加に伴なう歩留り低下による生産性の低減を招来す
る。This leads to a decrease in productivity due to a decrease in the number of elements that can be cut out from the same area and a decrease in yield due to an increase in the element area.
また１以上述べた従来の方法では要素回路が規則的に配
列されているメモリ素子以外のロジック素子等圧は適用
できないという問題点があった。Furthermore, the above-mentioned conventional methods have the problem that equal voltage cannot be applied to logic elements other than memory elements in which element circuits are regularly arranged.
本発明の目的は、上記した不都合がなく、容易に要素回
路の位置が探索できる半導体集積回路素子を提供するに
ある。 ・
〔発明の概要〕
この目的を達成するため本発明では、半導体集積回路素
子周辺の要素回路のない部分に要素回路の素子内位置を
示す座標を刻み込む素子構造を用いた。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that does not have the above-mentioned disadvantages and allows easy searching for the position of an element circuit. - [Summary of the Invention] In order to achieve this object, the present invention uses an element structure in which coordinates indicating the position of an element circuit within the element are inscribed in a portion around the semiconductor integrated circuit element where there is no element circuit.
以下、本発明の実施例を第１〜第３図により説明する。 Embodiments of the present invention will be described below with reference to FIGS. 1 to 3.
第１図はメモリ素子のチップ概念図であり、１はチップ
、２はチップ１に作られている要素回路としてのメモリ
セル領域、３はメモリセル以外の要素回路領域、４は要
素回路の素子内位置を示す座標である。また、第２．第
６図は第１図の拡大図であり、５は不良要素回路を包含
する不良像域である。FIG. 1 is a conceptual diagram of a memory element chip, where 1 is a chip, 2 is a memory cell area as an element circuit made on the chip 1, 3 is an element circuit area other than memory cells, and 4 is an element circuit element. These are coordinates indicating the internal position. Also, the second. FIG. 6 is an enlarged view of FIG. 1, and 5 is a defective image area including the defective element circuit.
第１図に示すように、チップ１の要素回路のない周辺領
域に座標４を刻んでおく。座標４は集積回路を顕微鏡等
で見たとき鮮明な線として見えるものならどんな方法で
刻んでもよいが。As shown in FIG. 1, coordinates 4 are carved in the peripheral area of chip 1 where there are no element circuits. Coordinate 4 may be carved by any method that makes it visible as a clear line when the integrated circuit is viewed through a microscope or the like.
本実施例では、分解解析の際のエッチラグでも消えにく
いアイソレージ目ン拡散で座標を刻んだ。座標の刻み方
は、第２図の拡大図に示す如く要素回路の配列に対応し
た座標を用いる刻み方と、第３図の拡大図に示す如く、
不良要素口−を包含する不良領域を示すような座標を用
いる刻み方がある。In this example, the coordinates were carved using isolation diffusion, which is difficult to erase even with the etch lag during decomposition analysis. The coordinates can be carved using coordinates corresponding to the arrangement of the element circuits, as shown in the enlarged view of Fig. 2, or as shown in the enlarged view of Fig. 3.
There is a method of marking using coordinates that indicate the defective area including the defective element opening.
前者はメモリ素子等、要素回路が規則的に配列されてい
るものに適し、後者はロジック素子環、要素回路の配置
に規則性が見られないものに適する。The former is suitable for devices such as memory devices in which element circuits are regularly arranged, and the latter is suitable for logic element rings and devices in which there is no regularity in the arrangement of element circuits.
顕微鏡を用いた不良素子の解析の際、これらの座標４は
不良素子回路探索に大いに役立つ。When analyzing a defective element using a microscope, these coordinates 4 are very useful for searching for a defective element circuit.
それは、ちょうど地図の周辺に印刷されているインデッ
クスと同じで、メモリ素子の場合、テスタでわかった不
良ビットメモリセルの番地を手掛りに、実素子上の不良
メモリセルを探し当てることに相当する。This is just like the index printed around the map, and in the case of memory devices, it corresponds to locating the defective memory cell on the actual device using the address of the defective bit memory cell found by the tester as a clue.
第２図の実施例で言えば、顕微鏡の接眼レンズにある十
字マークの縦及び横軸を不良メモリセルのＸ及びＹ番地
を示すそれぞれの座標４に合わせるだけで十字マークの
クロス点がそのまま不良メモリセルの位置を示すことに
なる。In the example of FIG. 2, simply by aligning the vertical and horizontal axes of the cross mark on the eyepiece of the microscope with the respective coordinates 4 indicating the X and Y addresses of the defective memory cell, the cross point of the cross mark remains as it is. This will indicate the location of the memory cell.
以上述べたように、本発明による半導体集積回路素子の
不良要素回路探索は、とくにメモリセル配列の行数及び
列数をかぞえる必要がないので、きわめて短時間で探索
でき、かつかぞえまちがいなどによる探索ミスは皆無と
なる。As described above, the search for defective element circuits of semiconductor integrated circuit devices according to the present invention does not require counting the number of rows and columns of the memory cell array, so the search can be performed in an extremely short time, and the search can be performed in a very short time. There will be no mistakes.
なお、座標４の刻み方として、たとえばアルミ蒸着によ
る方法など、アイソレージ目ン拡散以外の方法で刻むこ
とも考えられる。また、座標４のバター／は、第２．第
３図以外の２進化ないし１６進化パターンであってもよ
いし、他の適当なパターンでもよい。Note that the coordinate 4 may be carved by a method other than isolation diffusion, such as by aluminum vapor deposition. Also, the butter/ at coordinate 4 is the second. Binary or hexadecimal patterns other than those shown in FIG. 3 may be used, or other suitable patterns may be used.
第１図は本発明の一実施例のメモリ素子のチッグ概念図
、第２図は第１図の拡大図、第３図は第２図とは異なる
実施例を示す拡大図である。
１・・・・・・チップ、
２・・・・・・メモリセル領域、
４・・・・・・座標、
５・・・・・・不良領域。FIG. 1 is a conceptual diagram of a memory device according to an embodiment of the present invention, FIG. 2 is an enlarged view of FIG. 1, and FIG. 3 is an enlarged view of an embodiment different from FIG. 2. 1... Chip, 2... Memory cell area, 4... Coordinates, 5... Defective area.
Claims (1)
位置を示す座標を設けたことを特徴とする半導体集積回
路素子。1. A semiconductor integrated circuit device characterized in that coordinates indicating the position within the device of an element circuit built into the device are provided around the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15297884A JPS6132550A (en) | 1984-07-25 | 1984-07-25 | Semiconductor integerated circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15297884A JPS6132550A (en) | 1984-07-25 | 1984-07-25 | Semiconductor integerated circuit element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6132550A true JPS6132550A (en) | 1986-02-15 |
Family
ID=15552285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15297884A Pending JPS6132550A (en) | 1984-07-25 | 1984-07-25 | Semiconductor integerated circuit element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6132550A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5633173A (en) * | 1994-07-14 | 1997-05-27 | Hyundai Electronics Industries Co., Ltd. | Method for detecting wafer defects |
-
1984
- 1984-07-25 JP JP15297884A patent/JPS6132550A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5633173A (en) * | 1994-07-14 | 1997-05-27 | Hyundai Electronics Industries Co., Ltd. | Method for detecting wafer defects |
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