JPH09223723A - Method and equipment for analyzing failure of semiconductor device - Google Patents
Method and equipment for analyzing failure of semiconductor deviceInfo
- Publication number
- JPH09223723A JPH09223723A JP2893596A JP2893596A JPH09223723A JP H09223723 A JPH09223723 A JP H09223723A JP 2893596 A JP2893596 A JP 2893596A JP 2893596 A JP2893596 A JP 2893596A JP H09223723 A JPH09223723 A JP H09223723A
- Authority
- JP
- Japan
- Prior art keywords
- coordinates
- observation
- chip
- semiconductor
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の製造
時の不良解析を短期間に効率良く行う方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for efficiently performing defect analysis during manufacturing of a semiconductor device in a short period of time.
【０００２】[0002]
【従来の技術】半導体装置の不良解析は、通常電気特性
の検査，テスタによる検査を基に不良箇所の観察を行い
不良箇所の原因を特定し、その原因を排除するようにウ
ェハ工程の対策を行っている。このような解析技術には
多数の解説書がある。例えば、“ＶＬＳＩプロセス技
術”（日刊工業新聞社，１９９３．６発行）の第６章，
故障解析技術等に詳述されている。2. Description of the Related Art In semiconductor device failure analysis, a defect location is usually observed based on an inspection of electrical characteristics and a tester to identify the cause of the failure location, and measures for the wafer process are taken to eliminate the cause. Is going. There are many manuals on such analysis techniques. For example, Chapter 6 of "VLSI Process Technology" (published by Nikkan Kogyo Shimbun, 1993. 6),
It is described in detail in failure analysis technology and the like.
【０００３】しかし、同書での半導体装置（チップ）の
不良箇所の特定には、エミッション顕微鏡，ＥＢテスタ
等の故障解析用の検査装置によりチップ上の不良位置の
特定を行い、その部分の電子顕微鏡観察を行う方法のみ
の記述であり半導体チップ上の部分の特定方法について
は記述されていない。However, in order to specify the defective portion of the semiconductor device (chip) in the same document, the defective position on the chip is specified by an inspection device for failure analysis such as an emission microscope and an EB tester, and the electron microscope of that portion is specified. Only the method of observing is described, and the method of specifying the portion on the semiconductor chip is not described.
【０００４】半導体チップの全体の観察から不良部分を
特定することはできるが、電子顕微鏡の観察では不良部
分を拡大するため、チップの中の部分拡大が必要にな
る。例えば１０mm角程度のチップの不良部分は１０μｍ
程度であり、その不良部分の位置が、チップの右角の方
向に存在することが判定された程度では、その不良箇所
を電子顕微鏡の視野に入る領域に照準するための操作に
多くの時間を必要とする。Although the defective portion can be specified by observing the entire semiconductor chip, the defective portion is magnified by observation with an electron microscope, so that it is necessary to magnify a portion inside the chip. For example, the defective part of a chip of about 10 mm square is 10 μm
If it is determined that the position of the defective portion is in the direction of the right corner of the chip, it takes a lot of time to perform the operation for aiming the defective portion in the area within the field of view of the electron microscope. And
【０００５】また、半導体装置として動作確認ができる
ウェハ工程の最終まで完成したウェハを用いれば、電気
的な検査によりその半導体チップの不良の有無，不良の
種類（カテゴリ）の情報を取得できる。しかし不良の原
因の解析には、不良カテゴリから不良となっている半導
体の構造に起因した部分を観察するために、完成したウ
ェハの上層から不良原因の該当箇所まで半導体を形成し
ている層（薄膜）をエッチングのような化学的な方法で
除去する。この様に上層の薄膜を除去したチップを観察
する際にも、観察する部分を特定するのに多くの時間を
必要とする。If a wafer that has been completed until the end of the wafer process in which the operation can be confirmed is used as a semiconductor device, information on the presence or absence of a defect and the type (category) of the defect of the semiconductor chip can be obtained by electrical inspection. However, in order to analyze the cause of the defect, in order to observe the portion caused by the defective semiconductor structure from the defect category, the layer forming the semiconductor from the upper layer of the completed wafer to the relevant portion of the defect cause ( The thin film) is removed by a chemical method such as etching. Even when observing the chip from which the upper thin film has been removed, much time is required to specify the portion to be observed.
【０００６】また、検査結果の情報から不良発生位置の
ウェハ上の座標を特定しておき、同様に観察する場合で
もウェハ上には不良の無い良品があるので、ウェハ全体
をエッチングして観察することはなく、不良のあるチッ
プのみを切り出して観察用の試料を作成し、観察する。
このときもウェハ上の座標では切り出したチップの座標
が分らず、観察に多くの時間を要する等の問題があっ
た。Further, even when the coordinates of the defect occurrence position on the wafer are specified from the information of the inspection result, and there is a good product having no defect on the wafer even when similarly observed, the entire wafer is etched and observed. However, only defective chips are cut out to prepare a sample for observation and observed.
Also at this time, there is a problem that the coordinates of the cut-out chip are not known from the coordinates on the wafer, and that much time is required for observation.
【０００７】[0007]
【発明が解決しようとする課題】本発明は、これらの問
題を解決するために、個々のチップ、もしくはウェハの
小片に切り出しても個々の切り出したものの不良発生箇
所のウェハ上の座標を容易に得るために、検査座標と観
察座標の対応を取ることを目的としてなされたものであ
る。SUMMARY OF THE INVENTION In order to solve these problems, the present invention makes it easy to determine the coordinates on the wafer of the defect occurrence points of individual cuts even if they are cut into individual chips or small pieces of wafers. In order to obtain it, the purpose is to establish correspondence between inspection coordinates and observation coordinates.
【０００８】[0008]
【課題を解決するための手段】本発明の上記した課題の
解決手段は、半導体ウェハ上に観察用の目印となるマー
クを付与することである。半導体のウェハは、薄膜の積
層構造からなり、各形成層毎にホトリソグラフィ（以下
ホトと略す）の手法を用いて半導体デバイスのパターン
を形成している。このウェハはホト工程では第２の工程
から下地のパターンに合わせて上層のパターンの位置合
わせを行い、精度良く半導体の立体構造を形成して行
く。この下地との合わせの際にはウェハの上のチップ配
列情報，ウェハの座標情報を用いて下地との合わせ精度
を維持している。本発明はこのホト工程の露光するマス
クパターン上にチップとチップの境界であるチップを切
る際の切取りマーク（スクライブライン）の一部に目印
座標のマークをホト工程で付与できるようにマークを予
めマスクパターン上に用意し、半導体ウェハの形成工程
のホト工程毎にウェハ上に目印座標マークを付与し、該
マークからチップ上の座標を特定し観察することができ
る。A means for solving the above-mentioned problems of the present invention is to provide a mark as an observation mark on a semiconductor wafer. A semiconductor wafer has a laminated structure of thin films, and a pattern of a semiconductor device is formed for each formation layer by using a method of photolithography (hereinafter abbreviated as photo). In this photo process, the upper layer pattern is aligned with the underlying pattern from the second process in the photo process to accurately form a three-dimensional structure of the semiconductor. At the time of alignment with the base, the chip alignment information on the wafer and the coordinate information of the wafer are used to maintain the alignment accuracy with the base. According to the present invention, a mark is preliminarily provided on the mask pattern to be exposed in the photo process so that a mark of a mark coordinate can be added to a part of a cut mark (scribe line) when cutting the chip which is a boundary between chips in the photo process. It is possible to prepare on a mask pattern, provide a mark coordinate mark on the wafer for each photo process of the semiconductor wafer forming process, specify the coordinates on the chip from the mark, and observe.
【０００９】本発明の目印座標マークは、工程毎に付与
するが、下層の工程から上層の工程まで同一の位置にマ
ークすれば座標の変換は目印座標のマークとチップの座
標の管理で良いが、実際には同一のマーク上にいくつも
のマークを重ねて行くとその部分だけ、盛り上がったり
して、上層になればますます高くなり膜剥がれ等の原因
となり半導体の製造には不適当である。The mark coordinate mark of the present invention is provided for each process, but if the mark is marked at the same position from the lower layer process to the upper layer process, the coordinate conversion may be managed by the mark coordinate mark and the chip coordinate. Actually, when several marks are piled up on the same mark, only that part rises, and the upper layer becomes higher and the film peeling is caused, which is unsuitable for semiconductor manufacturing.
【００１０】従って本発明の好ましい実施の形態によれ
ば、目印座標マークの位置をホト工程毎にずらし、その
情報を管理し、観察の際にウェハの上層膜をエッチング
して除去したとき、各層にある目印座標マークを管理し
指示することで、観察したい座標に観察装置を合わせ
る。この観察する際の目印はエッチングした工程でなく
もう一つ下層の工程での目印座標マークを認識し管理す
る方式となる。Therefore, according to a preferred embodiment of the present invention, the position of the mark coordinate mark is shifted for each photo process, the information is managed, and when the upper layer film of the wafer is removed by etching during observation, each layer is removed. The observation device is aligned with the coordinates to be observed by managing and instructing the mark coordinate marks in. The mark at the time of this observation is a method of recognizing and managing the mark coordinate mark in the step of another lower layer instead of the step of etching.
【００１１】[0011]
【発明の実施の形態】本発明の一実施例を図１〜図８に
示す。図１は本発明の装置構成を示し、電気的な検査の
情報は検査データ収集解析の計算機１００に集められ、
ここで不良の観察したい場所を同定する。この観察座標
の情報はネットワークを用いたり又はフロッピーディス
ク等で目印座標管理装置１０１に検査データを送ること
ができる。実体であるウェハは、観察したいチップを切
り出し試料をエッチングする試料エッチング装置１１０
で上層の膜を剥がし観察の準備を行う。このとき切り出
したチップの座標，観察座標の入力装置１０２により、
観察するチップの座標を入力する。DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention is shown in FIGS. FIG. 1 shows an apparatus configuration of the present invention, in which electrical inspection information is collected in a computer 100 for inspection data collection and analysis,
Here, the place where the defect is to be observed is identified. This observation coordinate information can be sent to the marker coordinate management device 101 by using a network or by sending inspection data using a floppy disk or the like. A wafer, which is a substance, is a sample etching apparatus 110 for cutting out a chip to be observed and etching a sample.
The upper layer film is peeled off with to prepare for observation. By the input device 102 of the coordinates of the chip cut out at this time and the observation coordinates,
Enter the coordinates of the chip to be observed.
【００１２】この入力のインターフェースは図２に示す
様なインターフェースで入力する。検査したウェハの情
報２０１は、ウェハ全体の不良の様子を表示している。
ウェハのサイズで表示することで、ウェハ上のどの位置
を観察するか決定できる。ウェハ情報２０１は、半導体
メモリの個々の記憶素子（セル）が正常か否かを示して
いるが、例えば、４メガビットの記憶容量ならば１つの
チップに４百万個の記憶素子があり、計算機のディスプ
レイでは個々の１素子の情報まで表示できない。The input interface is as shown in FIG. The information 201 of the inspected wafer indicates a state of the defect of the entire wafer.
By displaying the size of the wafer, it is possible to determine which position on the wafer to observe. The wafer information 201 indicates whether or not each storage element (cell) of the semiconductor memory is normal. For example, if the storage capacity is 4 megabits, there are 4 million storage elements in one chip, and In the display of, it is not possible to display information for each individual element.
【００１３】そのため拡大図２０２の様に個別チップを
拡大表示し、その部分で観察したい不良の入力を行う。
このとき例えば図２の観察位置入力部２０３の矢印（マ
ウスポインタ）を移動し観察部分を指定する。このとき
拡大したチップはチップ位置入力の２０４（行），２０
５（列）にチップのウェハ上の位置が入力される。Therefore, as shown in the enlarged view 202, the individual chip is enlarged and displayed, and the defect desired to be observed in that portion is input.
At this time, for example, the arrow (mouse pointer) of the observation position input unit 203 in FIG. 2 is moved to specify the observation portion. At this time, the enlarged chip is 204 (rows), 20 of the chip position input.
The position of the chip on the wafer is input in 5 (column).
【００１４】以上のようにして観察座標は目印座標管理
装置１０１に入力される。入力したデータは図３のフロ
ーにより観察チップ座標に変換する。観察座標に合わせ
て目印座標管理装置１０１は、観察の目印となる座標，
目印座標を検索する。As described above, the observation coordinates are input to the mark coordinate management device 101. The input data is converted into observation chip coordinates by the flow of FIG. According to the observation coordinates, the mark coordinate management device 101 uses the coordinates as the observation mark,
Search for landmark coordinates.
【００１５】目印座標は、製造工程のホト工程で作成さ
れる。図５に示すレチクルパターンの目印パターン５０
２によりチップの間のスクライブライン上に形成され
る。レチクルは半導体の製造工程で１０〜５０回程度繰
り返される。そこで、ホト工程毎に目印パターンの位置
を替え目印パターンを形成する。このように形成したパ
ターンは図６の目印パターン５０２〜５０９のようにな
る。このようにして工程毎の目印座標を管理する。The mark coordinates are created in the photo process of the manufacturing process. The reticle pattern mark pattern 50 shown in FIG.
2 is formed on the scribe line between the chips. The reticle is repeated about 10 to 50 times in the semiconductor manufacturing process. Therefore, the position of the mark pattern is changed for each photo process to form the mark pattern. The pattern thus formed is like the mark patterns 502 to 509 in FIG. In this way, the mark coordinates for each process are managed.
【００１６】この管理した座標と不良座標の突き合わせ
を図７に示す。座標管理としてウェハ上のチップ位置を
ウェハのチップ配列を考慮し、チップの原点としてスク
ライブラインのセンタを上下をＹ軸，左右をＸ軸としそ
の交点をチップの原点とする。このようにすることで、
不良の座標と製造工程途中に形成された目印マークを管
理でき、チップを選択した後にチップ内の観察座標を作
成できる。FIG. 7 shows the matching between the managed coordinates and the defective coordinates. For coordinate management, the chip position on the wafer is taken into consideration in consideration of the chip arrangement of the wafer. As the origin of the chip, the center of the scribe line is the upper and lower Y axes and the left and right are the X axes, and the intersection is the origin of the chip. By doing this,
It is possible to manage defective coordinates and mark marks formed during the manufacturing process, and to create observation coordinates within a chip after selecting the chip.
【００１７】作成した観察座標は観察装置１１１に観察
座標として出力される。この出力は、観察装置のレベル
に応じて直接通信で送っても良く、フロッピディスク，
印字リスト等でも構わない。The created observation coordinates are output to the observation device 111 as observation coordinates. This output may be sent by direct communication depending on the level of the observation device.
It may be a print list or the like.
【００１８】観察する際のフローは図４に示した。試料
をエッチングした後、観察する工程を目印座標管理装置
１０１に入力し、観察チップの原点を選択し、その出力
座標に基づき観察する。観察した後、更に必要ならば同
一の作業を繰り返す。図８に観察座標から配線回路８０
１に異物８０２を観察した様子を示した。FIG. 4 shows the flow of observation. After etching the sample, the observation step is input to the mark coordinate management device 101, the origin of the observation chip is selected, and observation is performed based on the output coordinates. After the observation, the same operation is repeated if necessary. The wiring circuit 80 from the observation coordinates in FIG.
1 shows the appearance of the foreign matter 802.
【００１９】図９に本発明の他の実施例を示す。この実
施例は、検査データ収集解析１００から観察するデータ
を選択し、その情報を座標入力装置１０２から入力し目
印座標管理指示装置９０１は目印座標，観察座標を直接
試料エッチング装置９１０（例えばフォーカスとイオン
ビームエッチング装置等）に送信し、観察したい場所の
上層膜を剥がす。その後、ウェハスケールで観察できる
装置９１１にウェハを送り、ウェハ全体の中から、部分
的に観察できる。FIG. 9 shows another embodiment of the present invention. In this embodiment, data to be observed is selected from the inspection data collection and analysis 100, the information is input from the coordinate input device 102, and the mark coordinate management instruction device 901 directly outputs the mark coordinates and the observation coordinates to the sample etching device 910 (for example, focus Ion beam etching equipment, etc.) and peel off the upper layer film where you want to observe. After that, the wafer is sent to a device 911 that allows observation on a wafer scale, and partial observation can be performed from the entire wafer.
【００２０】[0020]
【発明の効果】本発明によれば、半導体チップ上の不良
位置をチップ全体を観察視野上で走査することなく、予
め管理した原点となる目印パターンからの距離を算出で
き、観察が短時間で行え、不良解析の効率を向上するこ
とができる。According to the present invention, it is possible to calculate the distance from a mark pattern serving as an origin that is managed in advance without scanning a defective position on a semiconductor chip over the entire observation field of view, and observation can be performed in a short time. It is possible to improve the efficiency of failure analysis.
【００２１】この方式により、半導体の不良解析期間を
従来の目印が無い場合に１〜２週間要していた作業が１
／２〜１／３に低減でき、短時間で不良原因を特定で
き、その原因に合わせた対策が早期に実施できるように
なり、半導体の歩留り向上の効果がある。With this method, it is possible to reduce the semiconductor defect analysis period from one to two weeks without the conventional mark.
The ratio can be reduced to / 2 to 1/3, the cause of the defect can be specified in a short time, and the countermeasure corresponding to the cause can be implemented at an early stage, which has the effect of improving the semiconductor yield.
【図１】本発明の第１の実施例の装置構成を示すブロッ
ク図。FIG. 1 is a block diagram showing a device configuration of a first embodiment of the present invention.
【図２】本発明の実施例における観察座標特定方法の説
明図。FIG. 2 is an explanatory diagram of an observation coordinate specifying method according to an embodiment of the present invention.
【図３】本発明の実施例における観察座標出力フロー
図。FIG. 3 is an observation coordinate output flow chart in the embodiment of the present invention.
【図４】本発明の実施例における観察座標原点選択フロ
ー図。FIG. 4 is a flow chart of observation coordinate origin selection flow according to the embodiment of the present invention.
【図５】本発明の実施例における目印レチクルの説明
図。FIG. 5 is an explanatory diagram of a mark reticle according to the embodiment of the present invention.
【図６】本発明の実施例における切り出した目印付チッ
プの概略図。FIG. 6 is a schematic view of a cut-out marker chip according to an embodiment of the present invention.
【図７】本発明の実施例における座標管理方法の説明
図。FIG. 7 is an explanatory diagram of a coordinate management method according to an embodiment of the present invention.
【図８】本発明の実施例における観察方法の説明図。FIG. 8 is an explanatory diagram of an observation method according to an example of the present invention.
【図９】本発明の第２の実施例の装置構成を示すブロッ
ク図。FIG. 9 is a block diagram showing a device configuration of a second embodiment of the present invention.
１０１…検査データ収集解析、１０１…目印座標管理装
置、１１１…観察装置（ＳＥＭ）１０２…切出し座標観
察座標入力部分、２０１…検査ウェハ、２０３…検査位
置入力、５０２〜５０９…目印パターン、７０１…スク
ライブセンタ、７０２…チップ配列、９１０…試料エッ
チング装置、９１１…ウェハスケール観察装置。Reference numeral 101 ... Inspection data collection / analysis, 101 ... Mark coordinate management device, 111 ... Observation device (SEM) 102 ... Cutout coordinate observation coordinate input portion, 201 ... Inspection wafer, 203 ... Inspection position input, 502-509 ... Mark pattern, 701 ... Scribing center, 702 ... Chip array, 910 ... Sample etching apparatus, 911 ... Wafer scale observation apparatus.
Claims (5)
解析において、電気的不良の発生箇所のウェハ上の位置
座標を観察する際に、半導体ウェハ上に目印パターンと
なる予め記された領域を定義した座標の原点を基に観察
装置を制御し、観察することを特徴とした半導体装置の
不良解析方法。1. In a failure analysis of a semiconductor wafer forming a semiconductor device, when observing the position coordinates on the wafer of a location where an electrical failure occurs, a pre-described area serving as a mark pattern is defined on the semiconductor wafer. A defect analysis method for a semiconductor device, characterized by controlling and observing an observation device based on the origin of the coordinates.
タを表示するインターフェースから入力する手段と、該
データと半導体ウェハ上に予め記された領域を定義した
座標の原点の座標を管理する手段と、両者のデータを結
合して観察する座標を出力する手段を有することを特徴
とする半導体装置の不良解析装置。2. A means for inputting position coordinates on a wafer to be observed from an interface for displaying inspection data, and a means for managing coordinates of an origin of coordinates defining the data and a region previously written on the semiconductor wafer. And a defect analysis device for a semiconductor device, comprising means for combining data of both and outputting coordinates for observation.
導体製造のマスクのチップを切断する領域に設けたこと
を特徴とした半導体装置の不良解析方法。3. A method of analyzing defects in a semiconductor device according to claim 1, wherein said pre-installed mark pattern is provided in a region for cutting a chip of a mask for manufacturing a semiconductor.
導体製造のマスクのチップを切断する領域に設け、製造
工程毎のマスクパターンに設置し、かつ工程毎にパター
ンが重複しないようにしたことを特徴とした半導体装置
の不良解析方法。4. The pre-installed mark pattern according to claim 3 is provided in a region where a chip of a mask for semiconductor manufacturing is cut, is set in a mask pattern for each manufacturing process, and the patterns do not overlap in each process. A semiconductor device failure analysis method characterized by the above.
４の目印パターンの座標を管理する手段と、検査の不良
座標のデータを結合して観察する座標を出力する手段を
有することを特徴とした半導体装置の不良解析装置。5. A means for managing the coordinates of the mark pattern of claim 4 as the origin of the chip coordinates of claim 2, and a means for outputting the coordinates for observation by combining the data of the defective coordinates of the inspection. Failure analysis device for semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2893596A JPH09223723A (en) | 1996-02-16 | 1996-02-16 | Method and equipment for analyzing failure of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2893596A JPH09223723A (en) | 1996-02-16 | 1996-02-16 | Method and equipment for analyzing failure of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09223723A true JPH09223723A (en) | 1997-08-26 |
Family
ID=12262269
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2893596A Pending JPH09223723A (en) | 1996-02-16 | 1996-02-16 | Method and equipment for analyzing failure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09223723A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6598217B1 (en) | 2000-02-18 | 2003-07-22 | Mitsubishi Denki Kabushiki Kaisha | Method of mounting fabrication-historical data for semiconductor device, and semiconductor device fabricated by such a method |
| US6650768B1 (en) | 1998-02-19 | 2003-11-18 | International Business Machines Corporation | Using time resolved light emission from VLSI circuit devices for navigation on complex systems |
| JP2007258359A (en) * | 2006-03-22 | 2007-10-04 | Sharp Corp | Process for manufacturing semiconductor device and deposition device of semiconductor device |
| CN103855047A (en) * | 2012-12-04 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Physical analysis structure and method of deep-groove products |
-
1996
- 1996-02-16 JP JP2893596A patent/JPH09223723A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6650768B1 (en) | 1998-02-19 | 2003-11-18 | International Business Machines Corporation | Using time resolved light emission from VLSI circuit devices for navigation on complex systems |
| US6598217B1 (en) | 2000-02-18 | 2003-07-22 | Mitsubishi Denki Kabushiki Kaisha | Method of mounting fabrication-historical data for semiconductor device, and semiconductor device fabricated by such a method |
| JP2007258359A (en) * | 2006-03-22 | 2007-10-04 | Sharp Corp | Process for manufacturing semiconductor device and deposition device of semiconductor device |
| CN103855047A (en) * | 2012-12-04 | 2014-06-11 | 上海华虹宏力半导体制造有限公司 | Physical analysis structure and method of deep-groove products |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6362013B1 (en) | Semiconductor inspection apparatus and method of specifying attributes of dies on wafer in semiconductor inspection apparatus | |
| JP2002323458A (en) | Defect inspection management system and defect inspection system and apparatus of electronic circuit pattern | |
| JP5411211B2 (en) | Defect analyzer | |
| TWI309789B (en) | Method for translating repeater defect coordinates to reticle coordinates using cad data in a semiconductor wafer reticle | |
| WO2005008548A1 (en) | Method of transmitting cad data to a wafer inspection system | |
| JPS62276848A (en) | Electron beam test probe system for integrated circuit analysis | |
| US8178837B2 (en) | Logical CAD navigation for device characteristics evaluation system | |
| JP2002532760A (en) | Mechanisms for manufacturing and inspecting reticles | |
| US6687633B2 (en) | Inspection system, inspection apparatus, inspection program, and production method of semiconductor devices | |
| US20140177940A1 (en) | Recipe generation apparatus, inspection support apparatus, inspection system, and recording media | |
| US6724929B1 (en) | Wafer inspecting apparatus | |
| US7149340B2 (en) | Mask defect analysis for both horizontal and vertical processing effects | |
| JP2009206248A (en) | Apparatus and method for inspecting overlapping figure, and charged particle beam writing apparatus | |
| KR20030051064A (en) | Method for measuring fail probability by only defect, method for measuring defect limited yield using classification the extracted defect pattern's parameter, and system for measuring fail probability by only defect and the defect limited yield | |
| JPH09223723A (en) | Method and equipment for analyzing failure of semiconductor device | |
| CN108231617B (en) | Defect analysis | |
| JPH11340291A (en) | Semiconductor device inspecting/analyzing method, its system, and manufacture of semiconductor device | |
| KR20080058682A (en) | Method for manufacturing specimen for analyzing by transmission electron microscope | |
| JPH1050787A (en) | Apparatus and method for analyzing defect in semiconductor device | |
| US7079966B2 (en) | Method of qualifying a process tool with wafer defect maps | |
| US20060023931A1 (en) | System for evaluating a design of a mask, exposure system, method for evaluating a design of a mask, method for manufacturing a semiconductor device and mask | |
| JPH1174326A (en) | Semiconductor section observing device | |
| JP2894078B2 (en) | Failure analysis device and failure analysis method for integrated circuit device | |
| US7634127B1 (en) | Efficient storage of fail data to aid in fault isolation | |
| JPH10339943A (en) | Production of semiconductor device |