JPS61285542A - Instruction prefetching method - Google Patents
Instruction prefetching methodInfo
- Publication number
- JPS61285542A JPS61285542A JP12737585A JP12737585A JPS61285542A JP S61285542 A JPS61285542 A JP S61285542A JP 12737585 A JP12737585 A JP 12737585A JP 12737585 A JP12737585 A JP 12737585A JP S61285542 A JPS61285542 A JP S61285542A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- address
- register
- odd
- instructions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- Advance Control (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、高速処理を要求される計算機の命令先取り
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for prefetching instructions in computers that require high-speed processing.
第2図は従来の命令先取り方法を説明するためのもので
あり2図において(1)は単語長命令及び倍語長命令の
組合せからなるプログラムが格納された主記憶部、(2
)は次に実行すべき命令が格納された主記憶部(1)の
アドレスを保持する命令アドレスレジスタ、(3)は命
令アドレスレジスタ(2)に保持されたアドレスに従っ
て主記憶部(1)から読み出された命令が保持される命
令レジスタ、(4)は命令レジスタ(3)に保持されて
いる命令を解読する命令解読部、(5)は命令解読部(
4)の指令により命令を実行する中央処理装置部である
。FIG. 2 is for explaining the conventional instruction prefetching method. In FIG.
) is an instruction address register that holds the address of the main memory (1) where the next instruction to be executed is stored, and (3) is the instruction address register that holds the address of the main memory (1) where the next instruction to be executed is stored. (4) is an instruction decoding unit that decodes the instructions held in the instruction register (3); (5) is an instruction decoding unit (
4) is a central processing unit that executes instructions according to instructions.
次に動作について説明する。中央処理装置部(5)が命
令解読部(4)の指令で命令を実行している間に。Next, the operation will be explained. While the central processing unit (5) is executing instructions according to instructions from the instruction decoding unit (4).
命令アドレスレジスタ(2)の内容は、命令解読部(4
)の指令で欠如実行すべき命令のアドレスに更新され、
そのアドレスに従って主記憶部(1)から読み出された
次に実行すべき命令が命令レジスタ(3)に保持される
。中央処理装置(5)が現在実行中の命令の処理が終了
した時点で命令解読部(4)は命令レジスタ(3)に保
持されている命令を解読し、中央処理装置(5)に次の
命令の実行の指令を与える。この様にして次々と主記憶
部(1)に格納されたプログラムが中央処理装置部(5
)で処理されていく。The contents of the instruction address register (2) are stored in the instruction decoder (4).
) is updated to the address of the instruction to be executed, missing in the command
The next instruction to be executed read from the main memory (1) according to the address is held in the instruction register (3). When the central processing unit (5) finishes processing the instruction currently being executed, the instruction decoding unit (4) decodes the instruction held in the instruction register (3) and sends the next instruction to the central processing unit (5). Give instructions for the execution of commands. In this way, the programs stored in the main memory (1) one after another are stored in the central processing unit (5).
) will be processed.
上記のような従来の命令先取り方法では、単語長命令の
みで構成されている場合は常に次に実行すべき命令が読
み出されているが1倍語長命令が入ったプログラムの場
合は2倍語長命令の2語目が読み出されてなく、中央処
理装置部が命令を実行する前に2語目の命令を読み出す
必要があり。In the conventional instruction prefetch method as described above, if the program consists of only word-length instructions, the next instruction to be executed is always read, but in the case of a program containing 1x word-length instructions, the number of instructions to be executed is doubled. The second word of the word length instruction has not been read, and it is necessary to read the second word before the central processing unit executes the instruction.
倍語長命令の実行時間が遅くなるという問題点があった
。There was a problem in that the execution time of double-length instructions was slow.
この発明は、かかる問題点を解決するためになされたも
ので、単語長命令でも倍語長命令でも常に命令先取りが
なされている命令先取り方法を得ることを目的とする。The present invention was made to solve this problem, and an object of the present invention is to provide an instruction prefetching method in which instructions are always prefetched for both word-length instructions and double-word-length instructions.
この発明に係る命令先取り方法は、主記憶部を偶数アド
レス部と奇数アドレス部に分割し、同時に双方から1語
づつ、あわせて2語の命令を読み出し、命令レジスタは
3個用意し、偶数アドレス部から読み出された命令1語
と奇数アドレス部から読み出された命令を読み出された
順に2語保持するものである。The instruction prefetching method according to the present invention divides the main memory into an even address section and an odd address section, reads one word from both at the same time, a total of two instruction words, prepares three instruction registers, and One instruction word read from the odd address section and two instructions read from the odd address section are held in the order in which they were read.
この発明においては、同時に2語の命令を読み出し、読
み出しの順に、奇数アドレス命令、偶数アドレス命令、
奇数アドレス命令の3語が命令レジスタに保持されてい
るので9倍語長命令が、主記憶部に、偶数アドレス、奇
数アドレスの順に格納されていても、逆に奇数アドレス
、偶数アドレスの順に格納されていても、常に命令レジ
スタに先取りされている。これKより9倍語長命令の実
行時間を速くすることができる。In this invention, two-word instructions are read at the same time, and in the order of reading, an odd address instruction, an even address instruction,
Since the three words of an odd address instruction are held in the instruction register, even if a 9x word length instruction is stored in the main memory in the order of even addresses and then odd addresses, it will be stored in the order of odd addresses and even addresses. It is always pre-fetched in the instruction register even if it is executed. This allows the execution time of an instruction with a word length 9 times faster than that of K.
第1図は、この発明の一実施例を示すためのものであり
9図において、 +21 、 (4) 、 (51は上
記従来の構成と全く同一のものであり、 (1a)は
単語長命令及び倍語長命令の組合せからなるプログラム
が格納された主記憶部の偶数アドレスに対応する部分。Figure 1 is for showing one embodiment of the present invention. and a portion corresponding to an even address in the main memory where a program consisting of a combination of double word length instructions is stored.
(1b)は上記主記憶部の奇数アドレスに対応する部分
。(1b) is a portion corresponding to an odd address in the main memory section.
(3a)は主記憶部(1a)から読み出された命令を保
持する偶数アドレス命令レジスタ、 (3b)は主記
憶部(1b)から読み出された命令を保持する奇数アド
レス命令レジスタ、 (3c)は奇数アドレス命令レ
ジスタ(3b)に次に読み出された命令がセットされる
時に奇数命令レジスタ(3b)に保持されている命令を
取り込み保持する奇数アドレス命令レジスタ、 (6a
)は命令解読部(4)の指令により、偶数アドレス命令
レジスタ(3a)と奇数アドレス命令レジスタ(3C)
とを選択し2次に実行すべき命令を命令解読部(4)に
与えるセレクタp (6b)は命令解読部(4)の指
令により、奇数アドレス命令レジスタ(5b)と偶数ア
ドレス命令レジスタ(6a)とを選択し2倍語長命令の
2語目を中央処理装置(5)に与えるセレクタである。(3a) is an even address instruction register that holds instructions read from the main memory (1a); (3b) is an odd address instruction register that holds instructions read from the main memory (1b); (3c) ) is an odd address instruction register (6a) that captures and holds the instruction held in the odd instruction register (3b) when the next read instruction is set in the odd address instruction register (3b).
) is an even address instruction register (3a) and an odd address instruction register (3C) according to a command from the instruction decoder (4).
The selector p (6b) selects the instruction to be executed next and gives the instruction to be executed next to the instruction decoder (4). ) and supplies the second word of the double word length instruction to the central processing unit (5).
次に動作について説明する。単語長命令の処理について
は従来の命令先取り方法と同様であるが。Next, the operation will be explained. Processing of word length instructions is similar to the conventional instruction prefetch method.
本発明忙よる命令先取り方法では、同時に2語読み出さ
れるため、命令解読部(4)はセレクタ(6a)を制御
して順次奇数アドレス命令レジスタ(3C)と偶数アド
レス命令レジスタ(6a)を選択し、命令解読し、中央
処理装置部(5)に実行指令を与える。In the busy instruction prefetch method of the present invention, since two words are read at the same time, the instruction decoder (4) controls the selector (6a) to sequentially select the odd address instruction register (3C) and the even address instruction register (6a). , decodes the command, and gives an execution command to the central processing unit (5).
主記憶部(Ia) 、 (1b)の偶数アドレス、奇数
アドレスに格納されている倍語長命令の処理は、中央処
理装置部(5)が現在実行中の命令の処理を終了しさ時
点で、命令解読部(4)は、セレクタ(6a)を制御し
て偶数アドレス命令レジスタ(3a)に保持されている
命令を解読し、中央処理装置部(5)にその命令の実行
を指令し、セレクタ(6b)を制御して奇数アドレス命
令レジスタ(3b)の内容を倍語長命令の2語目として
与える。その時命令アドレスレジスタ(2)は更に次の
偶数アドレスに更新され、主記憶部(1a)、 (1b
)から次の命令2語を読み出し、偶数アドレス命令レジ
スタ(3a)、奇数アドレス命令レジスタ(3b)にセ
ットする。倍語長命令が主記憶部(1a)(1b)の奇
数アドレス、偶数アドレス把格納されている時は、命令
解読部(4)はセレクタ(6a)により奇数アドレス命
令レジスタ(3c)を解読して中央処理装置部(5)に
実行指令を与え9倍語長命令の2語目としてセレクタ(
6b)により偶数アドレス命令レジスタ(3a)の内容
を与えて、上記と同様の動作を行う。The processing of the double word length instructions stored in the even and odd addresses of the main memory sections (Ia) and (1b) is carried out at the point when the central processing unit section (5) finishes processing the instruction currently being executed. The instruction decoder (4) controls the selector (6a) to decode the instruction held in the even address instruction register (3a), instructs the central processing unit (5) to execute the instruction, and (6b) to give the contents of the odd address instruction register (3b) as the second word of the double word length instruction. At that time, the instruction address register (2) is further updated to the next even address, and the main memory (1a), (1b
), and set them in the even address instruction register (3a) and the odd address instruction register (3b). When a double word length instruction is stored at odd or even addresses in the main memory (1a) (1b), the instruction decoder (4) decodes the odd address instruction register (3c) using the selector (6a). gives an execution command to the central processing unit (5) and selects the selector (
6b) gives the contents of the even address instruction register (3a) and performs the same operation as above.
この発明による命令先取り方式は以上のような方法であ
るので、単語長命令と倍語長命令の組み合せからなるプ
ログラムを処理する場合、常に次に実行すべき命令が先
取りされているため、命令読み出し時間を削減すること
ができる。Since the instruction prefetching method according to the present invention is as described above, when processing a program consisting of a combination of word length instructions and double word length instructions, the next instruction to be executed is always prefetched, so that the instruction read time can be reduced.
以上のように、この発明による命令先取り方法では、単
語長命令でも倍語長命令でも常に命令先取りがなされて
おり、高速に処理できる利点がある。As described above, in the instruction prefetching method according to the present invention, instruction prefetching is always performed for both word-length instructions and double-word-length instructions, and has the advantage of high-speed processing.
第1図は本発明による命令先取り方法を説明するための
図、第2図は従来の命令先取り方法な説明するための図
である。図中、(1ンは主記憶部、(2)は命令アドレ
スレジスタ、(3)は命令レジスタ、(4)は命令解読
部、(5)は中央処理装置部、(6)は造しクタである
。
なお9図中、同一あるいは相当部分には同一符号を付し
て示しである。FIG. 1 is a diagram for explaining an instruction prefetching method according to the present invention, and FIG. 2 is a diagram for explaining a conventional instruction prefetching method. In the figure, (1) is the main memory, (2) is the instruction address register, (3) is the instruction register, (4) is the instruction decoder, (5) is the central processing unit, and (6) is the built-in controller. In Figure 9, the same or corresponding parts are indicated by the same reference numerals.
Claims (1)
せからなるプログラムが、命令アドレスレジスタの指定
するアドレスに従つて読み出された命令レジスタに保持
され、解読実行される計算機の命令読み出し方法におい
て、主記憶部を偶数アドレス部を奇数アドレス部に分割
し、偶数アドレス部から読み出された命令を保持するレ
ジスタと、奇数アドレス部から読み出された命令を読み
出された順に保持する2個のレジスタと、命令アドレス
レジスタの偶数・奇数により次に実行すべき命令を上記
命令レジスタから選択するセレクタとを有し、中央処理
装置部が命令の解読実行している間に、主記憶部から偶
数アドレス、奇数アドレス同時に上記命令レジスタに読
み出しておく事により、次に実行すべき命令が常に先に
読み出されている事を特徴とする命令先取り方法。Computer instruction reading where a program consisting of a combination of word length instructions and double word length instructions stored in the main memory is held in an instruction register read out according to the address specified by the instruction address register, and decoded and executed. In this method, the main memory is divided into an even address part and an odd address part, and a register holds instructions read from the even address part, and a register holds instructions read from the odd address part in the order in which they are read. It has two registers and a selector that selects the next instruction to be executed from the instruction register according to the even/odd number of the instruction address register. An instruction prefetching method characterized in that an instruction to be executed next is always read out first by reading out even and odd addresses from the above instruction register at the same time.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12737585A JPS61285542A (en) | 1985-06-12 | 1985-06-12 | Instruction prefetching method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12737585A JPS61285542A (en) | 1985-06-12 | 1985-06-12 | Instruction prefetching method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61285542A true JPS61285542A (en) | 1986-12-16 |
Family
ID=14958427
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12737585A Pending JPS61285542A (en) | 1985-06-12 | 1985-06-12 | Instruction prefetching method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61285542A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0421128A (en) * | 1990-05-16 | 1992-01-24 | Advantest Corp | Instruction reading circuit |
JPH0784781A (en) * | 1993-09-13 | 1995-03-31 | Nec Corp | Information processor |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5344130A (en) * | 1976-10-05 | 1978-04-20 | Toshiba Corp | Floating access memory device |
JPS5656450A (en) * | 1979-10-09 | 1981-05-18 | Marshall & Williams Co | Stretching clip chain |
JPS56124953A (en) * | 1980-03-05 | 1981-09-30 | Hitachi Ltd | Instruction fetch system |
JPS5764855A (en) * | 1980-10-06 | 1982-04-20 | Advantest Corp | Storage device |
-
1985
- 1985-06-12 JP JP12737585A patent/JPS61285542A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5344130A (en) * | 1976-10-05 | 1978-04-20 | Toshiba Corp | Floating access memory device |
JPS5656450A (en) * | 1979-10-09 | 1981-05-18 | Marshall & Williams Co | Stretching clip chain |
JPS56124953A (en) * | 1980-03-05 | 1981-09-30 | Hitachi Ltd | Instruction fetch system |
JPS5764855A (en) * | 1980-10-06 | 1982-04-20 | Advantest Corp | Storage device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0421128A (en) * | 1990-05-16 | 1992-01-24 | Advantest Corp | Instruction reading circuit |
JPH0784781A (en) * | 1993-09-13 | 1995-03-31 | Nec Corp | Information processor |
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