JPS61279963A - Interruption control system - Google Patents

Interruption control system

Info

Publication number
JPS61279963A
JPS61279963A JP60120483A JP12048385A JPS61279963A JP S61279963 A JPS61279963 A JP S61279963A JP 60120483 A JP60120483 A JP 60120483A JP 12048385 A JP12048385 A JP 12048385A JP S61279963 A JPS61279963 A JP S61279963A
Authority
JP
Japan
Prior art keywords
interruption
interrupt
input
processing unit
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60120483A
Other languages
Japanese (ja)
Inventor
Toshikatsu Taniguchi
敏克 谷口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60120483A priority Critical patent/JPS61279963A/en
Publication of JPS61279963A publication Critical patent/JPS61279963A/en
Pending legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE:To prevent the deterioration of CPU's processing ability due to a continuously arising asynchronizing interruption by providing a means storing the time when an interruption from an I/O device is reported to the CPU at every interruption in an I/O controller. CONSTITUTION:The I/O controller 2 is connected to the central processing unit CPU 1, and one or more I/O devices 3 are connected under the control of the controller 2. In terms of the controller 2, a memory device 22 stores the time when the asynchronizing interruption occurs and its phenomenon, the memory device 23 stores at every interruption the reporting time when said asynchronizing interruption is reported to the CPU1, a memory device 24 stores at every interruption the interval of the asynchronizing interruption arising time when the device 3 is in normal operation, and a memory device 25 stores the phenomenon of the previously arising asynchronizing interruption. When an interruption processing unit 26 accepts the asynchronizing interruption, it decides whether it reports said interruption to the CPU 1 or not.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は割込み制御方式に係り、特に電子計算機システ
ムにおいて、障害により入出力装置で連続的に発生した
非同期割込みの中央処理装置への報告を抑止する方式に
関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an interrupt control method, and in particular, to suppressing the reporting of asynchronous interrupts that occur continuously in an input/output device due to a failure to a central processing unit in a computer system. Regarding the method of

〔発明の背景〕[Background of the invention]

従来、中央処理装置と入出力装置が入出力制御装置を介
して接続されるに電子計算機システムにおいて、入出力
装置で非同期に割込みを発生すると、入出力制御装置は
該非同期側込みを無条件に中央処理装置に報告していた
。中央処理装置は割込みを受付けると、実行中の処理を
中断して割込み処理を行う、従って、入出力装置の障害
にｉり非同期割込みが繰り返し報告されると、中央処理
装置は割込み処理に占有され、電子計算機システムの処
理速力が低下する。なお、非同期割込みに関連するもの
には例えば特公昭２５７−９０９０号が挙げら九るが、
繰り返し発生する場合の処理能力の低下について考慮さ
れていない。Conventionally, in electronic computer systems where a central processing unit and an input/output device are connected via an input/output control device, when an input/output device generates an interrupt asynchronously, the input/output control device unconditionally handles the asynchronous side interrupt. It was reported to the central processing unit. When the central processing unit receives an interrupt, it interrupts the current process and handles the interrupt. Therefore, if an asynchronous interrupt is repeatedly reported due to an input/output device failure, the central processing unit becomes occupied with interrupt processing. , the processing speed of the computer system decreases. In addition, examples related to asynchronous interrupts include Japanese Patent Publication No. 257-9090.
No consideration is given to the reduction in processing performance when the problem occurs repeatedly.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、入出力装置の障害により連続的に発生
する非同期割込みによる中央処理装置の処理能力の低下
を防止することにある。An object of the present invention is to prevent a decline in the processing capacity of a central processing unit due to asynchronous interrupts that occur continuously due to failures in input/output devices.

〔発明の概要〕[Summary of the invention]

本発明は、入出力装置の非同期割込みの中央処理装置へ
の報告時刻を入出力制御装置内に割込み事象ごとに記憶
しておき、非同期割込みが発生した場合、同一事象の前
回の割込み発生報告から予め定めた時間経過していなけ
れば、該非同期側込みの入出力制御装置から中央処理装
置への報告を抑止するものである。The present invention stores the time at which an asynchronous interrupt of an input/output device is reported to a central processing unit in the input/output control device for each interrupt event, and when an asynchronous interrupt occurs, the report time of an asynchronous interrupt of an input/output device to a central processing unit is stored. If a predetermined period of time has not elapsed, the asynchronous side input/output control device is inhibited from reporting to the central processing unit.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例を図面に基づいて説明する。 Hereinafter, one embodiment of the present invention will be described based on the drawings.

第２図は本発明における電子計算機システムの構成例を
示したもので、中央処理装置ｌに入出力制御装置１が接
続され、該入出力制御装置２の制御下に１台もしくはそ
れ以上の入出力装置３が接続される０便宜上、第２図で
は入出力制御装置２に１台の入出力装置が接続されると
している。FIG. 2 shows a configuration example of a computer system according to the present invention, in which a central processing unit l is connected to an input/output control device 1, and one or more input/output devices are controlled by the input/output control device 2. For convenience, FIG. 2 assumes that one input/output device is connected to the input/output control device 2.

第１図に本発明を実現するための入出力制御装置２の構
成例を示す。第１図において、時計機構２１は実時計の
働きをする。記憶装置（Ｍｌ）２２は非同期割込みが発
生したときの時刻と割込み事象を記憶する６記憶装置（
Ｍ２）２３は割込み事象ごとに中央処理装置１に報告し
た非同期割込みの報告時刻を記憶する。記憶装置（Ｍ３
）２４は入出力装置３の正常動作時の非同期割込み発生
時間間隔を割込み事象ごとに記憶する。記憶装置（Ｍ４
）２５は前回発生した非同期割込みの事象を記憶する。FIG. 1 shows an example of the configuration of an input/output control device 2 for realizing the present invention. In FIG. 1, a clock mechanism 21 functions as a real clock. The storage device (Ml) 22 is a storage device (Ml) 6 that stores the time and interrupt event when an asynchronous interrupt occurs.
M2) 23 stores the reporting time of the asynchronous interrupt reported to the central processing unit 1 for each interrupt event. Storage device (M3
) 24 stores the asynchronous interrupt occurrence time interval during normal operation of the input/output device 3 for each interrupt event. Storage device (M4
) 25 stores the event of the asynchronous interrupt that occurred last time.

第３図は記憶装置２２〜２５のメモリマツプを示したも
のである０割込み処理ユニット２６は入出力装置３から
非同期割込みを受付けると、中央処理装置１に鎖側込み
を報告するかどうか決める。なお、記憶装置２２〜２５
は一つのメモリを用いてもよい。FIG. 3 shows a memory map of the storage devices 22 to 25. When the interrupt processing unit 26 receives an asynchronous interrupt from the input/output device 3, it decides whether to report the chain side interrupt to the central processing unit 1. Note that the storage devices 22 to 25
may use one memory.

第４図は割込み処理ユニット２６の処理フローを示す。FIG. 4 shows the processing flow of the interrupt processing unit 26.

以下、第４図に従って説明する。This will be explained below according to FIG.

非同期割込みが発生すると、その割込み事象と発生時刻
を記憶装置（Ｍｌ）２２に記憶する（ステップ１０１）
、次に記憶装置（Ｍｌ）２２と記憶装置（Ｍ４）２５の
内容から今回発生した割込み事象の内容が前回発生した
割込み事象の内容と同じかどうか判断する（ステップ１
０２）、同じ事象でなければステップ１０４にジャンプ
するが、同じ事象であれば、記憶装置（Ｍｌ）２２と記
憶装［（Ｍ２）２３の内容から前回当該事象の割込み報
告を中央処理装置１に報告してからの経過時間を求め、
記憶装置（Ｍ３）２４に記憶している正常動作時の当該
事象発生時間間隔以上の時間が経過しているか判断する
（ステップ１０３）−経　１過していれば、当該事象の
割込み報告を中央処理装置１に報告しくステップ１０４
）、記憶装置（Ｍｌ）２２の内容のうち、割込み発生時
刻を記憶装置（Ｍ２）２３の該当領域に報告時刻として
記憶しくステップ１０５）、割込み事象を記憶装置（Ｍ
４）２５に記憶する（ステップ１０６）。When an asynchronous interrupt occurs, the interrupt event and occurrence time are stored in the storage device (Ml) 22 (step 101).
Next, it is determined from the contents of the storage device (Ml) 22 and the storage device (M4) 25 whether the contents of the interrupt event that occurred this time are the same as the contents of the interrupt event that occurred last time (step 1
02), if the event is not the same, the process jumps to step 104, but if the event is the same, the interrupt report of the previous event is sent to the central processing unit 1 from the contents of the memory device (Ml) 22 and the memory device [(M2) 23. Find the elapsed time since the report was made,
Determine whether a time equal to or longer than the time interval of occurrence of the event during normal operation stored in the storage device (M3) 24 has elapsed (step 103). Step 104 to report to processing device 1
), among the contents of the storage device (Ml) 22, the interrupt occurrence time is stored as a report time in the corresponding area of the storage device (M2) 23 (step 105), and the interrupt event is stored in the storage device (Ml) 22 as a report time.
4) Store in 25 (step 106).

また、ステップ１０３で所定時間間隔以下であることが
判定されると、今回発生した非同期割込みの中央処理袋
！ｉｌｌへの報告を抑止しくステップ１０７）、単に記
憶装置（Ｍｌ）２２の当該割込み事象を記憶装置（Ｍ４
）２５に記憶する（ステップ１０６）。Further, if it is determined in step 103 that the time interval is less than or equal to the predetermined time interval, the central processing block for the asynchronous interrupt that occurred this time! In order to suppress the reporting to the memory device (step 107), the corresponding interrupt event in the memory device (Ml) 22 is simply transmitted to the memory device (M4).
) 25 (step 106).

（発明の効果〕 本発明によれば１人出力装置に発生する同一事象の非同
期割込みの中央処理装置への報告を予め定めた時間内で
は１回に押えることができるので。(Effects of the Invention) According to the present invention, asynchronous interrupts of the same event occurring in a single output device can be reported to the central processing unit only once within a predetermined time.

入出力装置の障害により連続的に発生した非同期割込み
の処理による中央処理装置の処理能力低下防止に効果が
ある。This is effective in preventing a decline in the processing capacity of the central processing unit due to the processing of asynchronous interrupts that occur continuously due to failures in input/output devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は入出力制御装置の一実施例を示す図、第２図は
本発明で対象とする電子計算機システムの構成例を示す
図、第３図は第１図における記憶装置のメモリマツプを
示す図、第４図は第１図における割込み処理ユニットの
動作を説明するフロー図である。 １・・・中央処理装置、　２・・・入出力制御装置、３
・・・入出力装置、　２１・・・時計機構、２２〜２５
・・・記憶装置。 ２６・・・割込み処理ユニット。 第１図 第２図 第３図 Ｍ４　Ｅ口FIG. 1 is a diagram showing an example of an input/output control device, FIG. 2 is a diagram showing a configuration example of a computer system targeted by the present invention, and FIG. 3 is a memory map of the storage device in FIG. 1. 4 are flowcharts illustrating the operation of the interrupt processing unit in FIG. 1. 1... Central processing unit, 2... Input/output control device, 3
...input/output device, 21...clock mechanism, 22-25
···Storage device. 26... Interrupt processing unit. Figure 1 Figure 2 Figure 3 M4 E port

Claims (1)

【特許請求の範囲】[Claims] （１）中央処理装置と入出力制御装置と入出力装置を備
えている電子計算機システムにおいて、入出力制御装置
内に、入出力装置からの割込みの中央処理装置への報告
時刻を割込み事象ごとに記憶する手段を設け、該入出力
制御装置は、入出力装置から割込みを受け取ると、同一
事象の割込みの前回の中央処理装置への報告時刻から予
め定めた時間経過しているか否か調べ、予め定めた時間
経過していれば当該割込みを中央処理装置へ報告し、経
過していなければ報告を抑止することを特徴とする割込
み制御方式。(1) In a computer system equipped with a central processing unit, an input/output control unit, and an input/output device, the input/output control unit records the time at which an interrupt from the input/output device is reported to the central processing unit for each interrupt event. A storage means is provided, and when the input/output control device receives an interrupt from the input/output device, it checks whether a predetermined period of time has elapsed since the previous time when an interrupt of the same event was reported to the central processing unit, and An interrupt control method characterized by reporting the interrupt to a central processing unit if a predetermined time has elapsed, and suppressing the report if a predetermined time has not elapsed.
JP60120483A 1985-06-05 1985-06-05 Interruption control system Pending JPS61279963A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60120483A JPS61279963A (en) 1985-06-05 1985-06-05 Interruption control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60120483A JPS61279963A (en) 1985-06-05 1985-06-05 Interruption control system

Publications (1)

Publication Number Publication Date
JPS61279963A true JPS61279963A (en) 1986-12-10

Family

ID=14787292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60120483A Pending JPS61279963A (en) 1985-06-05 1985-06-05 Interruption control system

Country Status (1)

Country Link
JP (1) JPS61279963A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01270152A (en) * 1988-04-21 1989-10-27 Nec Ic Microcomput Syst Ltd Interruption circuit
JPH0229842A (en) * 1988-07-20 1990-01-31 Fujitsu Ltd Input/output interruption control system
JPH07152585A (en) * 1993-11-30 1995-06-16 Nec Corp Priority control monitor system
US6131137A (en) * 1997-09-08 2000-10-10 Fujitsu Limited Drive control unit and optical memory apparatus
US6151187A (en) * 1997-08-18 2000-11-21 Fujitsu Limited Disk unit, a servo track write system and a servo track write method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01270152A (en) * 1988-04-21 1989-10-27 Nec Ic Microcomput Syst Ltd Interruption circuit
JPH0229842A (en) * 1988-07-20 1990-01-31 Fujitsu Ltd Input/output interruption control system
JPH07152585A (en) * 1993-11-30 1995-06-16 Nec Corp Priority control monitor system
US6151187A (en) * 1997-08-18 2000-11-21 Fujitsu Limited Disk unit, a servo track write system and a servo track write method
US6131137A (en) * 1997-09-08 2000-10-10 Fujitsu Limited Drive control unit and optical memory apparatus

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