JPS6127641A - 集積回路装置の製造方法 - Google Patents

集積回路装置の製造方法

Info

Publication number
JPS6127641A
JPS6127641A JP13771785A JP13771785A JPS6127641A JP S6127641 A JPS6127641 A JP S6127641A JP 13771785 A JP13771785 A JP 13771785A JP 13771785 A JP13771785 A JP 13771785A JP S6127641 A JPS6127641 A JP S6127641A
Authority
JP
Japan
Prior art keywords
integrated circuit
glass
glass layer
substrate
beryllia
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13771785A
Other languages
English (en)
Inventor
Wahei Kitamura
北村　和平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13771785A priority Critical patent/JPS6127641A/ja
Publication of JPS6127641A publication Critical patent/JPS6127641A/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 本発明は集積回路装置の製造方法に関する。ここでは特
に絶縁物基板に半導体基板すなわち集積回路基板を取り
付けた半導体装置すなわち集積回路装置の製造方法につ
いて説明する。
従来、ダイオード、トランジスタ、ＩＣ等の半導体素子
を絶縁物基板、例えばセラミック基板等に固着し、半導
体素子をセラミックパッケージによって封止することが
行なわれている。この際半導体素子ペレットをセラミッ
クに固着するには、セラミック基板の所望表面に金（Ａ
ｕ）層をスクリーン印刷あるいはドツティングしその金
（Ａｕ）層にシリコン等の半導体基板を溶着する。また
他の方法では低熔融ガラス層を同様にスクリーン印刷（
グレーズ法）しそのガラス層に半導体基板を溶着する。
しかし乍らこのような技術によればこのシリコン基板の
溶着において金（Ａｕ）層形成はセラミック基板式を高
価なものにし、特にシリコン基板サイズの増大に伴ない
大きなものとなっている。また低熔融ガラス層形成法は
熱放散が悪いために高消費電力の製品に適用できない。
本発明の目的は上述のごとき問題点を解決した半導体装
置の製造方法などを提供するものである。
このような目的を達成するために本発明の一実施例の概
要は、絶縁物基板の一主表面に設けられたガラス層にべ
ＩＪ　ｌアを含有させ熱放散をよくしたことを特徴とす
るものである。
以下に本発明に係る一実施例を図面を参照して説明する
。第１図はセラミックデュアルインラインパッケージに
より封止した本発明に係る半導体装置を示す要部断面図
である。１がセラミック基板で、２がその基板の一表面
の凹部に設けられたベリリアを含むガラス層であり、こ
のガラス層２上に例えばシリコンからなる半導体素子ペ
レット３が設置され、熱処理されてセラミック基板１に
ガラス層２を介して固着されている。なお、同図におい
て５は外部ひき出しリード、５は半導体ペレットの電極
をリード部に接続するコネクターワイヤー、６はセラミ
ックケースであり、セラミック基板１に絶縁性ガラスを
介して接着されているものである。
かかる半導体装置の製法を次に詳述する。
セラミック基板１の凹部内にベリリアを含んだガラスペ
ットをスクリーン印刷（グレーズ法）し、ベリリアを含
むガラス層を形成する。ガラスペーストは半導体ペレッ
ト付用ガラス粉末を酢酸アルミ、ベンゼン、トリクレン
等からなる有機溶媒中顛分散させ、０．１〜０．３μｍ
程度の粉末のみからなる懸濁液をつくる。次いで０．１
μｍ以下のベリリア粉末をガラス粉末の重量で４０％程
混入させる。ここで作成されたベリリア人ガラスペース
トをスクリーン印刷（グレーズ法）によりセラミック基
板に被着する。これを乾燥したのち、通常４０００前後
で焼成しセラミック基板に付着させる。このようにして
形成されたベリリア人ガラス層２はシリコンペレット４
をその上にのせて加熱処理（たとえば４５０Ｃ程度の加
熱温度）を施こしてベリリア入ガラス層を介してセラミ
ック基板にシリコンペレットを固着する。然るのちリー
ド線先端部と半導体ペレット上面の電極をコネクタワイ
ヤ４によって接続し、セラミックキャップ６を低融点ガ
ラスを介して封着する。
以上のべたように、本発明の一実施例によれば熱伝導度
が従来のガラス埋込に比べ少なくとも１桁以上よくなる
ため、消費電力の大きい半導体素子にも採用できるので
金（Ａｕ）層形成が必要なくなり、部材を安価なものに
することができる。
またＡｕ層を用いてとりつける場合のように半導体素子
ペレット固着時にスクラブする必要がなくなり、歩留り
よく自動組立ができる利点がある。
また半導体素子の固着法が統一されるので部品の標準化
もはかれる。
【図面の簡単な説明】
第１図は本発明の一実施例に係る半導体装置の要部断面
図である。 】・・・セラミック基板、２・・・ガラス層、３・・・
半導体ペレット、４・・・コネクターワイヤ、５・・・
外部引出しリード、６・・・セラミックキャップ。 第　　１　　図

Claims (1)

  1. 【特許請求の範囲】 １、（ａ）絶縁物基板の一主表面に熱伝導性が良好な物
    質を含有したガラス層を形成する工程と （ｂ）上記ガラス層の上に集積回路基板をのせ、上記絶
    縁物基板と上記集積回路基板とを固着させる工程と からなることを特徴とする集積回路装置の製造方法。
JP13771785A 1985-06-26 1985-06-26 集積回路装置の製造方法 Pending JPS6127641A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13771785A JPS6127641A (ja) 1985-06-26 1985-06-26 集積回路装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13771785A JPS6127641A (ja) 1985-06-26 1985-06-26 集積回路装置の製造方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP7468279A Division JPS55166933A (en) 1979-06-15 1979-06-15 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6127641A true JPS6127641A (ja) 1986-02-07

Family

ID=15205173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13771785A Pending JPS6127641A (ja) 1985-06-26 1985-06-26 集積回路装置の製造方法

Country Status (1)

Country Link
JP (1) JPS6127641A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009083068A (ja) * 2007-10-02 2009-04-23 Eguro:Kk コイル状ワークを使用したｎｃ旋盤加工システムおよびコイル状ワークを使用したｎｃ旋盤加工方法
DE102013102058B4 (de) 2012-03-01 2024-05-29 Infineon Technologies Ag Chipanordnungen und Verfahren zum Bilden einer Chipanordnung

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5046484A (ja) * 1973-08-30 1975-04-25
JPS5013554B1 (ja) * 1968-03-24 1975-05-20
JPS535981A (en) * 1976-07-06 1978-01-19 Toyoda Chuo Kenkyusho Kk Method of producing semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5013554B1 (ja) * 1968-03-24 1975-05-20
JPS5046484A (ja) * 1973-08-30 1975-04-25
JPS535981A (en) * 1976-07-06 1978-01-19 Toyoda Chuo Kenkyusho Kk Method of producing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009083068A (ja) * 2007-10-02 2009-04-23 Eguro:Kk コイル状ワークを使用したｎｃ旋盤加工システムおよびコイル状ワークを使用したｎｃ旋盤加工方法
DE102013102058B4 (de) 2012-03-01 2024-05-29 Infineon Technologies Ag Chipanordnungen und Verfahren zum Bilden einer Chipanordnung

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