JPS61265647A - Data transferring system - Google Patents

Data transferring system

Info

Publication number
JPS61265647A
JPS61265647A JP10797085A JP10797085A JPS61265647A JP S61265647 A JPS61265647 A JP S61265647A JP 10797085 A JP10797085 A JP 10797085A JP 10797085 A JP10797085 A JP 10797085A JP S61265647 A JPS61265647 A JP S61265647A
Authority
JP
Japan
Prior art keywords
data
address
memory
signal
output terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10797085A
Other languages
Japanese (ja)
Inventor
Akira Nishimura
彰 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP10797085A priority Critical patent/JPS61265647A/en
Publication of JPS61265647A publication Critical patent/JPS61265647A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To transfer simultaneously data to one piece or more of memories, and to shorten the transfer time, by a simple and inexpensive method, by providing a means for outputting a selecting signal by bringing an output of an address decoder to OR. CONSTITUTION:In case when data stored in a memory part 16 is transferred to a memory part 15 and a memory part 17, a MPU part 11 sends out an address signal outputted to an output terminal 1 of an address decoder part 12, makes a SEL 2 signal LOW and sets a memory part 16 to an active state, and reads out data from a prescribed address. Subsequently, the address signal is switched to the contents outputted to an output terminal 3 of the decoder part 12, a LOW signal is inputted to OR circuits 13, 14, SEL 1, 3, signals are made LOW, the memory parts 15, 17 are set to an active state, and readout data is written in a prescribed address simultaneously. Also, when only the memory parts 15, 17 are set to an active state, and the data is read/written, an address signal outputted to an output terminal 0 or 2 of the decoder part 12 is used.

Description

【発明の詳細な説明】 技術分野 本発明はデータ転送方式に関し、特に複数のメモリを有
するマイクロプロセッサ応用システムにおいて、メモリ
へのデータ転送を時間短縮するのに好適なデータ転送方
式に関するものである。TECHNICAL FIELD The present invention relates to a data transfer method, and more particularly to a data transfer method suitable for shortening the time required to transfer data to a memory in a microprocessor application system having a plurality of memories.

従来技術 従来、複数個のメモリを有しているマイクロプロセッサ
応用システムにおいては、上記複数個のメモリを各々に
セレクト（バンク切替え）するために、アドレス信号を
デコードするアドレスデコーダを具備している。本シス
テムにおいて例えばメモリ＃１からメモリ＃２にデータ
転送する場合は。BACKGROUND ART Conventionally, a microprocessor application system having a plurality of memories is equipped with an address decoder that decodes an address signal in order to select (bank switch) each of the plurality of memories. In this system, for example, when data is transferred from memory #1 to memory #2.

マイクロプロセッサが、先ず、アドレスデコーダを介し
てメモリ＃１を指定し、所定のアドレスからデータを読
出した後、その読出データをアドレスデコーダを介して
メモリ＃２を指定し、所定のアドレスに書込んでいる。The microprocessor first specifies memory #1 via the address decoder, reads data from a predetermined address, and then specifies memory #2 via the address decoder and writes the read data to the predetermined address. I'm here.

しかしながら、例えば、メモリ＃１からメモリ＄２．　
＃３にデータ転送する場合も、マイクロプロセッサが上
記と同様の方法によりメモリ＃１からデータを読出した
後、そのデータを始めにメモリ＃２に書込み、次にメモ
リ＃３に書込んでいるために、転送するデータ量が多く
なると、転送に要する時間が長くなってシステム全体の
処理能力を低下させていた。However, for example, from memory #1 to memory $2.
When transferring data to #3, the microprocessor reads data from memory #1 using the same method as above, and then writes that data first to memory #2 and then to memory #3. Furthermore, as the amount of data to be transferred increases, the time required for transfer increases, reducing the processing capacity of the entire system.

目　　　　　的 本発明の目的は、このよう、な従来の間πを解決し、複
数個のメモリを有するマイクロプロセッサ応用システム
において、簡単かつ安価な方法により、データを同時に
１個以上の上記メモリに転送して転送の時間を短縮する
ことのできるデータ転送方式を提供することにある。OBJECTIVES It is an object of the present invention to solve this conventional problem and to transfer data to one or more of the above-mentioned memories simultaneously in a microprocessor application system having a plurality of memories in a simple and inexpensive manner. An object of the present invention is to provide a data transfer method that can shorten transfer time.

構　　　成 本発明は、上記の目的を達成するため、各種データを記
憶するメモリを複数個有し、該メモリをアドレスデコー
ダによりセレクトするマイクロプロセッサ応用システム
において、上記アドレスデコーダの出力を論理和して上
記セレクト信号を出力する手段（ＯＲ回路４，５）を備
え、該手段の出力でセレクトした１個以上の上記メモリ
に上記データを転送することを特徴としたものである。Structure In order to achieve the above object, the present invention provides a microprocessor application system that has a plurality of memories for storing various data and selects the memories by an address decoder, in which the outputs of the address decoders are ORed and the The present invention is characterized in that it includes means (OR circuits 4 and 5) for outputting a selection signal, and the data is transferred to one or more of the selected memories using the output of the means.

以下、本発明の一実施例に基づいて具体的に説明する。Hereinafter, a detailed explanation will be given based on one embodiment of the present invention.

第１図は本発明の一実施例を示すマイクロプロセッサ応
用システムの構成図である。同図において、１１は本シ
ステムの全体処理を行うマイクロプロセッサ（ＭＰＵ）
部、１２はアドレス信号の一部をデコードするアドレス
デコーダ部、１３．１４はアドレスデコーダ部１２の出
力端Ｏ〜３からの出力を論理和するＯＲ回路、１５〜１
７はセレクト信号５ＥＬＬ〜３でアクティブ状態なるメ
モリ部である。なお、アドレスバスはアドレス信号を、
データバスは各種のデータ信号を、コントロール線はＲ
／Ｗ信号などを送り込むためのものである。FIG. 1 is a block diagram of a microprocessor application system showing one embodiment of the present invention. In the figure, 11 is a microprocessor (MPU) that performs the overall processing of this system.
12 is an address decoder section that decodes a part of the address signal; 13.14 is an OR circuit that ORs outputs from the output terminals O to 3 of the address decoder section 12; 15 to 1;
Reference numeral 7 denotes a memory section which is activated by select signals 5ELL to 5ELL. Note that the address bus carries address signals,
The data bus carries various data signals, and the control line is R.
This is for sending the /W signal etc.

今、メモリ部１６に格納しているデータをメモリ部１５
とメモリ部１７に転送する場合、ＭＰＵ部１１は、先ず
、アドレスデコーダ部１２の出力端１に出力されるアト
１ノス信号を送出し、５ＥＬ２信号を”Ｌｏｗ”にして
、メモリ部１６をアクティブ状態にし、所定のアドレス
からデータを読出す。The data currently stored in the memory unit 16 is transferred to the memory unit 15.
When transferring the information to the memory unit 17, the MPU unit 11 first sends out the At1NOS signal that is output to the output terminal 1 of the address decoder unit 12, sets the 5EL2 signal to “Low”, and activates the memory unit 16. state and read data from a predetermined address.

次に、アドレス信号をアドレスデコーダ部１２の出力端
３に出力する内容に切替えて、ＯＲ回路１３および１４
に”Ｌｏｗ”信号を入力し、５ＥＬＬおよび３信号を′
″ＬＯ％＋Ｈにして、メモリ部１５および１７をアクテ
ィブ状態にし、上記の続出データを所定のアドレスに同
時に書込む。Next, the content of the address signal is changed to be output to the output terminal 3 of the address decoder section 12, and the OR circuits 13 and 14
Input “Low” signal to 5ELL and 3 signal.
``LO%+H'', the memory sections 15 and 17 are activated, and the successive data mentioned above are simultaneously written to a predetermined address.

また、メモリ部１５あるいはメモリ部１７のみをアクテ
ィブ状態して、データをリード／ライトするときは、ア
ドレスデコーダ部１２の出力端Ｏあるいは出力端２に出
力されるアドレス信号を用いる。Further, when only the memory section 15 or the memory section 17 is activated to read/write data, the address signal outputted to the output terminal O or the output terminal 2 of the address decoder section 12 is used.

コノヨウに、アドレスデコーダ部１２の出力端３の出力
でメモリ部１５およびメモリ部１７をセレクトするＯＲ
回路１３．１４を設けたことで。In addition, an OR function that selects the memory section 15 and the memory section 17 with the output of the output terminal 3 of the address decoder section 12
By providing circuits 13 and 14.

データの同時転送が可能となり、転送に要する時間を従
来の約半分にすることができる。このことは転送するデ
ータ量が増加するに連れて短縮時間の絶対量が大きくな
るので、システム全体の処理能力を高めることが可能と
なる。Simultaneous data transfer is now possible, and the time required for transfer can be cut in half compared to conventional methods. This means that as the amount of data to be transferred increases, the absolute amount of time saved increases, making it possible to increase the processing capacity of the entire system.

効　　　果 以上説明したように１本発明によれば、複数のメモリを
有するマイクロプロセッサ応用システムにおいて、１個
以上の上記メモリへのデータ転送をアドレスデコーダの
出力を受けたＯＲ回路１３゜１４に１個以上の上記メモ
リをセレクトさせて行わせるので、特別な回路部品を用
いることなく、データの同時転送が可能となり、転送の
時間は短縮される。Effects As explained above, according to the present invention, in a microprocessor application system having a plurality of memories, data transfer to one or more of the memories is performed by one OR circuit 13, 14 receiving the output of an address decoder. Since more than one memory is selected, data can be transferred simultaneously without using special circuit components, and the transfer time is shortened.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を示すマイクロプロセッサ応
用システムの構成図である・ １１：マイクロプロセッサ（Ｍ　Ｐ　Ｕ）部、１２ニア
ドレスデコ一ダ部、１３，１４：ＯＲ回路、１５〜１７
：メモリ部。 特許出願人　株式会社リ　　コ　　− ／　　　−♂FIG. 1 is a configuration diagram of a microprocessor application system showing an embodiment of the present invention. 11: Microprocessor (MPU) section, 12 Near address decoder section, 13, 14: OR circuit, 15- 17
:Memory part. Patent applicant Rico Co., Ltd. − / −♂

Claims (1)

【特許請求の範囲】[Claims] （１）各種データを記憶するメモリを複数個有し、該メ
モリをアドレスデコーダによりセレクトするマイクロプ
ロセッサ応用システムにおいて、上記アドレスデコーダ
の出力を論理和して上記セレクト信号を出力する手段を
備え、該手段の出力でセレクトした１個以上の上記メモ
リに上記データを転送することを特徴とするデータ転送
方式。(1) A microprocessor application system having a plurality of memories storing various data and selecting the memories by an address decoder, comprising means for ORing the outputs of the address decoders and outputting the select signal; A data transfer method characterized in that the data is transferred to one or more of the memories selected by the output of the means.
JP10797085A 1985-05-20 1985-05-20 Data transferring system Pending JPS61265647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10797085A JPS61265647A (en) 1985-05-20 1985-05-20 Data transferring system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10797085A JPS61265647A (en) 1985-05-20 1985-05-20 Data transferring system

Publications (1)

Publication Number Publication Date
JPS61265647A true JPS61265647A (en) 1986-11-25

Family

ID=14472681

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10797085A Pending JPS61265647A (en) 1985-05-20 1985-05-20 Data transferring system

Country Status (1)

Country Link
JP (1) JPS61265647A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007102467A (en) * 2005-10-04 2007-04-19 Denso Corp Microcomputer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007102467A (en) * 2005-10-04 2007-04-19 Denso Corp Microcomputer

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