JPS6125221B2 - - Google Patents
Info
- Publication number
- JPS6125221B2 JPS6125221B2 JP53024651A JP2465178A JPS6125221B2 JP S6125221 B2 JPS6125221 B2 JP S6125221B2 JP 53024651 A JP53024651 A JP 53024651A JP 2465178 A JP2465178 A JP 2465178A JP S6125221 B2 JPS6125221 B2 JP S6125221B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating film
- titanium
- gold
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 239000004065 semiconductor Substances 0.000 claims description 24
- 238000007747 plating Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 12
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 20
- 239000010931 gold Substances 0.000 description 20
- 229910052737 gold Inorganic materials 0.000 description 20
- 229910052581 Si3N4 Inorganic materials 0.000 description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 13
- 239000010936 titanium Substances 0.000 description 13
- 229910052719 titanium Inorganic materials 0.000 description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 12
- 238000000034 method Methods 0.000 description 9
- UUWCBFKLGFQDME-UHFFFAOYSA-N platinum titanium Chemical compound [Ti].[Pt] UUWCBFKLGFQDME-UHFFFAOYSA-N 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 7
- FHUGMWWUMCDXBC-UHFFFAOYSA-N gold platinum titanium Chemical compound [Ti][Pt][Au] FHUGMWWUMCDXBC-UHFFFAOYSA-N 0.000 description 5
- 229910052697 platinum Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 241001310793 Podium Species 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- FZQYVWUONRVDQB-UHFFFAOYSA-N gold titanium tungsten Chemical compound [Ti][W][Au] FZQYVWUONRVDQB-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 150000003608 titanium Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Landscapes
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】
本発明は多層絶縁膜および多層金属膜により構
成される金属電極を有する半導体装置に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device having a metal electrode composed of a multilayer insulating film and a multilayer metal film.
高信頼性を有する半導体装置においては、その
電極用金属材料としてエレクトロマイグレーシヨ
ンなどの点において劣るアルミニウムに代わり、
金を主体とする、いわゆる金電極が広く採用され
るようになつている。そして電極構造として半導
体装置に一般に使用される絶縁膜との密着性の向
上およびシリコン基板などとの反応を防止するた
めにチタン−白金−金あるいはチタン−タングス
テン−金などの多層膜電極構造が用いられてい
る。 In highly reliable semiconductor devices, aluminum is used as the metal material for electrodes in place of aluminum, which is inferior in terms of electromigration, etc.
So-called gold electrodes, which are mainly made of gold, are becoming widely used. As an electrode structure, a multilayer electrode structure such as titanium-platinum-gold or titanium-tungsten-gold is used to improve adhesion with insulating films commonly used in semiconductor devices and to prevent reactions with silicon substrates. It is being
また、半導体装置の特性安定化（以下パツシベ
ーシヨンという）のため、シリコン基板上に設け
られる絶縁膜層として従来の熱酸化膜のみではな
く、気相成長法あるいはプラズマ内反応により成
長したシリコン窒化膜などを熱酸化膜上に成長さ
せ、熱酸化膜−シリコン窒化膜あるいは熱酸化膜
−シリコン窒化膜−シリコン酸化膜などの多層絶
縁膜構造が採用される。 In addition, in order to stabilize the characteristics of semiconductor devices (hereinafter referred to as passivation), insulating film layers provided on silicon substrates are not limited to conventional thermal oxide films, but also include silicon nitride films grown by vapor phase growth or plasma reactions. is grown on a thermal oxide film, and a multilayer insulating film structure such as a thermal oxide film-silicon nitride film or a thermal oxide film-silicon nitride film-silicon oxide film is adopted.
ところで、このような多層絶縁膜構造を採用す
る場合において、第１層の絶縁膜上に形成する第
２層以上の絶縁膜の成長時に、第１層の絶縁膜上
の汚れや、絶縁膜成長後の熱処理による熱歪など
が起因して第２層以上の絶縁膜と第１層の絶縁膜
との間に形成される段差部において第２層以上の
絶縁膜がめくれあがる場合がある。特に数層の絶
縁膜上に金電極の金層を金メツキ法により形成す
る場合に、この絶縁膜のめくれあがりのために金
メツキ導電パス用金属が断線し、金メツキ不着と
いう重大な歩留低下をもたらすという欠点があ
る。 By the way, when such a multilayer insulating film structure is adopted, when the second or higher insulating films formed on the first insulating film are grown, dirt on the first insulating film or growth of the insulating film may occur. Due to thermal strain caused by subsequent heat treatment, the insulating film of the second or higher layer may be turned up at the step portion formed between the insulating film of the second or higher layer and the first layer of the insulating film. Particularly when forming a gold layer for a gold electrode on several layers of insulating films by the gold plating method, the peeling of the insulating film can cause disconnection of the gold-plated conductive path metal, resulting in a serious yield loss due to non-adhesion of the gold plating. It has the disadvantage of causing a decline.
本発明は上記問題点を解消するもので、半導体
基板上に、まず第１層の絶縁膜を形成し、その上
面に形成する第２層以後の絶縁膜をその上方の金
を付着すべき電極状金属層の端縁より内方の一定
範囲にわたつてエツチング処理によりこれを除去
し、該第２層以上の絶縁膜層を金属層の範囲内に
内包させるもので、これによつてパツシベーシヨ
ン効果を失うことなく多層膜金属よりなる電極状
金属層と第１層の絶縁膜とを電気的に完全に接続
することを可能ならしめたことを特徴とするもの
である。 The present invention solves the above-mentioned problems. First, a first layer of insulating film is formed on a semiconductor substrate, and the second and subsequent insulating films formed on the upper surface of the first layer are used as electrodes to which gold is to be attached. This method removes a certain range inward from the edge of the shaped metal layer by etching process, thereby enclosing the second and higher insulating film layers within the range of the metal layer, thereby improving the passivation effect. The present invention is characterized in that it is possible to completely electrically connect the electrode-like metal layer made of a multilayer metal to the first layer insulating film without losing the electrical properties.
以下本発明の実施例を熱酸化膜および気相成長
により形成したシリコン窒化膜を有し、かつチタ
ン−白金−金多層膜電極を有する半導体装置に適
用した場合について説明する。 Hereinafter, a case will be described in which an embodiment of the present invention is applied to a semiconductor device having a thermal oxide film and a silicon nitride film formed by vapor phase growth, and a titanium-platinum-gold multilayer electrode.
本発明の実施例の説明に先立つて、基板上に多
層絶縁膜および多層金属膜により構成される金電
極を有する半導体装置の製造工程を説明すると次
のとおりである。 Prior to describing the embodiments of the present invention, the manufacturing process of a semiconductor device having a gold electrode formed of a multilayer insulating film and a multilayer metal film on a substrate will be described as follows.
第１図イにおいて、半導体基板１の表面にまず
第１層の絶縁膜となる熱酸化膜２を形成し、その
上面に気相成長により形成した第２層の絶縁膜と
なるシリコン窒化膜３を500〜1500Åの厚さに形
成し、その後第１および第２層の絶縁膜２，３の
一部に開孔４を形成し、前記半導体基板１にリン
またはポロンなどを拡散して基板１の一部に拡散
層１Ａを形成する。次に第１図ロに示すように開
孔４を通して前記拡散層１Ａにオーミツク接合の
ために白金硅化物の膜５を形成し、次に基板１、
熱酸化膜２および白金硅化物の膜５の表面全体は
約500Åの厚さで第１層の電極金属膜となるチタ
ン層６を蒸着法などの手段によつて形成する。 In FIG. 1A, a thermal oxide film 2, which will become a first layer insulating film, is first formed on the surface of a semiconductor substrate 1, and a silicon nitride film 3, which will become a second layer insulating film, is formed on the upper surface by vapor phase growth. is formed to a thickness of 500 to 1500 Å, and then holes 4 are formed in parts of the first and second layer insulating films 2 and 3, and phosphorus or poron is diffused into the semiconductor substrate 1 to form the substrate 1. A diffusion layer 1A is formed in a part of the area. Next, as shown in FIG.
On the entire surface of the thermal oxide film 2 and the platinum silicide film 5, a titanium layer 6 having a thickness of about 500 Å and serving as a first electrode metal film is formed by means such as vapor deposition.
このチタン層６は金メツキ導電パス用金属とし
て用いられ、メツキ後に他の金属層をマスクとし
てエツチングされるものである。第１図ハはその
上面にさらに公知のリフトアウエイ法によりチタ
ン−白金電極状金属層を形成した状態を示す。す
なわち、該電極状金属層はチタン層７と、その上
に形成した白金層８とからなり、チタン層７の膜
厚は約500Å、白金層８の膜厚は1000〜2000Åで
ある。通常、金層は粘性が大きく、リフトアウエ
イ法によるパターニングが困難なために、メツキ
法により成形されるのである。 This titanium layer 6 is used as a gold-plated conductive path metal, and after plating is etched using another metal layer as a mask. FIG. 1C shows a state in which a titanium-platinum electrode-like metal layer is further formed on the upper surface by a known lift-away method. That is, the electrode-like metal layer consists of a titanium layer 7 and a platinum layer 8 formed thereon, the titanium layer 7 having a thickness of about 500 Å, and the platinum layer 8 having a thickness of 1000 to 2000 Å. Usually, the gold layer has a high viscosity and is difficult to pattern using the lift-away method, so it is formed using the plating method.
第１図ニはチタン−白金電極状金属層以外の部
分をフオトレジスト９によりマスクしてチタン層
６を導電パスとし、金メツキ液中において金メツ
キを行い、その表面に3000〜10000Åの金層１０
を形成した状態を示す。さらに第１図ホはフオト
レジスト９およびチタン−白金電極状金属層に接
する部分以外のチタン層６を除去した状態であ
り、通常の形式のチタン−白金−金電極１１を有
する半導体装置を示す。 In Figure 1D, parts other than the titanium-platinum electrode-like metal layer are masked with a photoresist 9, the titanium layer 6 is used as a conductive path, and gold plating is performed in a gold plating solution. 10
This shows the state in which it has been formed. Furthermore, FIG. 1E shows a semiconductor device having a conventional titanium-platinum-gold electrode 11, with the photoresist 9 and the titanium layer 6 other than the portions in contact with the titanium-platinum electrode metal layer removed.
上記工程を経て得られた半導体装置は、第１図
イ，ロに示すシリコン窒化膜３の成長時に、熱酸
化膜２上の汚れや、同工程中で行われる拡散など
の処理に伴う高温熱処理のために第２図イに示す
ように熱酸化膜２上に形成されたシリコン窒化膜
３がその端縁よりめくれあがる場合が生ずるので
ある。このような欠陥が生じた場合には第２図ロ
に示すように第１図ロの処理で形成されたメツキ
導電パス用チタン層６が熱酸化膜２とシリコン窒
化膜３との段差部において断線し、その上方に形
成するチタン−白金電極状金属層上に金メツキを
することが不可能となるのである。 The semiconductor device obtained through the above steps is free from dirt on the thermal oxide film 2 during the growth of the silicon nitride film 3 shown in FIG. Therefore, as shown in FIG. 2A, the silicon nitride film 3 formed on the thermal oxide film 2 may curl up from its edges. If such a defect occurs, as shown in FIG. 2B, the plating conductive path titanium layer 6 formed by the process shown in FIG. The wire breaks, and it becomes impossible to gold plate the titanium-platinum electrode-like metal layer formed above it.
本発明は第３図イに示すように、半導体基板１
上に設けた第１の絶縁膜層となる熱酸化膜２上に
第２の絶縁膜層となるシリコン窒化膜３を形成し
このシリコン窒化膜３が半導体装置の外部からそ
の上方に形成するチタン−白金電極状金属層７，
８の範囲内に内包されるように該チタン−白金電
極状金属層７，８の端縁より内方にまでこれをエ
ツチング処理によつて除去し、その除去面に熱酸
化膜２を露呈させ、第１図ロの工程で成形したチ
タン層６とチタン−白金電極状金属層７，８とを
完全に導通させ、このチタン層６を通してチタン
−白金電極状金属層７，８上に確実に金メツキを
行うものである。 As shown in FIG.
A silicon nitride film 3 which becomes a second insulating film layer is formed on a thermal oxide film 2 which becomes a first insulating film layer provided above, and this silicon nitride film 3 is made of titanium that is formed above it from outside the semiconductor device. - platinum electrode-like metal layer 7,
The titanium-platinum electrode-like metal layers 7 and 8 are removed by etching to the inner side from the edges so as to be included within the range 8, and the thermal oxide film 2 is exposed on the removed surface. , the titanium layer 6 formed in the process of FIG. It is used for gold plating.
第３図ロに第１図ホに対応する完成時の状態を
示す。 FIG. 3(b) shows the completed state corresponding to FIG. 1(e).
したがつて、本発明によればシリコン窒化膜３
がチタン−白金電極状金属層７，８に内包され、
シリコン窒化膜３上を覆つてチタン層６の上方よ
りチタン−白金電極状金属層７，８を形成したた
めに例えばシリコン窒化膜３がめくれあがつたと
しても、接続不良が生ぜず、金メツキの付着不良
を完全になくし、半導体製品の歩留りを向上させ
ることができる。さらに、シリコン窒化膜３のエ
ツチングの範囲を電極状金属層７，８のポデイパ
ツド部にまでエツチングにより除去して熱酸化膜
２を露呈させることによつてパツシベーシヨン効
果が損なわれることなく、またプロセス的にも極
めて安定した半導体装置を製造することができ
る。 Therefore, according to the present invention, the silicon nitride film 3
is included in the titanium-platinum electrode-like metal layers 7 and 8,
Since the titanium-platinum electrode-like metal layers 7 and 8 are formed over the silicon nitride film 3 from above the titanium layer 6, for example, even if the silicon nitride film 3 is peeled up, a connection failure will not occur and the gold plating will not be damaged. It is possible to completely eliminate adhesion defects and improve the yield of semiconductor products. Furthermore, by etching away the silicon nitride film 3 to the podium pad portions of the electrode metal layers 7 and 8 to expose the thermal oxide film 2, the passivation effect is not impaired, and the process is improved. It is also possible to manufacture extremely stable semiconductor devices.
第４図は本発明半導体装置を熱酸化膜２とシリ
コン窒化膜３とを有するストライブ型マイクロ波
トランジスタに応用した例を示す。すなわち、本
実施例ではトランジスタチツプの外部からチタン
−白金−金電極層１２のボデイングパツド部の一
部下方に至るまで熱酸化膜２を露呈させており、
これによつてチタン−白金電極層１２が再現性よ
く確実に成形することができるものである。 FIG. 4 shows an example in which the semiconductor device of the present invention is applied to a stripe type microwave transistor having a thermal oxide film 2 and a silicon nitride film 3. That is, in this embodiment, the thermal oxide film 2 is exposed from the outside of the transistor chip to a portion below the body pad portion of the titanium-platinum-gold electrode layer 12.
This allows the titanium-platinum electrode layer 12 to be reliably formed with good reproducibility.
本発明は以上のように、半導体基板上に第１の
絶縁膜層と、少なくとも第２の絶縁膜層を順次形
成し、この上面にさらに金を含む多層膜金属層に
より構成する電極を備えた半導体装置の外部から
多層膜金属の電極層の下方に延長して第２層以上
の絶縁膜をエツチング処理によつて除去すること
によつて第２層以上の絶縁膜を電極層内に内包さ
せ、その上方にチタン層並びに金電極層を形成す
るために製造工程中における絶縁層の剥離に伴う
金メツキ不着という重大な欠陥の発生を完全にな
くし、製品の歩留りを従来に比して飛躍的に向上
することができる効果を有するものである。 As described above, the present invention comprises sequentially forming a first insulating film layer and at least a second insulating film layer on a semiconductor substrate, and further comprising an electrode formed of a multilayer metal layer containing gold on the upper surface thereof. The second or higher insulating film is included in the electrode layer by extending from the outside of the semiconductor device below the multilayer metal electrode layer and removing the second or higher insulating film by etching. In order to form a titanium layer and a gold electrode layer above the titanium layer, we completely eliminate the occurrence of serious defects such as non-adhesion of gold plating due to peeling of the insulating layer during the manufacturing process, and dramatically increase the yield of products compared to conventional methods. It has the effect that it can be improved.
また、本発明は以上実施例に限らず多層金属膜
により形成される金電極を有する一般の半導体装
置に広く適用することができる。 Further, the present invention is not limited to the above embodiments, but can be widely applied to general semiconductor devices having gold electrodes formed of multilayer metal films.
第１図イ〜ホは半導体装置の製造工程を示す説
明図、第２図イ，ロは従来の製造工程中に生ずる
問題点を示す半導体装置の断面図、第３図イは本
発明半導体装置の一実施例を示す製造工程の途中
の縦断面図、ロは完成時の縦断面図、第４図は本
発明の応用例を示すストライプ型マイクロ波トラ
ンジスタの要部斜視図である。
図において、１……半導体基板、２……熱酸化
膜、３……シリコン窒化膜、６，７……チタン
層、８……白金層、１０……金層、１１……金電
極、１２……チタン−白金−金多層膜電極層であ
る。
1A to 1E are explanatory diagrams showing the manufacturing process of a semiconductor device, FIGS. 2A and 2B are cross-sectional views of a semiconductor device showing problems that occur during the conventional manufacturing process, and FIG. 3A is a semiconductor device of the present invention. FIG. 4 is a vertical cross-sectional view in the middle of the manufacturing process showing one embodiment of the present invention, B is a vertical cross-sectional view at the time of completion, and FIG. In the figure, 1... semiconductor substrate, 2... thermal oxide film, 3... silicon nitride film, 6, 7... titanium layer, 8... platinum layer, 10... gold layer, 11... gold electrode, 12 ...It is a titanium-platinum-gold multilayer electrode layer.
Claims (1)
基板上に形成し、前記第１の絶縁膜上に第２の絶
縁膜を選択的に形成する工程と、前記コンタクト
穴を介して前記基板の一部に接触し前記第１およ
び第２の絶縁膜をこえて前記基板の他の一部に延
在するメツキ用導電パスとして第１の導体層を形
成する工程と、前記コンタクト穴における前記第
１の導体層の部分から前記第２の絶縁膜の外周の
少なくとも一部をこえた箇所における前記第１の
金属導体層の部分まで第２の導体層を形成する工
程と、前記第１の金属導体層をメツキ用導電パス
として前記第２の導体層のほぼ全面にメツキ導体
を形成する工程と、前記第２の導体層をマスクと
して前記第１導体層を選択エツチングする工程と
を有する半導体装置の製造方法。1. Forming a first insulating film having a contact hole on a semiconductor substrate, selectively forming a second insulating film on the first insulating film, and forming one of the substrates through the contact hole. forming a first conductive layer as a conductive path for plating that contacts the first and second insulating films and extends to another part of the substrate; forming a second conductor layer from a portion of the conductor layer to a portion of the first metal conductor layer beyond at least a portion of the outer periphery of the second insulating film; A semiconductor device comprising the steps of forming a plating conductor on almost the entire surface of the second conductor layer using the layer as a conductive path for plating, and selectively etching the first conductor layer using the second conductor layer as a mask. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2465178A JPS54117680A (en) | 1978-03-03 | 1978-03-03 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2465178A JPS54117680A (en) | 1978-03-03 | 1978-03-03 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS54117680A JPS54117680A (en) | 1979-09-12 |
| JPS6125221B2 true JPS6125221B2 (en) | 1986-06-14 |
Family
ID=12144034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2465178A Granted JPS54117680A (en) | 1978-03-03 | 1978-03-03 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54117680A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10941251B2 (en) | 2018-03-22 | 2021-03-09 | Momentive Performance Materials Inc. | Silicone polymer and composition comprising the same |
| US10968351B2 (en) | 2018-03-22 | 2021-04-06 | Momentive Performance Materials Inc. | Thermal conducting silicone polymer composition |
| US11319414B2 (en) | 2018-03-22 | 2022-05-03 | Momentive Performance Materials Inc. | Silicone polymer |
| US11472925B2 (en) | 2018-03-22 | 2022-10-18 | Momentive Performance Materials Inc. | Silicone polymer |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6112045A (en) * | 1984-06-28 | 1986-01-20 | Oki Electric Ind Co Ltd | Formation of bump electrode |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52131455A (en) * | 1976-04-28 | 1977-11-04 | Hitachi Ltd | Semiconductor device |
-
1978
- 1978-03-03 JP JP2465178A patent/JPS54117680A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52131455A (en) * | 1976-04-28 | 1977-11-04 | Hitachi Ltd | Semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10941251B2 (en) | 2018-03-22 | 2021-03-09 | Momentive Performance Materials Inc. | Silicone polymer and composition comprising the same |
| US10968351B2 (en) | 2018-03-22 | 2021-04-06 | Momentive Performance Materials Inc. | Thermal conducting silicone polymer composition |
| US11319414B2 (en) | 2018-03-22 | 2022-05-03 | Momentive Performance Materials Inc. | Silicone polymer |
| US11472925B2 (en) | 2018-03-22 | 2022-10-18 | Momentive Performance Materials Inc. | Silicone polymer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS54117680A (en) | 1979-09-12 |
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