JPS61251039A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61251039A JPS61251039A JP60089915A JP8991585A JPS61251039A JP S61251039 A JPS61251039 A JP S61251039A JP 60089915 A JP60089915 A JP 60089915A JP 8991585 A JP8991585 A JP 8991585A JP S61251039 A JPS61251039 A JP S61251039A
- Authority
- JP
- Japan
- Prior art keywords
- surface charge
- charge density
- glass
- groove
- annular grooves
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は高耐圧の半導体装置に係り、臀に高耐圧化の九
めにユニサーフエース・ダブルモート構造を採用した半
導体基体のバツシベーヨヨン（表面安定化）に関する。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device with a high breakdown voltage. related to
との檎半纒体装叙はサイリスタに適用されることが多い
ので、以下、サイリスタに於ける半導体基体を例に採っ
て説明する。Since the semicircular body mounting described above is often applied to thyristors, the semiconductor substrate in the thyristor will be explained below as an example.
サイリスタなどは電力変換装置への応用が活発で、その
ため、高耐圧化が大きな命題の一つとなっている。Thyristors and other devices are being actively applied to power conversion devices, and one of the major challenges for this is to increase their voltage resistance.
そして、このような高耐圧化に対する回答として与えら
れている半導体構造の一つに、いわゆるユニサーフェイ
ス・ダブルモート構造がある。One of the semiconductor structures that has been proposed as an answer to such high breakdown voltage requirements is the so-called unisurface double moat structure.
そこで、第２図に、このような従来のサイリス′りの半
導体基体の一例を示す。この第２図において、半導体基
体１は上側主表面２と下側主表面３を有し、この間に、
隣接相互で導電型が異なる４層の半導体層、即ちＰ鳶層
４．Ｎｍ層５．Ｐａ層６．Ｎ鳶層７を有している。FIG. 2 shows an example of such a conventional silis-based semiconductor substrate. In FIG. 2, a semiconductor body 1 has an upper main surface 2 and a lower main surface 3, between which
Four adjacent semiconductor layers having different conductivity types, ie, P layer 4. Nm layer5. Pa layer 6. It has an N layer 7.
２１層４〜Ｎｘｌ＠ｉ ７ ｔｄ、 Ｐ Ｎ 接合Ｊｓ
〜Ｊｓ ｔ 形成シ”Ｃいる。上側主表面２には２個
の環状溝８，９が同心円状に設けられ、外溝８の外周壁
部にＰＮ接合Ｊ、の端部が露出し、内溝９の内周壁にＰ
Ｎ接合Ｊ。21 layer 4~Nxl@i 7 td, P N junction Js
〜Js t Formation "C". Two annular grooves 8 and 9 are provided concentrically on the upper main surface 2, and the end of the PN junction J is exposed on the outer peripheral wall of the outer groove 8, and the inner P on the inner peripheral wall of groove 9
N-junction J.
の端部が露出している。なお、この構造は、これら両溝
８，９が上側玉表面２に同心的に設けられていることか
ら、上記しｍようにユニサーフエース・ダブルモート構
造と呼称されているのである。The end of the is exposed. This structure is called the Unisurf Ace double moat structure as described above because both grooves 8 and 9 are provided concentrically on the upper ball surface 2.
ＰＮ接合Ｊ３は上側主表面２に露出している。PN junction J3 is exposed on upper main surface 2.
−万、こレラの＃８．９にはパッシベーション材として
ガラス１０．１１が焼結されてＰＮ接合Ｊ１ｍＪ、のパ
ッシベーションをしている。-10,000, Glass 10.11 is sintered as a passivation material in #8.9 of Korera to passivate the PN junction J1mJ.
ところでこのパッシベーション材となるガラス１１Ｊ、
１１には、その電荷がＮ型シリコンの電子密反ｔ−減少
させたり、またはそれをＰａ！に反転させたりするもの
（以下、これを負の表面電荷密度を有するものと呼ぶ）
と、ＰｆＪｌシリコンの正孔密度を減少させたり、また
はそれをＮｍに反転させたりするもの（以下、これを正
の表面電荷密度を有するものと呼ぶ）とがある。By the way, glass 11J, which is the passivation material,
11, the charge reduces the electron density of N-type silicon, or makes it Pa! (hereinafter referred to as having a negative surface charge density)
There are also those that reduce the hole density of PfJl silicon or invert it to Nm (hereinafter referred to as those that have a positive surface charge density).
上側主表面の２１層６にはゲート電極１２が、そしてＮ
１層７にはカソード電極１３がそれぞれオーミックコン
タクトされており、その他の部分にはシリコン酸化膜１
４が設けられている。一方、下側主表面３にはアノード
電極１５が設けられている。さらに、溝８．９の間には
Ｎｕの高不純物濃度領域１６がチャンネル・ストッパー
として設けられている。The 21st layer 6 on the upper main surface has a gate electrode 12 and an N
Cathode electrodes 13 are in ohmic contact with each layer 7, and a silicon oxide film 1 is provided on the other parts.
4 are provided. On the other hand, an anode electrode 15 is provided on the lower main surface 3. Further, between the trenches 8.9, a highly doped region 16 of Nu is provided as a channel stopper.
カソード電極１３に対してアノード電極１５が正電位と
なるような順方向電圧を印加したときには、ＰＮ接合Ｊ
、が耐圧を維持し、このときカソード電極１３に対して
ゲート電極１２が正電位となるようにゲート電圧を加え
ると、半導体基体１はオン状態に移行する。When a forward voltage is applied such that the anode electrode 15 has a positive potential with respect to the cathode electrode 13, the PN junction J
maintains a breakdown voltage, and when a gate voltage is applied so that the gate electrode 12 has a positive potential with respect to the cathode electrode 13, the semiconductor substrate 1 shifts to the on state.
アノード電Ｑ１５に対してカソード％＝ １２が正電位
となるような逆方向電圧を印加した時、ＰＮ接合Ｊｉが
大部分の耐圧を維持している。When a reverse voltage such that the cathode %=12 becomes a positive potential with respect to the anode voltage Q15 is applied, the PN junction Ji maintains most of the withstand voltage.
第３図は第２図の要部を拡大して、電圧阻止時の状態を
示し九ものであり、この第３図において第２図と同一物
には同一符号を付けている。FIG. 3 is an enlarged view of the essential parts of FIG. 2 to show the state at the time of voltage blocking. In FIG. 3, the same parts as in FIG. 2 are given the same reference numerals.
順方向電圧阻止はＰＮ接合Ｊ、で行っており、この時、
Ａで示す領域（点を付けた領域）に空乏層が形成される
。順方向電圧阻止状態で電界強度が最大となる場所はａ
で示す付近である。ガラス１１として正の表面電荷密度
を持つものを用いた場合。Forward voltage blocking is performed by a PN junction J, and at this time,
A depletion layer is formed in the region indicated by A (dotted region). The location where the electric field strength is maximum in the forward voltage blocking state is a
It is around the area shown by . When glass 11 having a positive surface charge density is used.
電圧が高まるにつれて空乏層は溝９の底を外周側に向っ
て延びるが、ガラス１１が正の表面電荷密度を持つため
、空乏層は延びにくい。そして、′電圧を高くするに従
い、ａ付近の電界強度は大きくなり、それが２００〜３
００ ＫＶ／ｃｍに達するとブレークオーバする。一方
、ガラス１１とし℃負の表面電荷密度を持つものを用い
た場合、空乏層は溝９の底を外周側に向って延び易くな
り、点線にて示す領域Ｂまで延び、チャンネル・ストッ
パー１６への到達が竿くなってチャンネル・ストッパー
１６へ到達した後は空乏層は＠８の方向へは延びずらく
なり、このためｂにて示す付近の電界強度が大きくなっ
てくる。更に′１圧を高くするとａ、ｂいずれかの付近
の′電界強度が例えば２００〜３００ＫＶ／ｃｍになっ
て、早く到達した方でブレークオーバが起る。As the voltage increases, the depletion layer extends from the bottom of the groove 9 toward the outer periphery, but because the glass 11 has a positive surface charge density, the depletion layer does not easily extend. As the voltage increases, the electric field strength near a increases, and it increases from 200 to 3
Breakover occurs when it reaches 00 KV/cm. On the other hand, when a glass 11 having a negative surface charge density of 0.degree. After reaching the channel stopper 16, the depletion layer becomes difficult to extend in the direction @8, and as a result, the electric field strength near b becomes large. If the '1 voltage is further increased, the electric field strength near either a or b becomes, for example, 200 to 300 KV/cm, and the one that reaches it earlier causes breakover.
この様に溝９では負の表面電荷ＹＢ度ｋＮつパッシベー
ション材を用いると、阻止゛電圧は高くなる。In this way, if a passivation material having a negative surface charge of YB degree kN is used in the groove 9, the blocking voltage becomes high.
一方、ＰＮ接合Ｊ１の方をみると、逆方向′電圧阻止の
場合に同様なことが起るが、ＰＮ接合Ｊ、とは異なり、
ＰＮ接合Ｊ、はＮｍ）１５内にできる空乏層にとっては
負の曲率凡になっているため、低い電圧で空乏層が一点
鎖緘で示すようにチャンネル・ストッパー１６に達して
しまう。こうして空乏層がチャンネル・ストッパー１６
に達した後は、Ｃ付近で強電界部が発生し、順方向阻止
電圧より低い電圧で電界強度が例えば２００〜３００
ＫＶ ／ ｃｍにもなり、＃９のパッシベーション材１
１と同じ貝の表面゛電荷密度を持つパッシベーション材
では、逆方向電圧に対しては有効ではない。On the other hand, looking at the PN junction J1, a similar thing occurs in the case of reverse voltage blocking, but unlike the PN junction J,
Since the depletion layer formed in the PN junction J, (Nm) 15 has a negative curvature, the depletion layer reaches the channel stopper 16 at a low voltage, as shown by the dot chain. In this way, the depletion layer becomes the channel stopper 16.
After reaching , a strong electric field is generated near C, and the electric field strength is, for example, 200 to 300 at a voltage lower than the forward blocking voltage.
KV/cm, #9 passivation material 1
A passivation material having the same shell surface charge density as No. 1 is not effective against reverse voltage.
従って％従来は＃＄８には正の表［ＩＤ′ｇＬ荷密度を
有するガラス１０が、又溝９には負の表面電荷密度ｔ有
するガラス１１がパッシベーション材としてそれぞれ充
填されてい友。なお、このような従来の半導体装置につ
いては、例えば特開昭５８−１１１３２２号公報に島示
がある。Therefore, conventionally #$8 is filled with glass 10 having a positive surface charge density [ID'gL, and groove 9 is filled with glass 11 having a negative surface charge density t as a passivation material. Note that such a conventional semiconductor device is described in, for example, Japanese Unexamined Patent Publication No. 111322/1983.
しかしながら、このような半導体嚢体の製造工程として
は、以下に示すものが従来から主として採用ちれている
。即ち、先ずＮｆｆ１シリコン単結晶ウエハが用意され
る。次に、公知の返択拡散技術を用いて、図示の接合形
状を持つＰＮＮ接合型１〜Ｊａ成する。その後、古９を
公知の選択エツチング法により設け、ここに、例えばＰ
ｂ糸ガラス粉末を公知の電気法１１１Ｊ＠．沈降法ある
いはドクターブレード法により堆積させ、ついで約８０
０〜８５０ Ｃで焼付けＣ負の表面電荷密度を有するガ
ラス１１を得る。However, as a manufacturing process for such a semiconductor envelope, the following has been mainly adopted in the past. That is, first, an Nff1 silicon single crystal wafer is prepared. Next, using a known return diffusion technique, PNN junction types 1 to Ja having the illustrated junction shapes are formed. Thereafter, an old layer 9 is provided by a known selective etching method, and here, for example, P
B yarn glass powder was processed by the known electric method 111J@. Deposited by sedimentation method or doctor blade method, then about 80%
Baking at 0-850 C gives a glass 11 with a negative surface charge density.
久に同様に公知の選択エツチング法を用いて、綽８を設
けここに、例えばＺｎＯ系ガラスの粉末を同様な上記公
知手ｔＳｔ金用いて堆積させて、約６５０〜７００Ｃで
焼付けて正の表面電荷密度を有するガラス１０を得る。Similarly, using a well-known selective etching method, a cage 8 is provided, and powder of, for example, ZnO-based glass is deposited thereon using the same well-known technique as described above, and baked at about 650 to 700 C to form a positive surface. A glass 10 having a charge density is obtained.
これは、Ｐｂ系ガラスとＺｎＯ系ガラスの軟化温度焼付
温度に差があり、また焼付後に正負いずれかの表面電荷
密度を持つことを利用したものであるが、２種類のパッ
シベーション材を使用するため、パッシベーション製造
工程が一鴇類のガラスを使用するのに対し２倍の工程数
が必要となる。また、溝９ヘパツシベーション材１１を
焼付けた後に溝８及ヒハツシベーション材１０ヲ設ける
ため、パッシベーション材１１へのエツチング液及び２
度焼きの影曽によるパッシベーション材１１の表面′＃
ｋＬｍ密ｉの変化が問題となる。This takes advantage of the fact that there is a difference in the softening temperature and baking temperature of Pb-based glass and ZnO-based glass, and that they have either a positive or negative surface charge density after baking, but since two types of passivation materials are used, , the passivation manufacturing process requires twice the number of steps compared to using a single piece of glass. In addition, in order to provide the groove 8 and the passivation material 10 after baking the passivation material 11 into the groove 9, an etching solution and a
Surface of passivation material 11 due to the shadow of degree firing
Changes in kLm density i become a problem.
従つ【、上記した従来の半導体装置では、その製造工程
が′４Ｌ細で，しかも充分な耐圧特性を得るのが困難で
あるという欠点があった。Therefore, the above-mentioned conventional semiconductor device has the disadvantage that its manufacturing process is very detailed and it is difficult to obtain sufficient breakdown voltage characteristics.
本発明の目的は、上記し次従来技術の欠点を除き、効率
的なパッシベーション機能ヲ備えて順方向逆方向共に充
分な阻止電圧を与え、しかも製造工程が簡単な半導体装
置を提供するにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which eliminates the above-mentioned drawbacks of the prior art, has an efficient passivation function, provides sufficient blocking voltage in both forward and reverse directions, and has a simple manufacturing process.
この目的を達成するため、本発明は、ユニサーフエース
・ダブルモート構造の２個の塊状溝の一方と他方とで、
そこに充填すべきパッシベーション材の充填厚さ金変え
、これにより同一極性の表面′電荷密度を有するパッシ
ベーション材を用いても充分な耐圧が与えられるように
した点’ｔ＊ｍとする。To achieve this objective, the present invention provides that, in one and the other of the two block grooves of the Unisurf Ace double moat structure,
A point 't*m' is defined as a point 't*m' where the filling thickness of the passivation material to be filled therein is changed so that a sufficient withstand voltage can be provided even if passivation materials having the same polarity and surface charge density are used.
以下５本発明による半導体装置について、図示の実施例
により詳細に説明する。Hereinafter, five semiconductor devices according to the present invention will be explained in detail with reference to illustrated embodiments.
第１図は本発明の一実施例による半導体基体１の置部拡
大図で、図において、８０．９０は塊状溝、１００、
１１０はパッシベーション材であり、その他第２図，
第３図に示すものと同一物，相当物には同一符号を付け
ている。FIG. 1 is an enlarged view of the placement part of a semiconductor substrate 1 according to an embodiment of the present invention.
110 is a passivation material, and the others shown in Fig. 2,
Components that are the same or equivalent to those shown in FIG. 3 are given the same reference numerals.
また、第４図には、本発明の一実施例において（５１ｉ
７ｆ４するＺｎＯ，系ガラスのガラス厚と表面％荷密度
の関係を表わすグラフを示す。FIG. 4 also shows that in one embodiment of the present invention (51i
A graph showing the relationship between glass thickness and surface % loading density of 7f4 ZnO-based glass is shown.
第１図において、＠９０には負の表面電荷密度を有する
パッシベーション材であるガラスｌ］１０が。In FIG. 1, glass l]10, which is a passivation material having a negative surface charge density, is placed at @90.
七の表面電荷密度が２ＸｌＯｃｍ となる様第４図よ
り（至）μｍの厚さに充填されている。As shown in FIG. 4, it is filled to a thickness of (up to) μm so that the surface charge density of the layer becomes 2XlOcm.
一方、ｔ＃８０には表面電荷密度を正極側に近ずけるた
めに、パッシベーション材としてのガラス１００は、そ
の表面電荷密度がＯＸｌｏｃｍ となる様にガラス１
１０と同一材質のガラスを第４図より１０μｍの厚さで
充填されている。On the other hand, at t#80, in order to bring the surface charge density closer to the positive electrode side, glass 100 as a passivation material is used so that the surface charge density becomes OXlocm.
As shown in FIG. 4, it is filled with glass made of the same material as No. 10 to a thickness of 10 μm.
こうして、いま、順方向電圧が印加された時、Ｐｎ接合
Ｊ，では、空乏層の地びが良くチャンネル・ストッパー
１６に到達し易くなっている。ま九逆方向電圧が印加さ
れた時、Ｐ Ｎ接合Ｊ，では、空乏層にとって負の曲軍
凡があるため構造的に空乏層がチャンネル・ストッパー
１６に到達し易いのであるが表面電荷密度がほぼ０とな
るガラス１００のために、空乏層が延びにくくされてい
る。In this way, when a forward voltage is applied now, the depletion layer of the Pn junction J is well-developed and easily reaches the channel stopper 16. When a reverse voltage is applied, the depletion layer structurally tends to reach the channel stopper 16 in the PN junction J, because there is a negative curve for the depletion layer, but the surface charge density Since the glass 100 has a substantially zero value, it is difficult for the depletion layer to extend.
このため、順逆両方向電圧についても空乏層がチャンネ
ル・ストッパー１６に到達する様な高゛屯圧に達したと
き、やつと強蒐界部が生じ℃ブレークオーバーを起てよ
うにすることができる。For this reason, when the depletion layer reaches such a high pressure that the forward and reverse voltages reach the channel stopper 16, a strong field region is generated and a °C breakover can occur.
従って、この実施例によれば、２個の環状ｇｓｏ。According to this example, therefore, two annular gso's.
９０に同じ材買のパッシベーション材を充填しタニもか
かわらず、塊状綽の深さで表面電荷密度とその極性をｖ
＠整することにより充分な順逆方向耐圧を与えることが
できる。90 was filled with a passivation material from the same material, and the surface charge density and its polarity were determined by the depth of the lumps.
By adjusting the voltage, sufficient forward and reverse breakdown voltage can be provided.
次Ｋ、この実施例の半導体基体の製造工程について説明
する。Next, the manufacturing process of the semiconductor substrate of this embodiment will be explained.
先ず、Ｎ型シリコン単結晶ウェハーが用意される。公知
の選択拡散技術を用いて５図示の接合形状を持つＰＮ接
合Ｊ、〜Ｊ、、Ｐｇ−Ｎｚ層４〜７゜チャンネル・スト
ッパー１６ｉ形成する。First, an N-type silicon single crystal wafer is prepared. Using a well-known selective diffusion technique, PN junctions J, -J, , Pg-Nz layers 4-7° channel stopper 16i having the junction shape shown in Fig. 5 are formed.
次に、ｇｓｏ、９ｏを公知の選択エツチング法により韓
８０は浅く、溝９０は深く（必要なガラス厚の約３倍）
設け、ここにＺｎＵ、系ガラス粉末を公知の１を気泳動
法、沈降法あるいはドクターブレード法により堆積させ
、約６５０〜８５０Ｃで焼付ける。Next, by etching gso and 9o using a known selective etching method, the grooves 90 are shallow and the grooves 90 are deep (approximately three times the required glass thickness).
ZnU and glass powder are deposited thereon by a pneumophoresis method, a sedimentation method, or a doctor blade method, and baked at about 650 to 850C.
こうして酵８０．９０へ堆積され、ガラスは焼付けによ
り堆積され几厚みの約１／３に収縮し、溝深さの約１／
３の厚みがパッシベーション材トして充填され、この結
果、負の表面電荷密度を有するガラス１１０と正の表面
電荷密度側に近すいたガラス１００ヲ得ることができる
。In this way, the glass is deposited on the fermenter 80.90, and the glass is deposited by baking and shrinks to about 1/3 of the thickness of the glass, and about 1/3 of the groove depth.
As a result, a glass 110 having a negative surface charge density and a glass 100 having a surface charge density close to the positive surface charge density can be obtained.
本発明によれば、従来よりホトリソグラフィ一工程とガ
ラスの堆積、税付工＆を各々１１１ｉ！ｉｌづつ低減で
き、製造工程は簡略化している。According to the present invention, one step of photolithography, glass deposition, and tax processing are each performed in 111i! The manufacturing process is simplified.
なお、本発明による半導体基体としては、上述のサイリ
スタに限らずトライブック等にも通用できる。Note that the semiconductor substrate according to the present invention is not limited to the above-mentioned thyristor, but can also be used for try books and the like.
以上説明したように、本発明によれは、２個の環状綽に
充填すべさパッシベーション材を同一の材料としても光
分な耐圧を与えることができるから、従来技術の欠点ｔ
−除き、光分な蒙圧丑性をもった半導体装ｉ１を容易に
得ることができる。As explained above, according to the present invention, even if the passivation material used to fill two annular cages is made of the same material, it is possible to provide an optical withstand voltage, which eliminates the drawbacks of the prior art.
- Except for the above, it is possible to easily obtain a semiconductor device i1 having a light resistance.
第１図は本発明による千尋体装置の一実施例を示す要部
拡大断面図、＄２図は従来の半尋体装直の一例を示す断
面図、第３図は第２図の一部拡大断面図、第４図は本発
明の一央一例におりるパッシベーション材の物性図であ
る。
ｌ・・・・・・半導体基体、８０．９０・・・・・・塊
状酵、 １００゜１１０・・・・・・パッシベーショ
ン材となるガラス。
フッへ′？
第１！！１
一
第２１！！
１１１Ｂ！！１FIG. 1 is an enlarged cross-sectional view of the essential parts of an embodiment of the Chihiro body device according to the present invention, FIG. 2 is a sectional view showing an example of a conventional half-body body installation, and FIG. The enlarged sectional view and FIG. 4 are physical properties of a passivation material that is one example of the present invention. l... Semiconductor substrate, 80.90... Bulk fermentation, 100°110... Glass serving as passivation material. Fuhe'? 1st! ! 1 1st 21st! ! 111B! ! 1
Claims (1)
半導体層を有する半導体基体の一方の主表面に、同心円
状に配置した２個の環状溝を形成させ、これら環状溝内
にパッシベーション材を充填して順方向耐圧と逆方向耐
圧を向上させるようにした半導体装置において、これら
２個の環状溝に充填したパッシベーション材の充填厚み
をこれら環状溝の一方と他方とで異ならしめ、内側の環
状溝内での充填厚みを外側の環状溝内でのそれよりも大
になるように構成したことを特徴とする半導体装置。 ２、特許請求の範囲第１項において、上記２個の環状溝
のうち、内側の環状溝の深さを外側の環状溝の深さより
も大となるように構成したことを特徴とする半導体装置
。 ３、特許請求の範囲第１項において、上記パッシベーシ
ョン材が、いずれの環状溝内においても負の表面電荷密
度を有する材料となるように構成したことを特徴とする
半導体装置。[Claims] 1. Two annular grooves arranged concentrically are formed in one main surface of a semiconductor substrate having at least three semiconductor layers of different conductivity types between adjacent ones. In a semiconductor device in which a passivation material is filled in these annular grooves to improve forward breakdown voltage and reverse breakdown voltage, the filling thickness of the passivation material filled in these two annular grooves is equal to that of one of these annular grooves. 1. A semiconductor device, characterized in that the filling thickness in the inner annular groove is larger than that in the outer annular groove. 2. A semiconductor device according to claim 1, characterized in that, of the two annular grooves, the depth of the inner annular groove is greater than the depth of the outer annular groove. . 3. The semiconductor device according to claim 1, wherein the passivation material is a material having a negative surface charge density in any of the annular grooves.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60089915A JPS61251039A (en) | 1985-04-27 | 1985-04-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60089915A JPS61251039A (en) | 1985-04-27 | 1985-04-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61251039A true JPS61251039A (en) | 1986-11-08 |
Family
ID=13984003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60089915A Pending JPS61251039A (en) | 1985-04-27 | 1985-04-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61251039A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003282888A (en) * | 2002-03-22 | 2003-10-03 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5565440A (en) * | 1978-11-11 | 1980-05-16 | Hitachi Ltd | Glass-coated semiconductor device |
| JPS58111322A (en) * | 1981-12-25 | 1983-07-02 | Hitachi Ltd | Semiconductor device |
-
1985
- 1985-04-27 JP JP60089915A patent/JPS61251039A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5565440A (en) * | 1978-11-11 | 1980-05-16 | Hitachi Ltd | Glass-coated semiconductor device |
| JPS58111322A (en) * | 1981-12-25 | 1983-07-02 | Hitachi Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003282888A (en) * | 2002-03-22 | 2003-10-03 | Mitsubishi Electric Corp | Semiconductor device and its manufacturing method |
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