JPS58111322A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58111322A JPS58111322A JP20913481A JP20913481A JPS58111322A JP S58111322 A JPS58111322 A JP S58111322A JP 20913481 A JP20913481 A JP 20913481A JP 20913481 A JP20913481 A JP 20913481A JP S58111322 A JPS58111322 A JP S58111322A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- junction
- groove
- voltage
- depletion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3178—Coating or filling in grooves made in the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Thyristors (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置に係わり１％に、ユニサーフエース
・ダブルモート構造の半導体基体のバシペーシ町に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and relates to a semiconductor substrate having a Unisurface double moat structure.
この樵半導体装置は、サイリスタに適用されることが多
９ので、以下、サイリスタに於る半導体基体を例に採っ
て説明する。Since this semiconductor device is often applied to a thyristor, it will be explained below using a semiconductor substrate in a thyristor as an example.
第１図は従来のサイリスタの半導体基体１を示している
。FIG. 1 shows a semiconductor body 1 of a conventional thyristor.
半導体基体ｌは上側主表面２と下側主表面３を有し、こ
の間に、隣接相互で導電層が異なる４半導体層、即ちｓ
Ｐｍ脂層４Ｎｍ脂層５Ｐ脂層６゜Ｎｏ脂層７有してい
る。Ｐｇ層４〜Ｎ■層７はｐｎ接ＱＪ１〜Ｊ、を形成し
ている。上側主表面２には２個の同心溝８．９が設けら
れ１、外溝８、の外周壁部にｐｎｎ接合、の端部が露出
し、ｎ＃Ｉ９の内周壁部Ｋｐｎ接合Ｊ、の端部が露出し
ている。The semiconductor substrate l has an upper main surface 2 and a lower main surface 3, between which four semiconductor layers, ie, s
It has Pm fat layer 4Nm fat layer 5P fat layer 6°No fat layer 7. The Pg layers 4 to N2 layers 7 form pn junctions QJ1 to J. Two concentric grooves 8.9 are provided on the upper main surface 2, the ends of the pnn junction are exposed on the outer peripheral wall of the outer groove 8, and the ends of the pnn junction J, are exposed on the inner peripheral wall of n#I9. The ends are exposed.
両溝８．９が上側主表面２に同ｔｂＱに設けられている
ことから、ユニサーフェイス・ダブルモート構造と呼称
されている。ｐｎｎ接合、は上側主表面２に露出して偽
る。＃１ｇ、９にはガラス１０゜１１が焼結されてｐｎ
接合Ｊｔ、、ｙ、のパシベーシ曹ンをしている。２１層
６にゲート電極１２ｔｈＮ■層７にカソード電極１３が
オーミックコンタクトされており、その他の部分にはシ
リコン酸化膜４４が設けられている。このシリコン酸化
膜１４はｐｎ接合Ｊ、のバシベーシ冒ンヲ行っている。Since both grooves 8.9 are provided on the upper main surface 2 at the same distance tbQ, it is called a unisurface double moat structure. The pnn junction is exposed on the upper main surface 2. #1g, 9 is sintered with glass 10°11 and pn
The passivation of the junctions Jt,,y, is performed. A gate electrode 12thN21 layer 6 has a cathode electrode 13 in ohmic contact with the layer 7, and a silicon oxide film 44 is provided on the other parts. This silicon oxide film 14 performs the cleaning of the pn junction J.
下側主表面３にはアノード電極１５が設けられている。An anode electrode 15 is provided on the lower main surface 3 .
溝８．９０関には高不純物濃度領域１６がチャンネル・
ストッパーとして設けられている。A high impurity concentration region 16 is formed as a channel at groove 8.90.
It is provided as a stopper.
カソード電極１３に対してアノード電極１５が正電位と
なるような順方向電圧を印加した時。When a forward voltage is applied such that the anode electrode 15 has a positive potential with respect to the cathode electrode 13.
ｐｎ接合Ｊ、が耐圧を維持し、カソード電極１３に対し
てゲート電極４２が正電位となるゲート電圧を加えると
、半導体基体１における耐圧は破れ。When the pn junction J maintains a breakdown voltage and a gate voltage is applied such that the gate electrode 42 has a positive potential with respect to the cathode electrode 13, the breakdown voltage in the semiconductor substrate 1 is broken.
、： ターンオンする。, : Turn on.
アノード電極１５に対してカソード電極が正電位となる
ような逆方向電圧を印加した時、ｐｎ接合Ｊ、が大部分
の耐圧を維持している。When a reverse voltage is applied such that the cathode electrode has a positive potential with respect to the anode electrode 15, the pn junction J maintains most of the breakdown voltage.
第２図は第１図の要部を拡大して、電圧阻止時の状態を
示し九ものである。FIG. 2 is an enlarged view of the main part of FIG. 1 to show the state when voltage is blocked.
第２図Ｋｉ？１．ｎて、第１図と同一物には同一符号を
付けている。Figure 2 Ki? 1. Components that are the same as those in FIG. 1 are given the same reference numerals.
順方向電圧阻止はｐｎ接合Ｊ、で行っておシ。Forward voltage blocking is performed by pn junction J.
この時１人で示す領域（点を付けた領域）λに空乏層が
形成されている。順方向電圧阻止状態で電界強度が最大
となる場所はａで示す付近である。At this time, a depletion layer is formed in the region λ shown by one person (dotted region). The location where the electric field strength is maximum in the forward voltage blocking state is near the area indicated by a.
ガラス１１として正電荷を持つものを用いた場合。When a glass 11 having a positive charge is used.
電圧が高まるにつれて空乏層は溝９の底を外局側に向っ
て延びるが、ガラス１１が正電荷を持つため、空乏層は
延びにくい。電圧を高くするに従い。As the voltage increases, the depletion layer extends from the bottom of the trench 9 toward the external center, but since the glass 11 has a positive charge, the depletion layer does not extend easily. As the voltage increases.
星付近の電界強度は大きくなシ、−例として２００〜３
００ｋＶ／ｍでブレークオーバする。一方、ガラス１１
として負電荷を持つ屯のを用いた場合、空乏層は＃１９
の底を外局側に向って延び易くなシ。The electric field strength near the star is large, for example 200~3
Breakover occurs at 00kV/m. On the other hand, glass 11
When using a negatively charged ion as a depletion layer, the depletion layer is #19.
The bottom of the tube does not easily extend toward the outer side.
点線にて示す領域Ｂｔで延び、チャンネル・ストッパー
ｓｅへの到達が早くなって、チャンネル・ストッパー１
６へ到達した後は空乏層は溝８の方向へは延びづらくな
って、ｂＫて示す付近の電界強度が大きくなってくる。It extends in the region Bt shown by the dotted line, and reaches the channel stopper se earlier, so that the channel stopper 1
6, it becomes difficult for the depletion layer to extend in the direction of the trench 8, and the electric field strength near bK increases.
夏に電圧を高くすると、ａ、ｂいずれかの付近の電界強
度が例えば２００〜３００ ｋＶ／ｅＷＩＫなって、早
く到達した方でブレークオーバが起る。If the voltage is increased in the summer, the electric field strength near either a or b will be, for example, 200 to 300 kV/eWIK, and breakover will occur in the one that reaches it earlier.
この様に溝９では、負電荷を持つパシベーション材を用
いると、阻止電圧は高くなる。In this way, when a passivation material having a negative charge is used in the groove 9, the blocking voltage increases.
一方、ｐｎ接合Ｊ、の方をみると、逆方向電圧阻止の場
合に同様なことが起るが、ｐｎ接合Ｊ。On the other hand, when looking at the pn junction J, a similar thing occurs in the case of reverse voltage blocking, but the pn junction J.
とは異なり％ｐｎ接合Ｊ、はＮｓ層層内内できる空乏層
にとっては、負の曲率ＲＫなっているため。Unlike %pn junction J, this is because the depletion layer formed within the Ns layer has a negative curvature RK.
低い電圧で空乏層が一点鎖線で示すようにチャンネル−
ストッパー１６に達してしまう。チャンネル・ストッパ
ー１６に達した後は、Ｃ付近で強電界部が発生し、Ｊ［
方向阻止電圧より低い電圧で。At low voltage, the depletion layer becomes channel − as shown by the dashed line.
The stopper 16 is reached. After reaching the channel stopper 16, a strong electric field is generated near C, and J[
At a voltage lower than the directional blocking voltage.
電界強度が例えば２００〜８００ｋＶ／、となシ。The electric field strength is, for example, 200 to 800 kV/.
負電荷を持つパシベーション材は、逆方向電圧に対して
は有効で呟ない。Passivation materials with a negative charge are effective against reverse voltage and do not react.
それゆえ１本発明の目的は、順逆両方向に対して阻止電
圧の高いパシベーション機能を有する半導体装置を提供
するＫある。Therefore, one object of the present invention is to provide a semiconductor device having a passivation function with a high blocking voltage in both forward and reverse directions.
本発明の特徴とするところは、溝８におけるｐｎ接合Ｊ
ｔのパシベ−ション材１０として正電荷を持つものを用
い、溝９におけるｐｎ接合Ｊ。The feature of the present invention is that the pn junction J in the groove 8
A pn junction J is formed in the groove 9 using a material having a positive charge as the passivation material 10 of the groove t.
のパシベーション材１１として正電荷を持つものを用い
るととＫある。It is possible to use a material having a positive charge as the passivation material 11.
第３図は本発明の一実施例を示す半導体基体ｌの要部拡
大図で、第１図に示すものと同一物、相蟲物には同一符
号を付けている。FIG. 3 is an enlarged view of essential parts of a semiconductor substrate l showing an embodiment of the present invention, in which the same parts and similar parts as shown in FIG. 1 are given the same reference numerals.
第３図において、溝８には正電荷を有するガラス１０が
、又、溝９には負電荷を有するガラス１１がパシベーシ
ョン材として充填されている。In FIG. 3, groove 8 is filled with positively charged glass 10, and groove 9 is filled with negatively charged glass 11 as a passivation material.
順方向電圧が印加された時、ｐｎ接合Ｊ、では。When a forward voltage is applied, at the pn junction J.
空乏層の延びが良く、チャンネル拳ストツノ（−１６に
到達し易くなって−る。１＊、逆方向電圧が印加された
時、ｐｎ接合Ｊ、では、空乏層にとって負の曲率Ｒがあ
る丸め、構造的に空乏層がチャンネル・ストッパー１６
に到達し易いのであるが、正電荷を持つガラスｌＯのた
めに、空乏層が延びに〈〈されている。The depletion layer has a good extension, making it easier to reach the channel angle (-16).When a reverse voltage is applied, the pn junction J has a rounded shape with a negative curvature R for the depletion layer. , the depletion layer is structurally the channel stopper 16
However, due to the positively charged glass lO, the depletion layer is elongated.
このため、順逆両方向電圧につｉても空乏層がチャンネ
ル・ストッパー１６に到達する様な高電圧になった後に
強電界部が生じてブレークオーバを起す。Therefore, even in both forward and reverse directions, after the depletion layer reaches a high voltage that reaches the channel stopper 16, a strong electric field is generated and breakover occurs.
次に、製造工ｓＫ基づいて本発明を説明する。Next, the invention will be explained based on the manufacturing process.
先ず、Ｎｍシリ；ン単結晶ウェハが用意される。First, a Nm silicon single crystal wafer is prepared.
公知の選択拡散技術を用いて、図示の接合形状を持つｐ
ｎ接合Ｊｓ 〜Ｊｓ 、Ｐｍ−Ｎｍ層４〜７゜チャンネ
ル・ストッパー１６を形成する。Using a well-known selective diffusion technique, p
N junctions Js to Js, Pm-Nm layers 4 to 7° channel stopper 16 are formed.
次に、溝９を公知の選択エツチング法によシ設け、こζ
ＫＰｂＯ−Ｂ雪０．−８口り系ガラス粉末を公知の沈降
法あるｖｈはドクターブレード法などＫより堆積させ、
約８００〜８５０Ｃで焼付けて。Next, grooves 9 are formed by a known selective etching method, and
KPbO-B snow 0. - 8-hole type glass powder is deposited by a known sedimentation method, VH is a doctor blade method, etc.
Bake at about 800-850C.
負電荷を有するガラス１１を得る。次に同様に公知の選
択エツチング法を用いて、溝８を設け、ここに、 ｚｌ
ｌｏ ＢＩＯｓ ８１０４系ガラス粉末を同様な上
記公知手段を用いて堆積させて、約６５０〜７００Ｃで
焼付けて、正電荷を有するガラス１０を得る。A glass 11 having a negative charge is obtained. Next, similarly using a known selective etching method, a groove 8 is provided, where zl
lo BIOs 8104 series glass powder is deposited using similar known means as described above and baked at about 650-700C to obtain positively charged glass 10.
これは１両ガラスの軟化温度、焼付温度に差があり、ま
た、焼付後に正負いずれかの電荷を持つことを利用した
もので、簡単に半導体基体１−を得ることができる。This method takes advantage of the fact that there is a difference in the softening temperature and baking temperature of the two glasses, and that they have either a positive or negative charge after baking, so that the semiconductor substrate 1- can be easily obtained.
パシベーション材としてはレジンも使用可能であシ、レ
ジンとガラスを組み合せて一方の溝にレジン、他方の溝
にガラスを充填しても良い。いずれの場合も、高い焼付
温度を有する方のパシベーション材を先に設けておく。Resin may also be used as the passivation material, or a combination of resin and glass may be used to fill one groove with resin and the other groove with glass. In either case, the passivation material having a higher baking temperature is provided first.
半導体基体としては上述のサイリスタに係らず。The semiconductor substrate is not related to the above-mentioned thyristor.
トライブック等にも適用できる。また、半導体基体、溝
の形状は各種のものが適用できる。It can also be applied to try books, etc. Further, various shapes of the semiconductor substrate and the groove can be applied.
第１図は従来のサイリスタの半導体基体を示す図、第２
図は第１図に示す半導体基体の要部拡大図、第３図は本
発明の一実施例を示すサイリスタの半導体基体の要部拡
大図である。Figure 1 shows the semiconductor substrate of a conventional thyristor, Figure 2
The figure is an enlarged view of the principal part of the semiconductor substrate shown in FIG. 1, and FIG. 3 is an enlarged view of the principal part of the semiconductor substrate of a thyristor showing one embodiment of the present invention.
Claims (1)
からなる半導体基体を有し、各半導体層はいずれも半導
体基体の一生表面に露出し、この−主表面には同心状に
２個の溝が形成されており１他方の主表面に露出する第
一半導体層とこの第一半導体層に隣接する第二半導体層
が形成する第一のｐｎ接合の端部は２個の溝のうちの外
溝の外周壁部に露出し、上記第二半導体層とこの半導体
層に隣接する第三半導体層が形成す今第二のｐ、 ｎ接
合の端部Ｉｆｉ２個の溝のうちの内轡の内周壁部に露出
し、・上記第二半導体層の上記−主表面に露出する部分
には、上記両溝にかけて第二半導体層と同一導電型であ
る高不純吻濃度領域が形成されており、上記外溝には負
の電荷を有するパシベーション材が充填され、上記内溝
には正の電荷を有するパシベーション材が充填されてい
ることを特徴とする半導体装置６ ・４・
゛、、1. It has a semiconductor substrate consisting of at least three semiconductor layers with different conductivity types between adjacent ones, each semiconductor layer is exposed on the entire surface of the semiconductor substrate, and there are two concentric layers on the main surface of the semiconductor substrate. A groove is formed, and the end of the first pn junction formed by the first semiconductor layer exposed on the other main surface and the second semiconductor layer adjacent to this first semiconductor layer is located in one of the two grooves. The end portion of the second p, n junction formed by the second semiconductor layer and the third semiconductor layer adjacent to this semiconductor layer is exposed on the outer peripheral wall of the outer groove. A high impurity concentration region having the same conductivity type as the second semiconductor layer is formed across both the grooves in a portion exposed to the inner peripheral wall portion and exposed to the main surface of the second semiconductor layer; A semiconductor device characterized in that the outer groove is filled with a passivation material having a negative charge, and the inner groove is filled with a passivation material having a positive charge.
゛、、
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20913481A JPS58111322A (en) | 1981-12-25 | 1981-12-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20913481A JPS58111322A (en) | 1981-12-25 | 1981-12-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58111322A true JPS58111322A (en) | 1983-07-02 |
Family
ID=16567848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20913481A Pending JPS58111322A (en) | 1981-12-25 | 1981-12-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58111322A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61251039A (en) * | 1985-04-27 | 1986-11-08 | Hitachi Ltd | Semiconductor device |
| US4799100A (en) * | 1987-02-17 | 1989-01-17 | Siliconix Incorporated | Method and apparatus for increasing breakdown of a planar junction |
-
1981
- 1981-12-25 JP JP20913481A patent/JPS58111322A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61251039A (en) * | 1985-04-27 | 1986-11-08 | Hitachi Ltd | Semiconductor device |
| US4799100A (en) * | 1987-02-17 | 1989-01-17 | Siliconix Incorporated | Method and apparatus for increasing breakdown of a planar junction |
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