JPS61238110A - Microwave 1/n frequency divider - Google Patents

Microwave 1/n frequency divider

Info

Publication number
JPS61238110A
JPS61238110A JP7965785A JP7965785A JPS61238110A JP S61238110 A JPS61238110 A JP S61238110A JP 7965785 A JP7965785 A JP 7965785A JP 7965785 A JP7965785 A JP 7965785A JP S61238110 A JPS61238110 A JP S61238110A
Authority
JP
Japan
Prior art keywords
frequency
closed loop
dual gate
divided
gate fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7965785A
Other languages
Japanese (ja)
Other versions
JPH07114327B2 (en
Inventor
Kazuhiko Honjo
和彦 本城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60079657A priority Critical patent/JPH07114327B2/en
Publication of JPS61238110A publication Critical patent/JPS61238110A/en
Publication of JPH07114327B2 publication Critical patent/JPH07114327B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To obtain a 1/n frequency divider having a large frequency division output level by setting a delay time of a closed loop to a nearly reciprocal of the frequency division output frequency and adding a frequency to be divided to the 2nd gate electrode of a dual gate FET. CONSTITUTION:An even number (2m; m is a positive integer) of inverters 4 and a delay line 5 are connected in cascade between the drain electrode 6 and the 1st gate 3 of the dual gate FET 1. The delay time of the closed loop comprising the even number of inverters, the delay line 5 and the dual gate FET is set to a td being a nearly reciprocal of a frequency division output frequency fo/n, and since the dual gate FET acts like on stage of inverter for the frequency-divided output frequency, 2m+1 (odd number) stages are formed as the closed loop, and since a pseudo ring oscillator is constituted, the oscillation is oscillated easily at a frequency of 1/td.

Description

【発明の詳細な説明】 (産業上の利用分野) この発明はマイクロ波分周器に関するものである0 (従来技術) マイクロ波通信装置には、マイクロ局部発振器が必要と
なるが、この局部発振器には、高い周波数安定度が要求
される口発振周波数を安定化する方法は大別して二種類
あろう第一の方法は高安定な共振器を発振器に付加する
方法であシ、第2の方法は発振周波数を分周して安定な
水晶発振周波数と位相比較しその結果を原発振器にフィ
ードバックし発振周波数を修正する方法である。
Detailed Description of the Invention (Field of Industrial Application) This invention relates to a microwave frequency divider.0 (Prior Art) A microwave communication device requires a micro local oscillator; There are two main ways to stabilize the oscillation frequency, which requires high frequency stability.The first method is to add a highly stable resonator to the oscillator, and the second method is to add a highly stable resonator to the oscillator. This method divides the oscillation frequency, compares the phase with a stable crystal oscillation frequency, and feeds the result back to the original oscillator to correct the oscillation frequency.

一般に第一の方法は設計技術的に容易であるが、外部共
振器を必要とするため形状が大きくなシ、サラにマイク
ロ波部のモノリシックIC化が不可能であるという欠点
を有し、大量生産には向かない技術である。一方第二の
方法はマイクロ波部の完全モノリシック化が可能であ夛
、大量生産に向いている0第二の方法を実現するために
はマイクロ波帯で動作する分周器が必要であるが、従来
は第2図に示す再生分周器が用いられている◎(従来技
術の問題点) 第2図において、入力端子21に入力した周波数fの信
号はミキサ22の第1の入力端子に加えられ、ミキサ出
力は周波数fの信号を遮断するフィルタ23を介して増
幅器24に入力され、増幅器出力の一部はミキサの第2
の入力端子に加えら周器の例はアイ・イー・イー・イー
、トランズアクシ冒ン・エム・ティー・ティー(IBE
BTrasaction MTT)の第32巻、第11
号の第1461から1468頁に記載されている〇か実
現できず、さらに分周出力レベルも小さく実際のシステ
ムへの応用は困難であった◎(発明の目的) 本発明の目的は上記再生分周器の欠点を除去し、分周出
力レベルの大きい17n(nは2以上の整数)分周器を
提供することにある0 (発明の構成) 本発明はデュアルゲートFF1Tのドレイン電極と第1
ゲート電極との間に、縦続に接続された遅延線路および
偶数個のインバータから構成される閉ループの遅延時間
が、分周出力周波数のほぼ逆数に設定され、前記デエア
ルグー)FETの第2ゲート電極に被分周周波数が加え
られることを特徴とすることから構成される〇 (実施例) 第1図は本発明の実施例を示すものでアシ、デュアルゲ
ートFETIのドレイン電極6と第1ゲート3の間には
偶数個(2m:mは正整数)のインバータ4および遅延
線路5が縦続接続されている。第1図において偶数個の
インバータと遅延線あるtdに設定されておシ、さらに
デ為アルゲー)FETは分周出力周波数にとっては1段
のインバータになっているため閉ループとしては2m+
1(奇数)段となシ、疑似リング発振器が構成されてい
るため、ユの周波数で発振しやすい状態となt、1 りている。
Generally, the first method is easy in terms of design technology, but it has the disadvantage that it requires an external resonator, so it is large in size, and it is impossible to make the microwave part into a monolithic IC. This is a technology that is not suitable for production. On the other hand, the second method allows the microwave section to be completely monolithic and is suitable for mass production.To realize the second method, a frequency divider that operates in the microwave band is required. Conventionally, a regenerative frequency divider shown in FIG. 2 has been used. (Problems with the prior art) In FIG. The mixer output is input to the amplifier 24 via a filter 23 that cuts off the signal of frequency f, and a part of the amplifier output is input to the second
An example of a frequency generator added to the input terminal of the IBE
BTrasaction MTT) Volume 32, No. 11
〇 described in pages 1461 to 1468 of the issue could not be realized, and the divided output level was also small, making it difficult to apply to an actual system ◎ (Objective of the Invention) The purpose of the present invention is to The object of the present invention is to eliminate the drawbacks of the frequency divider and provide a 17n (n is an integer of 2 or more) frequency divider with a high divided output level.
The delay time of a closed loop consisting of a delay line and an even number of inverters connected in cascade is set to approximately the reciprocal of the divided output frequency between the gate electrode and the second gate electrode of the D-FET. 〇 (Embodiment) Fig. 1 shows an embodiment of the present invention, in which the drain electrode 6 and the first gate 3 of a dual gate FETI are An even number (2m: m is a positive integer) of inverters 4 and delay lines 5 are connected in cascade between them. In Figure 1, an even number of inverters and a delay line are set to a certain td, and since the FET is one stage inverter for the divided output frequency, the closed loop is 2m+
Since the pseudo ring oscillator is configured with one (odd number) stage, it is in a state where it is easy to oscillate at the frequency of t,1.

ここで第2ゲート2に被分周周波数f0が入力されする
。この fi  10の信号が閉ループを巡りて第fo
の信号によ)ポンプさ孔開ループ内に定常的に存在する
ようになる口このとき被分周周波数f0は外部からの強
制入力となるため、閉ループ内にベルは他の高調波成分
に比べて大きい〇(発明の効果) このような本発明においては172分周のみならず1 
/ n分周がマイク四波帯において再生分周器構成で実
現でき、さらに分周出力も大きくとれるためマイクロ波
通信装置においてその効果は極めて大きい〇
Here, the divided frequency f0 is input to the second gate 2. This fi 10 signal goes around the closed loop to the fo
Since the frequency to be divided (f0) becomes a forced input from the outside, the bell in the closed loop is less than other harmonic components. (Effect of the invention) In this invention, not only the frequency division by 172 but also the frequency division by 1
/ n frequency division can be achieved in the microphone four-wave band with a regenerative frequency divider configuration, and the divided output can also be large, making it extremely effective in microwave communication equipment.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例で第2図は従来例である。図に
おいてlはデ鳳アルゲー)FET、4はインバータ、5
は遅延線路、22はミキサ、23はフィルタ、24は増
幅器である。
FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows a conventional example. In the figure, l is a FET, 4 is an inverter, and 5 is an inverter.
is a delay line, 22 is a mixer, 23 is a filter, and 24 is an amplifier.

Claims (1)

【特許請求の範囲】[Claims] デュアルゲートFETのドレイン電極と第1ゲート電極
との間に、縦続に接続された遅延線路および偶数個のイ
ンバータから構成される閉ループの遅延時間が、分周出
力周波数のほぼ逆数に設定され、前記デュアルゲートF
ETの第2ゲート電極に被分周周波数が加えられること
を特徴とするマイクロ波1/n(ただしnは2以上の整
数)分周器。
The delay time of a closed loop consisting of a delay line and an even number of inverters connected in series between the drain electrode and the first gate electrode of the dual gate FET is set to approximately the reciprocal of the divided output frequency, and dual gate F
A microwave 1/n (where n is an integer of 2 or more) frequency divider, characterized in that a frequency to be divided is applied to a second gate electrode of an ET.
JP60079657A 1985-04-15 1985-04-15 Microwave 1 / n frequency divider Expired - Fee Related JPH07114327B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60079657A JPH07114327B2 (en) 1985-04-15 1985-04-15 Microwave 1 / n frequency divider

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60079657A JPH07114327B2 (en) 1985-04-15 1985-04-15 Microwave 1 / n frequency divider

Publications (2)

Publication Number Publication Date
JPS61238110A true JPS61238110A (en) 1986-10-23
JPH07114327B2 JPH07114327B2 (en) 1995-12-06

Family

ID=13696211

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60079657A Expired - Fee Related JPH07114327B2 (en) 1985-04-15 1985-04-15 Microwave 1 / n frequency divider

Country Status (1)

Country Link
JP (1) JPH07114327B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01186018A (en) * 1988-01-20 1989-07-25 Matsushita Electric Ind Co Ltd Frequency divider
JP2007208589A (en) * 2006-02-01 2007-08-16 Univ Of Tokyo Frequency divider
JP2007528657A (en) * 2004-03-11 2007-10-11 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Divider

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59168706A (en) * 1983-03-02 1984-09-22 トムソン セーエスエフ Analog type nonperiodic split frequency divider circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59168706A (en) * 1983-03-02 1984-09-22 トムソン セーエスエフ Analog type nonperiodic split frequency divider circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01186018A (en) * 1988-01-20 1989-07-25 Matsushita Electric Ind Co Ltd Frequency divider
JP2007528657A (en) * 2004-03-11 2007-10-11 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Divider
JP4734510B2 (en) * 2004-03-11 2011-07-27 エスティー‐エリクソン、ソシエテ、アノニム Divider
JP2007208589A (en) * 2006-02-01 2007-08-16 Univ Of Tokyo Frequency divider

Also Published As

Publication number Publication date
JPH07114327B2 (en) 1995-12-06

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