JPS61237428A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61237428A JPS61237428A JP8048385A JP8048385A JPS61237428A JP S61237428 A JPS61237428 A JP S61237428A JP 8048385 A JP8048385 A JP 8048385A JP 8048385 A JP8048385 A JP 8048385A JP S61237428 A JPS61237428 A JP S61237428A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- semiconductor substrate
- scribe
- region
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 238000005530 etching Methods 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 29
- 230000001681 protective effect Effects 0.000 claims abstract description 24
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims description 8
- 238000012544 monitoring process Methods 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
この発明は半導体装置の製造方法に関し、特には不純物
の選択拡散等の工程を施こすに際して行なう半導体基板
表面に被着された酸化膜のエツチング工程のモニタに関
するものである。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a method for manufacturing a semiconductor device, and in particular to etching of an oxide film deposited on the surface of a semiconductor substrate when performing processes such as selective diffusion of impurities. This relates to process monitoring.
〈発明の概要〉
この発明は、半導体基板表面に被着された酸化膜を除去
する場合に、エツチング工程の終了時点を適切に知るた
め、半導体基板をチップ状に分割するために設けられた
スクライブ領域を利用し、このスクライブ領域を半導体
基板に施こす拡散処理の工程回数に応じて分割し、各分
割された領域を各拡散工程を実施する半導体基板領域の
モニタとしてエツチングの終了時点を監視する半導体装
置の製造方法である。<Summary of the Invention> The present invention uses a scriber provided to divide a semiconductor substrate into chips in order to appropriately know the end point of an etching process when removing an oxide film deposited on the surface of a semiconductor substrate. This scribe area is divided according to the number of diffusion process steps to be performed on the semiconductor substrate, and each divided area is used as a monitor of the semiconductor substrate area to perform each diffusion process to monitor the end point of etching. This is a method for manufacturing a semiconductor device.
〈従来の技術〉 半導体装置の製造工程、特にバイポーラＩＣ。<Conventional technology> Manufacturing process of semiconductor devices, especially bipolar IC.
ＭＯ８ＩＣの製造工程においては、半導体基板にＰ−Ｎ
接合を形成するためにボロン、リン等の不純物が選択拡
散される。この種の選択拡散を施こすに際しては、拡散
領域部分を被う保護膜を除去して半導体基板を露出させ
、この露出部に不純物が選択拡散される。上記保護膜の
除去は、不純物拡散が高精度に行われるためにはエツチ
ング工程で残存させない方が望ましく、またオーバエツ
チングをできるだけ少なくすることが必要で、そのため
には保護膜のエツチング工程の管理が極めて重要になる
。In the manufacturing process of MO8IC, P-N is applied to the semiconductor substrate.
Impurities such as boron and phosphorus are selectively diffused to form a junction. When performing this type of selective diffusion, the protective film covering the diffusion region is removed to expose the semiconductor substrate, and impurities are selectively diffused into this exposed portion. When removing the above-mentioned protective film, it is preferable not to leave it in the etching process so that impurity diffusion can be carried out with high precision, and it is also necessary to minimize over-etching. becomes extremely important.
〈発明が解決しようとする問題点〉
保護膜のエツチング終了時点の監視は、従来から当該半
導体基板とは別体のモニタ用半導体基板を準備し、この
モニタ用半導体基板に当該半導体基板と同一条件で表面
に保護膜を形成し、この保護膜（Ｓ ｉＯｚ ）を観察
しながらエツチングの終了時点を確認することによって
行われている。<Problems to be Solved by the Invention> In order to monitor the end of etching of a protective film, a monitoring semiconductor substrate separate from the semiconductor substrate is prepared, and this monitoring semiconductor substrate is subjected to the same conditions as the semiconductor substrate. This is done by forming a protective film on the surface and checking the end point of etching while observing this protective film (SiOz).
また上述のようなモニタによる判断が困難な工程におい
ては、目視によるエツチングの確認が無理な友め通常は
時間によって管理されている。In addition, in processes where it is difficult to judge by a monitor as described above, etching is usually managed by time, since it is impossible to check the etching visually.
しかし上記のようなエツチング工程の管理では、別途半
導体基板が必要になったり、半導体基板間に生じている
保護膜厚のバラツキに対処できず、エツチングを終了さ
せる好機を逸して半導体装置の歩留りや信頼性を低減さ
せる原因になっていた０く問題点を解決するための手段
〉
上記従来の半導体装置の製造方法における欠点を除去す
るため、半導体基板をチップ状に分割するために設けら
れたスクライブ領域を利用し、このスクライブ領域をエ
ツチング工程のモニタ領域としてエツチング終了時点の
確認に利用する。However, the above-mentioned etching process management requires a separate semiconductor substrate, cannot deal with variations in the thickness of the protective film that occur between semiconductor substrates, and misses a good opportunity to finish etching, which can lead to problems with the yield of semiconductor devices. Means for solving the problems that caused the reduction in reliability〉 In order to eliminate the drawbacks in the conventional semiconductor device manufacturing method described above, a scriber is provided to divide the semiconductor substrate into chips. This scribe area is used as a monitor area for the etching process to confirm the end of etching.
即ち、スクライブ領域に相当する半導体領域に、半導体
基板本体と同一の処理を施こし、同一工程を経て形成さ
れたスクライブ領域上の保護膜をモニタとしてエツチン
グ工程を監視し、終了時点を判断する。ここで半導体装
置の製造にあたっては通常複数回の選択拡散が施こされ
るため、各工程の監視に対処してスクライブ領域は複数
の領域に分割され、分割された各領域を半導体基板本体
の各選択拡散領域に施こす処理と同じ処理を施こしてモ
ニタとする。That is, the semiconductor region corresponding to the scribe region is subjected to the same process as the semiconductor substrate body, and the etching process is monitored using the protective film on the scribe region formed through the same process as a monitor to determine the end point. Since selective diffusion is normally performed multiple times in the manufacture of semiconductor devices, the scribe area is divided into multiple areas in order to monitor each process, and each divided area is divided into each area of the semiconductor substrate body. The same process as that applied to the selected diffusion area is applied to the area as a monitor.
く作 用〉
半導体基板本体に選択拡散を施こすにあたって、選択拡
散領域を被っている被膜が除去されて、該当部分の半導
体基板が露出される。このとき被膜の除去は、同一工程
を経てスクライブ領域に形成された被膜をモニタしなが
ら行われるため、エツチングの終了時期をタイミング良
く判断することができる。Function> When selectively diffusing the semiconductor substrate body, the film covering the selective diffusion region is removed to expose the corresponding portion of the semiconductor substrate. At this time, since the film is removed while monitoring the film formed in the scribe area through the same process, it is possible to determine the end of etching at a good timing.
〈実施例〉
バイポーラトランジスタを含む半導体装置の製造工程で
は、少なく共４回の選択拡散が半導体基板に施こされる
ため、このような製造工程を挙げて説明する。<Example> In the manufacturing process of a semiconductor device including a bipolar transistor, selective diffusion is performed on the semiconductor substrate at least four times, so such a manufacturing process will be described.
第１図（（おいて、予めＮ 埋込み層が形成され続いて
エピタキシャル成長層が形成された半導体基板１には、
バイポーラトランジスタ、抵抗等の回路素子を含んでな
る集積回路としての半導体チップが多数個形成される。In FIG.
A large number of semiconductor chips are formed as integrated circuits including circuit elements such as bipolar transistors and resistors.
従って半導体基板１には各半導体チップの境界部分に約
１００μｍ程度の幅でスクライブ領域２が予め設けられ
ている。Therefore, a scribe region 2 with a width of about 100 μm is provided in advance on the semiconductor substrate 1 at the boundary between each semiconductor chip.
このスクライブ領域２は、後述する４回の選択拡散に対
応して第２図に示す如く４領域２１＋２２＊２３及び２
４に分割されている。This scribe area 2 has four areas 21+22*23 and 2 as shown in FIG.
It is divided into 4 parts.
上記スクライブ領域２が設けられた半導体基板＋
１は、まずトランジスタ間を分離するためのＰ領域を選
択拡散するに先立って１層目の保護・膜３＋
が全域に形成される。ｐｎ接合分離のためのＰ領域（図
示せず）を被う上記保護膜３はホ） ＩＪソグラフィ技
術によって除去される。このとき上記第１スクライブ領
域２１は保護膜３のエツチング工程を監視するためのモ
ニタ領域として作用し、第１図の如くスクライブ領域２
１上の保護膜３がエツチングされた時点を検出してエツ
チングを終了させる。エツチングの終了時点は、エツチ
ング液の濡れが酸化膜面と半導体基板表面とでは著しく
相違し、濡れ状態を観察することによって判別できる。On the semiconductor substrate +1 provided with the scribe region 2, a first protective film 3+ is formed over the entire area before selectively diffusing the P region for isolating the transistors. The protective film 3 covering the P region (not shown) for pn junction isolation is removed by e) IJ lithography technique. At this time, the first scribe area 21 acts as a monitor area for monitoring the etching process of the protective film 3, and as shown in FIG.
The etching is terminated by detecting the point in time when the protective film 3 on the etching layer 1 has been etched. The end point of etching can be determined by observing the wetting state of the oxide film surface and the semiconductor substrate surface, since the wettability of the etching solution is significantly different between the oxide film surface and the semiconductor substrate surface.
上記エツチング工程で第１スクライブ領域２１は上記保
護膜３のエツチング雰囲気に晒されるものの、他の第２
乃至第４スクライブ領域２２〜２４は半導体基板１の残
りの領域と同様に保護膜３で被われたままエツチング工
程が実行される。Although the first scribe area 21 is exposed to the etching atmosphere of the protective film 3 in the etching process, the other second scribe area 21 is exposed to the etching atmosphere of the protective film 3.
The etching process is performed on the fourth scribe areas 22 to 24 while being covered with the protective film 3 like the remaining areas of the semiconductor substrate 1.
上記エツチング工程で露出した半導体基板領域にＰ不純
物の選択拡散処理を終えた半導体基板１は、第３図に示
す如く再び露出した基板表面を被って保護するための酸
化膜４が形成される。該酸化膜４の形成に伴ってその他
の半導体基板上はより厚さの増した２層目フィールド５
で被われる。After selectively diffusing P impurities into the semiconductor substrate region exposed in the etching process, the semiconductor substrate 1 is covered with an oxide film 4 to cover and protect the exposed substrate surface again, as shown in FIG. With the formation of the oxide film 4, a second layer field 5 with increased thickness is formed on the other semiconductor substrate.
covered with
次に例えばベース拡散を施こすために、半導体基板のベ
ース領域上を被う酸化膜がエツチング除去される。この
とき同じ条件で形成された酸化膜で被われている第２の
スクライブ領域２２も同じエツチング雰囲気に晒されて
第４図の如く除去され、ベース領域上の２層目フィール
ド酸化膜５のエツチング終了時をモニタする。露出され
た半導体基板にはベースのための不純物が選択拡散され
、その後第５図の如く基板表面に保護膜としての酸化膜
６が形成される。該酸化膜６の形成に伴って半導体基板
の他の領域を被う酸化膜は厚さを増し、３層目のフィル
ド酸化膜７を形成する。The oxide layer overlying the base region of the semiconductor substrate is then etched away, for example to perform base diffusion. At this time, the second scribe region 22 covered with an oxide film formed under the same conditions is also exposed to the same etching atmosphere and removed as shown in FIG. 4, and the second field oxide film 5 on the base region is etched. Monitor when finished. Impurities for the base are selectively diffused into the exposed semiconductor substrate, and then an oxide film 6 as a protective film is formed on the surface of the substrate as shown in FIG. With the formation of the oxide film 6, the thickness of the oxide film covering other regions of the semiconductor substrate increases, and a third layer of the filled oxide film 7 is formed.
以降選択拡散を施こす前に、該当領域を被う酸化膜をエ
ツチング除去して半導体基板を露出させる際、スクライ
ブ領域２を分割して準備された領域２３ ＋ ２４を被
う保護膜をモニタとしてエツチング工程を管理し、エッ
チング不足或いはエツチングオーバが生じない終了時点
を検出する。Thereafter, before performing selective diffusion, when etching away the oxide film covering the relevant region to expose the semiconductor substrate, the protective film covering regions 23 + 24 prepared by dividing the scribe region 2 is used as a monitor. The etching process is managed and the end point at which insufficient etching or overetching occurs is detected.
第６図は第４のスクライブ領域２４を露出させて第４回
目の選択拡散を実施する段階でのスクライブ領域の表面
状態を示し、半導体基板の主表面を被う酸化膜８に対し
てスクライブ領域２上の酸化膜は既に経た工程に応じた
膜厚が階段状を程する。第２図はこの状態での半導体基
板平面を示す。FIG. 6 shows the surface state of the scribe region at the stage of exposing the fourth scribe region 24 and performing the fourth selective diffusion. The oxide film on No. 2 has a step-like thickness depending on the steps that have already taken place. FIG. 2 shows the plane of the semiconductor substrate in this state.
選択拡散工程等の工程を終えて作成された回路素子間は
Ａ／蒸着等によって配線が形成され、各素子間が電気的
接続されてた後、半導体基板は上記スクライブ領域２か
らチップ状に分割される。Wiring is formed between the circuit elements created after completing the selective diffusion process, etc. by A/vapor deposition, etc., and after each element is electrically connected, the semiconductor substrate is divided into chips from the scribe area 2. be done.
スクライブ領域は上記のように分割に要する領域として
予め設けられ、半導体集積回路としては特別な役割を負
っていないため、たとえ上述のように保護膜が被着され
たり、不純物が拡散されてもほとんど支障はない。As mentioned above, the scribe area is provided in advance as an area required for division, and it has no special role in the semiconductor integrated circuit, so even if a protective film is applied or impurities are diffused as described above, there will be very little damage to the scribe area. There is no problem.
〈発明の効果〉
以上本発明によれば、半導体集積回路の動作には支障が
ないスクライブ領域を利用してエツチング工程のモニタ
領域を形成するため、エツチング工程を適正に監視する
ことができ、高精度に半導体装置を作製することができ
る０特にスクライブ領域を半導体装置の製造工程に対応
させて分割し、各分割領域を半導体基板本体の各領域と
同じ工程を経て処理するため、半導体基板が異なること
によるバラツキがなく、半導体装置のほぼ全工程に渡っ
て監視することができ、製造工程の管理に対する負担が
著しく軽減される。<Effects of the Invention> According to the present invention, the etching process monitor area is formed using the scribe area that does not interfere with the operation of the semiconductor integrated circuit, so the etching process can be properly monitored and the etching process can be improved. Semiconductor devices can be fabricated with high precision.In particular, the scribe area is divided according to the manufacturing process of the semiconductor device, and each divided area is processed through the same process as each area of the semiconductor substrate body, so the semiconductor substrate is different. There is no variation caused by this, and almost all processes of the semiconductor device can be monitored, and the burden on the management of the manufacturing process is significantly reduced.
第１図、第３図乃至第６図は本発明の一実施例を説明す
るための断面図、第２図は同平面図である０
１：半導体基板 ２ ＋ ２ｔ＊ ２Ｚ＋ ２３＋ ２
４ ニスクライブ領域 ３乃至８：保護膜
代理人 弁理士 福 士 愛 彦（他２名）第１図
ズ７う４グ］域／）１発ｌ享Ｊ−７’盾■乙第２図1, 3 to 6 are cross-sectional views for explaining one embodiment of the present invention, and FIG. 2 is a plan view thereof. 0 1: Semiconductor substrate 2 + 2t* 2Z+ 23+ 2
4 Niscribe area 3 to 8: Protective film agent Patent attorney Aihiko Fukushi (and 2 others) Figure 1 Z7U4G] area/) 1 shot l Kyo J-7' Shield ■ Otsu Figure 2
Claims (1)
導体基板の一部を露出させて半導体装置を製造する方法
において、 半導体基板をチップ状に分割するスクライブ領域を、半
導体基板に施こす選択拡散の回数に応じて分割し、 該分割されたスクライブ領域の夫々を、半導体基板本体
部の選択拡散領域に対応させて同一の工程を施こし、 各分割されたスクライブ領域の基板表面をモニタとして
選択拡散領域上を被う酸化膜をエッチングすることを特
徴とする半導体装置の製造方法。[Claims] 1) In a method of manufacturing a semiconductor device by exposing a part of a semiconductor substrate covered with a protective film in order to selectively diffuse impurities, a scribe region for dividing the semiconductor substrate into chips is provided. , the semiconductor substrate is divided according to the number of times of selective diffusion to be performed, each of the divided scribe areas is made to correspond to the selective diffusion area of the semiconductor substrate body, and the same process is performed, and each divided scribe is 1. A method of manufacturing a semiconductor device, comprising etching an oxide film covering a selective diffusion region using the substrate surface of the region as a monitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8048385A JPS61237428A (en) | 1985-04-15 | 1985-04-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8048385A JPS61237428A (en) | 1985-04-15 | 1985-04-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61237428A true JPS61237428A (en) | 1986-10-22 |
Family
ID=13719522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8048385A Pending JPS61237428A (en) | 1985-04-15 | 1985-04-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61237428A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63248134A (en) * | 1987-04-02 | 1988-10-14 | Nec Corp | Semiconductor device |
| JPH0223617A (en) * | 1988-07-13 | 1990-01-25 | Mitsubishi Electric Corp | Forming method for trench of semiconductor substrate wafer |
| JPH03288434A (en) * | 1990-04-04 | 1991-12-18 | Matsushita Electron Corp | Manufacture of semiconductor device |
-
1985
- 1985-04-15 JP JP8048385A patent/JPS61237428A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63248134A (en) * | 1987-04-02 | 1988-10-14 | Nec Corp | Semiconductor device |
| JPH0223617A (en) * | 1988-07-13 | 1990-01-25 | Mitsubishi Electric Corp | Forming method for trench of semiconductor substrate wafer |
| JPH03288434A (en) * | 1990-04-04 | 1991-12-18 | Matsushita Electron Corp | Manufacture of semiconductor device |
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