JPS61234041A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JPS61234041A
JPS61234041A JP60075887A JP7588785A JPS61234041A JP S61234041 A JPS61234041 A JP S61234041A JP 60075887 A JP60075887 A JP 60075887A JP 7588785 A JP7588785 A JP 7588785A JP S61234041 A JPS61234041 A JP S61234041A
Authority
JP
Japan
Prior art keywords
film
substrate
semiconductor
polycrystalline silicon
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60075887A
Other languages
Japanese (ja)
Inventor
Yoshitaka Sasaki
芳高 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
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Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP60075887A priority Critical patent/JPS61234041A/en
Publication of JPS61234041A publication Critical patent/JPS61234041A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/34—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being on the surface
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
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    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
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    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Abstract

PURPOSE:To reduce the ohmically contacting resistance by forming a semiconductor film on the back surface of a semiconductor substrate as one electrode film of a semiconductor device. CONSTITUTION:After a P<+> type semiconductor layer 3 is formed from the surface after an n-type epitaxially grown layer 2 is formed on an n<+> type semiconductor substrate 1a, a gate oxide film 5a is formed. After a polycrystalline silicon film 6a is then accumulated, a P-type semiconductor layer 5 is formed in a self-aligning manner, n<+> type semiconductor layer forming portion of a source region is then selectively opened, an n<+> type semiconductor layer 8 of a source region and an oxide film 5b1 are then formed, and a PSG film 5c is then accumulated thereon. Thereafter, after various heat treatments are executed, the substrate 1a is, for example, lap polished from the back surface, an undoped polycrystalline silicon layer 6b is accumulated, a high density phosphorus is diffused in the polycrystalline silicon, higher density phosphorus that the substrate is diffused in the substrate in this case, thereby forming an n<++> type semiconductor layer 1b. Subsequently, an electrode leading port is formed, and metal electrodes 9a, 9b are formed.

Description

【発明の詳細な説明】 ［発明の技術分野１ 本発明は、半導体基板の裏向を一電極として用いる大電
力用半導体装置において、裏面電極のオーミックコンタ
クトを良好とする半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention 1] The present invention relates to a semiconductor device for high power use in which the back side of a semiconductor substrate is used as one electrode, and which has good ohmic contact with a back electrode.

［発明の技術的背景とその問題点］ 従来のパワーＨａｓ　ＦＥｒ（絶縁ゲート型電解効果ト
ランジスタ）は、その代表的なものにＤＳＡ　　（Ｄｉ
ｒ−ｒｕｓｉｔｉｏｎ　５ｅｌｆ−＾１１ｇｎ１ｅｎｔ
）Ｈａｓ　ＦＥＴがあり、高濃度基板、例えば０．０１
〜０．０３Ωαの上にエピタキシャル領域を形成したシ
リコンウェハーを用い、エピタキシャル領域に２重拡散
によりチャネルを形成するものでゲート絶縁膜上に存在
する格子あるいはストライプ形状のゲート多結晶シリコ
ン電極に囲まれた同一の拡散窓によりチャネル領域形成
の不純物拡散と、ソース領域形成の不純物拡散を行い、
ソース・ゲート電極を形成し、舶２高濃度基板をドレイ
ン電極として用いている。[Technical background of the invention and its problems] A typical example of the conventional power HasFEr (insulated gate field effect transistor) is the DSA (Di
r-rusition 5elf-^11gn1ent
)Has FET, high concentration substrate, e.g. 0.01
Using a silicon wafer with an epitaxial region formed on ~0.03Ωα, a channel is formed in the epitaxial region by double diffusion, and the gate is surrounded by a lattice or stripe-shaped gate polycrystalline silicon electrode existing on the gate insulating film. The impurity diffusion for forming the channel region and the impurity diffusion for forming the source region are performed using the same diffusion window.
Source and gate electrodes are formed, and the second high concentration substrate is used as a drain electrode.

しかしながら、通常数オーム程度のオン抵抗素子は、基
板部ｆ！！０．０１〜０．０３Ωαでもオーミック抵抗
成分の影響は少ない。However, the on-resistance element, which is normally on the order of several ohms, is limited to the substrate portion f! ! Even at 0.01 to 0.03 Ωα, the influence of the ohmic resistance component is small.

しかし、数１００ミリオーム以下の低オン抵抗素子や、
素子の限界付近の大電流領域で用いられる曝 場合、オーミックコンタクト抵抗成分の寄与は極めて大
きな障害となる。However, low on-resistance elements of several hundred milliohms or less,
When exposure is used in a large current region near the limit of the device, the contribution of the ohmic contact resistance component becomes an extremely large obstacle.

一方、このオーミックコンタクト抵抗成分は、高融点金
属膜をバリヤメタルとして用いているショットキーバリ
ヤ型ダイオードのカソード領域のオーミックコンタクト
にも影響は大きい。つまりオーミックコンタクト抵抗の
大きさがそのままショットキーバリヤ型ダイオードの順
方向特性（Ｖ　Ｆ）に悲影響を及ぼす。On the other hand, this ohmic contact resistance component also has a large effect on the ohmic contact in the cathode region of a Schottky barrier diode that uses a high melting point metal film as a barrier metal. In other words, the magnitude of the ohmic contact resistance directly affects the forward characteristics (VF) of the Schottky barrier diode.

そこで、従来においては改良された￥導体装置に特開昭
５９−８４４７４　ｒ電力用縦型電解効果トランジスタ
」がある。Therefore, in the past, an improved conductor device is disclosed in Japanese Patent Application Laid-Open No. 59-84474, ``Vertical Field Effect Transistor for Power Use''.

この半導体装置は、上記欠点を補うため、予め基板の裏
面に基板よりもへｍ度の不純物を深く拡散じた後、主面
に形成されたエピタキシャル領域にＨＯＳ　ＦＥＴのソ
ース・ゲート領域を形成している。In order to compensate for the above-mentioned drawbacks, this semiconductor device is designed by first diffusing impurities deeper than the substrate into the back surface of the substrate, and then forming the source/gate regions of the HOS FET in the epitaxial region formed on the main surface. ing.

この方法によると、ドレイン電極のオーミックコンタク
ト抵抗は低減化されるが、その反面高濃度基板（〜１０
１９１０ｌ９中にさらにこれ以上の高濃度（１０２０〜
１０２１α４）不純物拡散を行うため、不純物拡散の進
行が遅く、そのため高温で長時間のプロセスが必要であ
る。これは、強いては高濃度基板からエピタキシャル領
域へ高濃度不純物拡散が進行し、エピタキシャル領域の
条件が変わり素子の特性をそこねてしまう。According to this method, the ohmic contact resistance of the drain electrode is reduced, but on the other hand, the high concentration substrate (~10
Even higher concentrations (1020~
1021α4) Since impurity diffusion is performed, the progress of impurity diffusion is slow, and therefore a long process at high temperature is required. This is because the high-concentration impurity diffusion progresses from the high-concentration substrate to the epitaxial region, changing the conditions of the epitaxial region and impairing the characteristics of the device.

次にエピタキシャル領域形成前に基板裏面側に高濃度不
純物拡散を施す方法では、従来の高濃度基板の厚み〜３
００μｍよりも薄い基板を用いなければならない。周知
のごとく、大電力素子は動作時に熱を発生するため基板
は薄い方が放熱特性は優れていると言われている。その
関係上、比較的薄い基板にエピタキシャル成長を施すに
はかなりむずかしい技術を必要とする。Next, in the method of performing high concentration impurity diffusion on the back side of the substrate before forming the epitaxial region, the thickness of the conventional high concentration substrate is ~3.
A substrate thinner than 00 μm must be used. As is well known, high-power devices generate heat during operation, so it is said that thinner substrates have better heat dissipation characteristics. For this reason, considerably difficult techniques are required to perform epitaxial growth on a relatively thin substrate.

まず基板が薄いため、ウェハーの先端が冷却、加熱に敏
感で、ウェハーのそり等によって、ウェハー周辺部にス
リップと称される結晶欠陥が発生しやすくなり、このス
リップは成長させるエピタキシャル層が厚いほど著しく
発生し、そのため特別の工夫が必要となりコスト高につ
ながる。First, because the substrate is thin, the tip of the wafer is sensitive to cooling and heating, and crystal defects called slips are more likely to occur around the wafer due to warping of the wafer. This occurs significantly, requiring special measures and leading to higher costs.

［発明の目的］ 本発明は、上述した欠点を取り除き、低いオーミックコ
ンタクト抵抗を有する半導体装置及びその製造方法を提
供することにある。[Object of the Invention] An object of the present invention is to eliminate the above-mentioned drawbacks and provide a semiconductor device having low ohmic contact resistance and a method for manufacturing the same.

［発明の概要］ 本発明は、−ＩＦ導電型有する崖導体基板の裏面に半導
体膜のうち特に基板よりも高濃度の不純物をドーピング
した多結晶シリコン等を具備し、該多結晶シリコンと金
属電極膜との低オーミツクコンタクト抵抗を可能とした
半導体装置であり、また本発明は、一導電型の半導体基
板上に半導体層を形成し、該半導体層の主面に１又は２
以上の半導体領域とその電極膜を形成し、裏面に半導体
膜を形成し、該半導体膜が前記半導体￥Ａツの一電極膜
としてなる半導体装置とその製造方法である。[Summary of the Invention] The present invention comprises, on the back surface of a cliff conductor substrate having a -IF conductivity type, polycrystalline silicon or the like doped with an impurity at a higher concentration than the substrate in a semiconductor film, and the polycrystalline silicon and a metal electrode. It is a semiconductor device that enables low ohmic contact resistance with a film, and the present invention also provides a semiconductor device in which a semiconductor layer is formed on a semiconductor substrate of one conductivity type, and one or two layers are formed on the main surface of the semiconductor layer.
The present invention provides a semiconductor device in which the above-described semiconductor region and its electrode film are formed, a semiconductor film is formed on the back surface, and the semiconductor film serves as one electrode film of the semiconductor A, and a manufacturing method thereof.

［発明の実施例］ 以Ｆ本発明の一実施例を説明する。[Embodiments of the invention] An embodiment of the present invention will be described below.

この一実施例は口ＳＡ　８０３　ＦＥＴについて説明す
る。This example describes an SA 803 FET.

第１図（ａ）に平面図、第１図（ｂ）にＡ−Ａの断面図
を示す。FIG. 1(a) shows a plan view, and FIG. 1(b) shows a sectional view taken along line A-A.

次に第２図（ａ）乃至（ｆ）を用いて本発明のＤＳＡ　
ＨＯＳの製造工程を説明する。ｎ＋型半導体基板１ａ上
にｎ型エピタキシャル成長Ｅ４２を例えば比抵抗１０〜
２５Ωα、厚み３０〜６０μｍ形成後、表面からＰ４″
型イ導体層３を形成する。Next, using FIGS. 2(a) to (f), the DSA of the present invention
The manufacturing process of HOS will be explained. N-type epitaxial growth E42 is grown on the n+-type semiconductor substrate 1a, for example, with a specific resistance of 10 to
After forming 25Ωα, thickness 30-60μm, P4″ from the surface
A type A conductor layer 3 is formed.

その後、ゲート酸化膜５ａを約１０００＾形成した様子
を第２図（ａ）に示す。Thereafter, a gate oxide film 5a having a thickness of about 1000^ is formed, as shown in FIG. 2(a).

次に多結晶シリコン膜６ａを例えば６０００　Ａ堆積後
選択的にバターニングし、この多結晶シリコンパターン
をマスクしてイオン注入を施し、チャンネル領域のＰ型
半導体層４を自己整合的に形成する。この様子を第２図
（ｂ）に示す。Next, the polycrystalline silicon film 6a is selectively patterned after being deposited at, for example, 6000 A, and ions are implanted with this polycrystalline silicon pattern as a mask to form the P-type semiconductor layer 4 in the channel region in a self-aligned manner. This situation is shown in FIG. 2(b).

続いてフォトエツチング技術にてフォトレジストアを用
いて、ソース領域のｎ６型半導体層形成予定部を選択的
に開口した様子を第２図（Ｃ）に示す。Subsequently, a portion of the source region where the N6 type semiconductor layer is to be formed is selectively opened using a photoresist using a photoetching technique, as shown in FIG. 2C.

次にソース領域のｎ＋型型半体体層８酸化膜５ｂ１を形
成しく第２図（ｄ）に図示）、その上にＣｖＤ法ニテ形
成シｔｃＰｓＧＷ１５　Ｇヲ約８０００１！１ｍ積した
様子を第２図（ｅ）に示す。Next, an n+ type half-layer 8 oxide film 5b1 of the source region is formed (as shown in FIG. 2(d)), and a CvD film is formed thereon with a thickness of about 80,001!1m. Shown in Figure (e).

しかる優、各種熱処理を施した１１　ｎ　”型ず導体基
板１ａを例えば裏面からラッピング研磨し、トータルウ
ェハ一層を約２００μｍ程度にする。However, the 11 n'' type conductive substrate 1a, which has been subjected to various heat treatments, is polished by lapping, for example, from the back side, so that the total thickness of each wafer layer is about 200 μm.

次に、ラッピング研磨で粗面化した状態でアンドープ多
結晶シリコンｌ！１６ｂを約１μｍｖ１度堆積した様子
を第２図（ｅ）にポす。Next, the undoped polycrystalline silicon l! is roughened by lapping and polished. FIG. 2(e) shows a state in which 16b was deposited once in a volume of about 1 μm.

次に１０００℃中でＰｏＣｊ！３から１３１１度リンを
前記多結晶シリコンに拡散し、この際ｎ＋＋半導体基板
中にも該基板より高濃度のリンが拡散され、ｎ″型型半
体体層１ｂ形成される。尚、このＴ程は、ゲッタリング
役割を兼ねる。Next, PoCj at 1000℃! Phosphorus is diffused into the polycrystalline silicon from 3 to 1311 degrees, and at this time, phosphorus with a higher concentration than that of the substrate is diffused into the n++ semiconductor substrate, forming an n'' type half body layer 1b. Cheng also serves as a gettering role.

しかる後、電極取り出し開口部を形成し、金属電極９ａ
、９ｂを形成することによってソース・ドレイン間耐圧
Ｖ、２００〜６００■程度のＤＳＡＤＡＳ ＨＯ３が完成する。この様子を第２図（ｆ）に示す。After that, an electrode extraction opening is formed and the metal electrode 9a is
, 9b, a DSADAS HO3 having a source-drain breakdown voltage of about 200 to 600 Å is completed. This situation is shown in FIG. 2(f).

次に他の実施例としてショットキーバリヤ型ダイオード
について、第３図により説明する。Next, a Schottky barrier diode as another embodiment will be explained with reference to FIG.

まず、ｎ＋＋半導体基板１ａの主面に形成したｎ型エビ
キシャル層２に約８００ＯＡの酸化Ｍ１５ｂを形成した
様子を第３図（ａ）に示す。続いて基板１ａの裏面をア
ルミナ粉等の研磨材によってラッピング研磨し、このＦ
Ａ磨面を粗面化しウェハー全体の厚みを約２００μｍ程
度にした様子を第３図（ｂ）に示す。First, FIG. 3(a) shows how oxidized M15b of about 800 OA is formed on the n-type epitaxial layer 2 formed on the main surface of the n++ semiconductor substrate 1a. Subsequently, the back surface of the substrate 1a is polished by lapping with an abrasive material such as alumina powder, and this F
FIG. 3(b) shows how the A-polished surface is roughened so that the total thickness of the wafer is about 200 μm.

次に粗面化したｎ＋＋半導体基板１ａに該基板よりも高
濃度のｎ”型不純物ドープのｎ″型型詰結晶シリコン６
ｂ堆積した様子を第３図（Ｃ）に示す。続いて熱処理を
施した後に、リン拡散、ＣＶＤ法によるＰＳＧＩｌ＊あ
るいはリンインプラ等を酸化膜に行い、該酸化膜５ｂと
その上に形成された高濃度リンを含んだ酸化ｍ＜図示せ
ず）のエツチングレートの差を利用してフォトエツチン
グ技術によって選択的に酸化膜５ｂのテーパー１ツチン
グを行った様子を第３図（ｄ）に示す。Next, the roughened n++ semiconductor substrate 1a is coated with an n'' type packed crystalline silicon 6 doped with an n'' type impurity at a higher concentration than the substrate.
FIG. 3(C) shows the state in which the b deposits were deposited. Subsequently, after heat treatment, the oxide film is subjected to phosphorus diffusion, PSGIl* by CVD method, or phosphorus implantation, etc., to form the oxide film 5b and the oxide m<not shown containing high concentration phosphorus formed thereon. FIG. 3(d) shows how the oxide film 5b is selectively tapered by a photoetching technique using the difference in etching rate.

しかる後、この上にモリブデン９Ｃを４０００へ。After that, add molybdenum 9C to 4000 on top of this.

アルミ金属１１１９ａを約８μｍｖ１ａ蒸着によって形
成し、かつ、熱処理を例えば４００℃、Ｎ２雰囲気にて
２０分程麿行いバリヤハイドを形成後、ざらに粗面化し
たシリコンウェハーの裏面に例えばＴｉ−Ｐｔ−ＡＵを
そｔＬぞれＳＯＯ＾、　１０ＧＯＡ　、　２０００八等
又はＣｒ−Ｎ１−ＡＬＪをそれぞれ５ＧＯＡ　＋　１０
００Ａ＋　２０００Ａ　＠蒸着形成することにょっ又カ
ソード電極の低オーミツクコンタクト抵抗化を可能とし
たショットキーバリヤ型ダイオードを形成できる。この
様子を第３図（ｅ）に示す。Aluminum metal 1119a is formed by vapor deposition of about 8 μm v1a, and heat treatment is performed for about 20 minutes at, for example, 400° C. in a N2 atmosphere to form a barrier hide. SOO^, 10GOA, 20008 etc. or Cr-N1-ALJ respectively 5GOA + 10
00A+ 2000A@ By vapor deposition, it is possible to form a Schottky barrier type diode which makes it possible to reduce the ohmic contact resistance of the cathode electrode. This situation is shown in FIG. 3(e).

尚、本発明による第１実施例のＤＡＳ　ＨＯ３ＦＥＴに
使用したシリコンウェハーは、ｎ＋＋半導体基板にｎ型
エピタキシャル層を成長させたｎオンｎ＋ウェハーを用
いたが、これに限定せず例えばｎ型半導体基板にｎ＋＋
不純物拡散を膿した拡散つＩバーを用いてもよい。よっ
て拡散ウェハーは通常２００〜２５０μｍと比較的薄い
ため。本発明による実施例はｎ＋＋半導体層〈又は基板
〉の裏面をラッピングする必要がなくそのまま多結晶シ
リコンを堆積するか、さもなくば例えばアルミナ粉を高
速でスプレーするサンドブラストにて裏面を粗面化した
後、多結晶シリコンを堆積してもよい。また、多結晶シ
リコンは堆積の際に−・緒にｎ”型不純物をドープして
も良いし、アンドープ多結晶シリコンにイオン注入や、
ＣＶＤ法によるＰＳＧＩＩからの拡散等各種の方法を用
いてもよい。Although the silicon wafer used in the DAS HO3FET of the first embodiment of the present invention is an n-on n+ wafer in which an n-type epitaxial layer is grown on an n++ semiconductor substrate, the present invention is not limited to this. ni n++
A diffusion tube that prevents impurity diffusion may also be used. Therefore, the diffusion wafer is usually relatively thin at 200 to 250 μm. Embodiments according to the present invention do not require lapping the back side of the n++ semiconductor layer (or substrate), and can either directly deposit polycrystalline silicon or roughen the back side by sandblasting, for example by spraying alumina powder at high speed. Afterwards, polycrystalline silicon may be deposited. Additionally, polycrystalline silicon may be doped with n'' type impurities during deposition, or undoped polycrystalline silicon may be ion-implanted,
Various methods may be used, such as diffusion from PSGII using the CVD method.

また、ｎ＋＋半導体基板中にｎ”望多結晶シリコン層か
ら高濃度ｎ”型不純物を拡散してもよいし、あるいは予
めｎ＋＋型不純物をｎ＋＋半導体基板に浅く拡散した後
にｎ０型多結晶シリコンを堆積してもよい。また、第２
実施例のごとく、ｎ＋型型半導体根板１ａ中ｎ０型不純
物拡散層を形成しなくてもかまわない。さらにまた第１
実施例。Alternatively, high concentration n'' type impurities may be diffused into the n++ semiconductor substrate from an n'' polycrystalline silicon layer, or n0 type polycrystalline silicon is deposited after shallowly diffusing n++ type impurities into the n++ semiconductor substrate in advance. You may. Also, the second
As in the embodiment, it is not necessary to form the n0 type impurity diffusion layer in the n+ type semiconductor base plate 1a. Furthermore, the first
Example.

第２実施例においてＰ型頭域とｎ型領域は逆でも良い。In the second embodiment, the P-type head region and the N-type region may be reversed.

また、半導体膜のうち時に多結晶シリコンを用いたが、
これに限定せず例えば非晶質シリコンや、高融点金属シ
リサイド等でも良い。In addition, although polycrystalline silicon is sometimes used in semiconductor films,
The material is not limited to this, and may be, for example, amorphous silicon, high melting point metal silicide, or the like.

［発明の効果］ 以上のごとく、本発明によると極めて狭いヂャネル領域
を形成後、基板裏面に該基板よりも高濃度なｎ″型型半
体体層半導体膜を形成できる。しかも基板裏面に形成さ
れている半導体膜で、特に・　多結晶シリコン族は単結
晶シリコンと比−較して数倍から数十倍の拡散スピード
を持っており、かつ多結晶であるため結晶間に多量の３
８１度不純物をドープすることが可能である。これは、
ｎ＋型学生導体基板りも高濃度の不純物ドープが可能な
ことを示している。したがって狭いブヤネル領域や浅い
ソース領域を形成した後にも基板よりも高濃度な半導体
層や、半導体膜が低温、短時間で形成可能でありｎ＋＋
半導体基板からｎ型エピタキシャル領域への高ｍａ不純
物（Ａｓ、Ｓｂ）の拡散の進行が起らず素子特性にも何
ら問題がない。[Effects of the Invention] As described above, according to the present invention, after forming an extremely narrow channel region, an n'' type half-layer semiconductor film having a higher concentration than that of the substrate can be formed on the back surface of the substrate. Polycrystalline silicon family semiconductor films, in particular, have a diffusion speed that is several to several tens of times faster than single-crystal silicon, and because they are polycrystalline, there is a large amount of
It is possible to dope with 81 degree impurities. this is,
The n+ type student conductor substrate also shows that it is possible to dope the impurity at a high concentration. Therefore, even after forming a narrow Bouyanel region or a shallow source region, a semiconductor layer or semiconductor film with a higher concentration than the substrate can be formed at low temperature in a short time, and n++
Diffusion of high-ma impurities (As, Sb) from the semiconductor substrate to the n-type epitaxial region does not occur, and there is no problem with device characteristics.

次にｎ＋＋半導体基板の裏面に００型不純物拡散を行う
ため、前記ｎ４″型半導体基板の１面にも０．３〜１．
０μｍ程良のｎ＋４型不純物拡散相が形成される。従来
方法では裏面の粗面化によって除去されてしまうが、本
発明では、二つのｎ”拡散層をｎ０多結晶シリコン膜が
被っているためオーミックコンタクト抵抗の低い素子が
可能である。Next, in order to perform 00 type impurity diffusion on the back surface of the n++ semiconductor substrate, 0.3 to 1.0.
An n+4 type impurity diffused phase with a thickness of approximately 0 μm is formed. In the conventional method, the n0 polycrystalline silicon film is removed by roughening the back surface, but in the present invention, since the two n'' diffusion layers are covered with the n0 polycrystalline silicon film, an element with low ohmic contact resistance can be achieved.

しかも、堆積時に００型不純物をドーピングして成る多
結晶シリコン膜を用いることによって該多結晶シリコン
族の特徴として堆積膜が厚いほど、あるいは１１度はど
グレンサイズの大きな多結晶シリコン膜が可能で表面の
凹凸の激しい膜が形成できる。Furthermore, by using a polycrystalline silicon film doped with 00-type impurities during deposition, a polycrystalline silicon film with a thicker deposited film or a larger 11° grain size can be produced. A film with a highly uneven surface can be formed.

これはチップの組立ての際、メタル電極との接触面積を
大きくし、ウェハーチップ裏面の金ｊ！ｔｌ！１とのＩ
ｉ説を防止するのに役立つ。したがって新たに粗面化す
る必要がない。This increases the contact area with the metal electrode during chip assembly, allowing the gold on the backside of the wafer chip to become larger! tl! I with 1
Helps prevent i-theory. Therefore, there is no need to newly roughen the surface.

周知のごとく、極薄いゲート酸化膜を有するＨＱＳ型半
導体装置の場合、ラッピングやサンドブラスト等の裏面
を粗面化する工程によって高圧の静電気が発生し、ゲー
トの絶縁破壊を起してしまう。As is well known, in the case of an HQS type semiconductor device having an extremely thin gate oxide film, high-voltage static electricity is generated during a back surface roughening process such as lapping or sandblasting, which causes dielectric breakdown of the gate.

本発明によると、多結晶シリコン族の形成方法の工夫に
よってこの裏面の粗面化を無くすことが可能で上述した
問題を防ぐこともできる。According to the present invention, by devising a method for forming polycrystalline silicon, it is possible to eliminate this roughening of the back surface, and the above-mentioned problems can also be prevented.

【図面の簡単な説明】[Brief explanation of drawings]

第１％４’本発明によるＯ８Ａ　Ｍ２Ｓ　ＦＥＴの平面
図とは他の実施例としてショットキーバリヤ型ダイオー
ドの各工程での断面図を示す。 １ａ・・・ｎ＋望半導体ｕ板、 １ｂ・・・ｎ”型半導体層、 ２・・・ｎ型半導体層、３・・・Ｐ＋型半導体層、４・
・・Ｐ型半導体層（チャネル領域）、５ａ・・・ゲート
酸化膜、５ｂ・・・酸化膜、５　ｃ−ＣＶ　Ｄ　ｍｌ化
膜、 ６ａ・・・ゲート多結晶シリコン膜、 ６ｂ・・・ｎ０型多結晶シリコン膜、 ７・・・フォトレジスト、 ８・・・ｎ′型型半体体層ソース領ｔｉり、９ａ・・・
ＡＩ電電極、９ｂ・・・裏面金属電極膜、９Ｃ・・・バ
リヤメタル（モリブデン）。 代理人　弁理士　三　　澤　　正　　義第２図 第２図 （ｆ） ｂ 第３図 ６ｂ ｂ1% 4' The plan view of the O8A M2S FET according to the present invention is a cross-sectional view of a Schottky barrier diode at various steps as another embodiment. 1a...n+ desired semiconductor u-plate, 1b...n'' type semiconductor layer, 2...n type semiconductor layer, 3...P+ type semiconductor layer, 4...
...P-type semiconductor layer (channel region), 5a...gate oxide film, 5b...oxide film, 5c-CVD ml film, 6a...gate polycrystalline silicon film, 6b...n0 type polycrystalline silicon film, 7... photoresist, 8... n' type half layer source region, 9a...
AI electrode, 9b... Back metal electrode film, 9C... Barrier metal (molybdenum). Agent Patent Attorney Masayoshi Misawa Figure 2 Figure 2 (f) b Figure 3 6b b

Claims (4)

【特許請求の範囲】[Claims] （１）一導電型の半導体基板上に半導体層を有し、該半
導体層の主面に１又は２以上の半導体領域と、その電極
膜を有し、裏面に単数の電極膜を有する半導体装置にお
いて、前記半導体基板の裏面に半導体膜を有し該半導体
膜が前記半導体装置の一電極膜として具備することを特
徴とする半導体装置。(1) A semiconductor device that has a semiconductor layer on a semiconductor substrate of one conductivity type, has one or more semiconductor regions and an electrode film thereof on the main surface of the semiconductor layer, and has a single electrode film on the back surface. 2. A semiconductor device according to claim 1, wherein a semiconductor film is provided on the back surface of the semiconductor substrate, and the semiconductor film is provided as one electrode film of the semiconductor device. （２）前記半導体膜は、不純物がドーピングされた多結
晶シリコン膜から成る特許請求の範囲第１項記載の半導
体装置。(2) The semiconductor device according to claim 1, wherein the semiconductor film is a polycrystalline silicon film doped with impurities. （３）一導電型の半導体基板上に半導体層を形成する工
程、該半導体前の主面に１又は２以上の半導体領域及び
その電極膜を形成する工程、前記半導体基板の裏面に半
導体膜を形成し、この半導体膜を半導体装置の一電極膜
とする工程を含むことを特徴とする半導体装置の製造方
法。(3) A step of forming a semiconductor layer on a semiconductor substrate of one conductivity type, a step of forming one or more semiconductor regions and their electrode films on the main surface in front of the semiconductor, and a step of forming a semiconductor layer on the back surface of the semiconductor substrate. 1. A method for manufacturing a semiconductor device, comprising the steps of forming a semiconductor film and using the semiconductor film as one electrode film of the semiconductor device. （４）前記半導体膜を通して半導体基板中へ不純物拡散
を施すことを特徴とする特許請求の範囲第３項記載の半
導体装置の製造方法。(4) A method for manufacturing a semiconductor device according to claim 3, characterized in that impurities are diffused into the semiconductor substrate through the semiconductor film.
JP60075887A 1985-04-09 1985-04-09 Semiconductor device and manufacture thereof Pending JPS61234041A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60075887A JPS61234041A (en) 1985-04-09 1985-04-09 Semiconductor device and manufacture thereof

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Application Number Priority Date Filing Date Title
JP60075887A JPS61234041A (en) 1985-04-09 1985-04-09 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS61234041A true JPS61234041A (en) 1986-10-18

Family

ID=13589254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60075887A Pending JPS61234041A (en) 1985-04-09 1985-04-09 Semiconductor device and manufacture thereof

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Country Link
JP (1) JPS61234041A (en)

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Publication number Priority date Publication date Assignee Title
JPS6243168A (en) * 1985-08-21 1987-02-25 Rohm Co Ltd Individual semiconductor device
JPS63187624A (en) * 1987-01-30 1988-08-03 Tadahiro Omi Semiconductor device
JPS63211635A (en) * 1987-02-26 1988-09-02 Nec Corp Semiconductor device
JPH01256129A (en) * 1988-04-06 1989-10-12 Sumitomo Electric Ind Ltd Manufacture of semiconductor device
JPH03236225A (en) * 1990-02-14 1991-10-22 Nippondenso Co Ltd Manufacture of semiconductor device
EP0971418A3 (en) * 1998-06-30 2001-11-07 Harris Corporation Semiconductor device having reduced effective substrate resistivity and associated methods
JP2002313795A (en) * 2001-04-18 2002-10-25 Shin Etsu Handotai Co Ltd Silicon single crystal wafer with high-melting-point metallic film and its manufacturing method, and method for impurity gettering in silicon single crystal
JP2003282589A (en) * 2002-03-26 2003-10-03 Denso Corp Method for manufacturing semiconductor device
US7145254B2 (en) 2001-07-26 2006-12-05 Denso Corporation Transfer-molded power device and method for manufacturing transfer-molded power device
JP2007019412A (en) * 2005-07-11 2007-01-25 Denso Corp Semiconductor device and its manufacturing method
JP2009522802A (en) * 2006-01-09 2009-06-11 テクニオン リサーチ アンド ディベロップメント ファウンデーション リミティド Transistor structure and manufacturing method thereof
JP2017139292A (en) * 2016-02-02 2017-08-10 富士電機株式会社 Semiconductor device and manufacturing method of the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5323569A (en) * 1976-08-18 1978-03-04 Toshiba Corp Semiconductor device
JPS6169122A (en) * 1984-09-12 1986-04-09 Nec Kansai Ltd Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5323569A (en) * 1976-08-18 1978-03-04 Toshiba Corp Semiconductor device
JPS6169122A (en) * 1984-09-12 1986-04-09 Nec Kansai Ltd Manufacture of semiconductor device

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6243168A (en) * 1985-08-21 1987-02-25 Rohm Co Ltd Individual semiconductor device
JPS63187624A (en) * 1987-01-30 1988-08-03 Tadahiro Omi Semiconductor device
JPS63211635A (en) * 1987-02-26 1988-09-02 Nec Corp Semiconductor device
JPH01256129A (en) * 1988-04-06 1989-10-12 Sumitomo Electric Ind Ltd Manufacture of semiconductor device
US6498366B1 (en) 1990-02-14 2002-12-24 Denso Corporation Semiconductor device that exhibits decreased contact resistance between substrate and drain electrode
US6949434B2 (en) 1990-02-14 2005-09-27 Denso Corporation Method of manufacturing a vertical semiconductor device
US5689130A (en) * 1990-02-14 1997-11-18 Nippondenso Co., Ltd. Vertical semiconductor device with ground surface providing a reduced ON resistance
US5994187A (en) * 1990-02-14 1999-11-30 Nippondenso Co., Ltd. Method of manufacturing a vertical semiconductor device
US5663096A (en) * 1990-02-14 1997-09-02 Nippondenso Co., Ltd. Method of manufacturing a vertical semiconductor device with ground surface providing a reduced ON resistance
JPH03236225A (en) * 1990-02-14 1991-10-22 Nippondenso Co Ltd Manufacture of semiconductor device
US7064033B2 (en) 1990-02-14 2006-06-20 Denso Corporation Semiconductor device and method of manufacturing same
US6649478B2 (en) 1990-02-14 2003-11-18 Denso Corporation Semiconductor device and method of manufacturing same
US6903417B2 (en) 1990-02-14 2005-06-07 Denso Corporation Power semiconductor device
EP0971418A3 (en) * 1998-06-30 2001-11-07 Harris Corporation Semiconductor device having reduced effective substrate resistivity and associated methods
JP2002313795A (en) * 2001-04-18 2002-10-25 Shin Etsu Handotai Co Ltd Silicon single crystal wafer with high-melting-point metallic film and its manufacturing method, and method for impurity gettering in silicon single crystal
US7145254B2 (en) 2001-07-26 2006-12-05 Denso Corporation Transfer-molded power device and method for manufacturing transfer-molded power device
DE10234155B4 (en) * 2001-07-26 2009-03-05 Denso Corp., Kariya-shi Press-molded power component
JP2003282589A (en) * 2002-03-26 2003-10-03 Denso Corp Method for manufacturing semiconductor device
JP2007019412A (en) * 2005-07-11 2007-01-25 Denso Corp Semiconductor device and its manufacturing method
JP2009522802A (en) * 2006-01-09 2009-06-11 テクニオン リサーチ アンド ディベロップメント ファウンデーション リミティド Transistor structure and manufacturing method thereof
JP2017139292A (en) * 2016-02-02 2017-08-10 富士電機株式会社 Semiconductor device and manufacturing method of the same

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