JPS61229328A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61229328A JPS61229328A JP60071778A JP7177885A JPS61229328A JP S61229328 A JPS61229328 A JP S61229328A JP 60071778 A JP60071778 A JP 60071778A JP 7177885 A JP7177885 A JP 7177885A JP S61229328 A JPS61229328 A JP S61229328A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- metal
- semiconductor material
- electrode
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 60
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000007747 plating Methods 0.000 claims description 16
- 238000005498 polishing Methods 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 abstract description 22
- 239000002184 metal Substances 0.000 abstract description 21
- 229910052751 metal Inorganic materials 0.000 abstract description 21
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、プレーティラドヒートシンク（Ｐｌａｔｅｄ
Ｈｅａｔ ５ｉｎｋ、以下ＰＨ８と称する）構造からな
る半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a plated heat sink.
The present invention relates to a method for manufacturing a semiconductor device having a heat 5 ink (hereinafter referred to as PH8) structure.
たとえば、ガンダイオード、インバットダイオード等の
半導体装置においてはその動作時の電カー失が大きく、
かつ微少領域に発熱が集中するため、半導体材料の温度
上昇が著るしく素子の劣化をもたらすため、厚メツキ金
属による熱放散を計る手段として上述したＰＨ８構造が
知られている。For example, semiconductor devices such as Gunn diodes and Invat diodes lose a large amount of electricity during their operation.
In addition, since heat generation is concentrated in a minute area, the temperature rise of the semiconductor material significantly causes deterioration of the element. Therefore, the above-mentioned PH8 structure is known as a means of measuring heat dissipation using thick plated metal.
従来、このＰＨ８構造は第２図に（ａ）ないしくｅ）に
示す方法で製造されていた。 ゛
まず、第２図（ａ）に示すように半導体ウェーハ１の能
動層領域側（図示せず。以下も同様）に全面にわたって
電極金属２を形成した上にメッキ法により、５０μｍ厚
程度０厚メッキ層３を形成する。そして第２図（ｂ）に
示すように半導体ウニ□−ハの反対側より研摩を行い半
導体材料を５０μｍ厚程度０厚くした後′、第２図（Ｃ
）に示すように電種金属４を選択的に設ける。さらに第
２図（ｄ） Ｇこ示すように電極金属４をマスクに半導
体材料をエツチングし、第２図（ｅ）に示すように厚メ
ッキ層３をしかるべき方法で切断する。Conventionally, this PH8 structure has been manufactured by the method shown in FIGS. 2(a) to 2(e). First, as shown in FIG. 2(a), an electrode metal 2 is formed over the entire surface of the semiconductor wafer 1 on the active layer region side (not shown; the same applies hereafter), and then a layer of about 50 μm thick is formed by plating. A plating layer 3 is formed. Then, as shown in Fig. 2(b), the semiconductor material was polished from the opposite side to make the semiconductor material thicker by about 50 μm.
), the electrolytic metal 4 is selectively provided. Further, as shown in FIG. 2(d), the semiconductor material is etched using the electrode metal 4 as a mask, and the thick plating layer 3 is cut by an appropriate method as shown in FIG. 2(e).
ところが、従来方法では次のような欠点があった。まず
、第２図（ｂ）の工程において、厚メツキ側を研摩用重
りにはりつけて半導体材料を研摩するか、必ずしも厚さ
が均一に形成されていない厚メッキ層３の表面を基準に
研摩を行うため、半導体材料の厚さの均一性が実現しに
くかった。またその後のプロセスにおいても、半導体材
料とメッキ層の熱膨張率の違いや、ウェーハのソリ等に
より半導体材料に割れが生じ易くその後の工程が困難に
なっていた。However, the conventional method has the following drawbacks. First, in the process shown in FIG. 2(b), the semiconductor material is polished by attaching the thick plated side to a polishing weight, or the semiconductor material is polished based on the surface of the thick plated layer 3, which does not necessarily have a uniform thickness. Because of this, it was difficult to achieve uniformity in the thickness of the semiconductor material. Further, in subsequent processes, cracks tend to occur in the semiconductor material due to differences in thermal expansion coefficients between the semiconductor material and the plating layer, warpage of the wafer, etc., making subsequent steps difficult.
さらに、第２図（ｅ）の工程で、厚メッキ層を切断する
ための高価な装置たとえばいわゆるダイサと称される装
置が必要となる。Furthermore, the process shown in FIG. 2(e) requires an expensive device, such as a so-called dicer, for cutting the thick plating layer.
また、同じＰＨ８構造を形成するため第３図（ａ）ない
しくｅ） ｊこ示す方法も知られている。まず、第３図
（ａ）に示す様に半導体ウェーハ１１の必要部分に電極
金属１２を、その周囲にメッキ付着防止の絶縁膜１３を
形成した状態にて形成し、この電極金属１４上に厚メッ
キ層１４を形成する。すると、この厚メッキ層１４は初
めより他と分離された形状として形成される。Furthermore, a method shown in FIGS. 3(a) to 3(e) is also known for forming the same PH8 structure. First, as shown in FIG. 3(a), an electrode metal 12 is formed on a necessary portion of a semiconductor wafer 11, with an insulating film 13 formed around it to prevent plating adhesion, and a thick layer is formed on the electrode metal 14. A plating layer 14 is formed. Then, this thick plating layer 14 is formed in a shape separated from others from the beginning.
次に第３図（ロ）に示すように研摩用重り１５に、ワッ
クス１６によって前記半導体ウェーハ１１の・厚メツキ
層１４面をはりつけ、この半導体ウェー、ハ１１の反対
側より研摩を行った後、第３図（Ｃ）に示すように両面
目合せ露光法により電極金属１７を設け、第２図（ロ）
に示すように電極金属１７をマスクに半導体材料をエツ
チングする。そして、絶縁膜１３、ワックス１６を除去
すると、第３図（ｅ）に示すようにＰＨ８構造ができる
。Next, as shown in FIG. 3(B), the thick plating layer 14 side of the semiconductor wafer 11 is attached to the polishing weight 15 using wax 16, and the semiconductor wafer is polished from the opposite side of the wafer 11. As shown in FIG. 3(C), the electrode metal 17 is provided by the double-sided aligned exposure method, and as shown in FIG. 2(B).
The semiconductor material is etched using the electrode metal 17 as a mask as shown in FIG. Then, when the insulating film 13 and wax 16 are removed, a PH8 structure is obtained as shown in FIG. 3(e).
ところが、この方法によっても第２図の実施例に示した
半導体材料膜厚の不均一性の問題は解決できず、さらに
、第３図（Ｃ）の工程で両面目合せ露光法の為の高価な
装置が必要となる。However, even with this method, the problem of non-uniformity in the thickness of the semiconductor material shown in the embodiment shown in FIG. 2 cannot be solved, and furthermore, the process shown in FIG. equipment is required.
本発明は、このような事情に基づいてなされたものであ
りミ高価な装置の導入なくして製造歩留りの良好なＰＨ
８構造を得る半導体装置の製造方法を提供するにある。The present invention was made based on these circumstances, and it is possible to achieve a PH with a good manufacturing yield without introducing expensive equipment.
An object of the present invention is to provide a method for manufacturing a semiconductor device that obtains an eight-structure structure.
このような目的を達成するため、本発明は半導体ウェー
ハの一面ζこ、複数の分離された電極、さらにその電極
面に厚メッキ層を形成する第１の工程と、前記厚メッキ
層の間に位置づけられる半導体領域を適当な深さにエツ
チングする第２の工程と、前記エツチングにより形成さ
れた半導体領域の凹陥部の底面を基準とし、前記半導体
ウェーハを他の面から研摩を行う第３の工程と、少なく
とも、前記電極に接続された半導体のエツチング面に電
極を形成する第５の工程と、前記第４の工程にいう機械
的固定状態を解除する第６の工程からなるようにしたも
のである。In order to achieve such an object, the present invention includes a first step of forming a plurality of separated electrodes on one surface of a semiconductor wafer, a thick plating layer on the electrode surface, and a step of forming a thick plating layer between the thick plating layer. a second step of etching the semiconductor region to be located to an appropriate depth; and a third step of polishing the semiconductor wafer from the other side using the bottom surface of the recessed portion of the semiconductor region formed by the etching as a reference. and at least a fifth step of forming an electrode on the etched surface of the semiconductor connected to the electrode, and a sixth step of releasing the mechanically fixed state referred to in the fourth step. be.
第１図（ａ）ないしくｄ）は本発明による半導体装置の
製造方法の一実施例を示す工程図である。まず、第１図
（ａ）に示す様に、半導体ウェーハ２１の必要部分に電
極金属２２を、その周囲に絶縁膜２．３を、さらにその
周囲にレジスト２４を形成する。そして、前記電極金属
２２上に厚メッキ層２５を形成する。次に第１図（ｂ）
に示す様にレジスト２４を除去した部分より半導体材料
のエツチングをする。FIGS. 1(a) to 1(d) are process diagrams showing an embodiment of a method for manufacturing a semiconductor device according to the present invention. First, as shown in FIG. 1(a), an electrode metal 22 is formed on a necessary portion of a semiconductor wafer 21, an insulating film 2.3 is formed around it, and a resist 24 is formed around it. Then, a thick plating layer 25 is formed on the electrode metal 22. Next, Figure 1(b)
As shown in FIG. 3, the semiconductor material is etched from the area where the resist 24 has been removed.
このエツチング深さは形成すべき半導体装置の厚さより
大きなものとする。次に第１図（Ｃ）に示す様に、ウェ
ーハを研摩用重り２６に、ワックス２フによりはりつけ
半導体ウェーハの反対側より研摩を行い半導体材料を薄
くする。この際、既にエツチングした半導体材料の形状
（第１図の）中点線に示した円形部）をモニターしなが
ら研摩を進めることにより、半導体ウェーハ面と平行な
研摩を実現することは容易である。このような研摩は各
電極金属２２と接続された半導体材料がそれぞれ分離さ
れるまで行われる。その後第１図（Ｃ）に示すように、
半導体材料のエツチングを行い厚さを最適化する。この
エツチング深さは均一に行われる。This etching depth is greater than the thickness of the semiconductor device to be formed. Next, as shown in FIG. 1C, the wafer is attached to a polishing weight 26 using wax 2 and polished from the opposite side of the semiconductor wafer to thin the semiconductor material. At this time, by proceeding with polishing while monitoring the shape of the already etched semiconductor material (circular portion shown by the dotted line in FIG. 1), it is easy to realize polishing parallel to the surface of the semiconductor wafer. Such polishing is performed until the semiconductor material connected to each electrode metal 22 is separated. After that, as shown in Figure 1 (C),
Optimize the thickness by etching the semiconductor material. This etching depth is uniform.
そして電極金Ｒ２８を真空蒸着法により付着し、ワック
ス２６を除去する。これにより、ワックス２６上に形成
された金属層２８と半導体材料上に形成された電極金属
２８とは段差部によって切断されていることから、各半
導体装置は容易に分離される。Electrode gold R28 is then deposited by vacuum evaporation, and wax 26 is removed. Thereby, since the metal layer 28 formed on the wax 26 and the electrode metal 28 formed on the semiconductor material are cut by the stepped portion, each semiconductor device can be easily separated.
このように構成した半導体装置の製造方法において、エ
ツチングされた半導体層面を基準として他方の面から研
摩（機械的）がなされている。すなわち、エツチングに
よる化学処理はその深さが均一にして凹陥部が形成され
ることになり、その均一な深さに形成された裏面を基準
（モニタで認識しながら）として、反対側から研摩を行
っていることから半導体ウェーハ面と平行に研摩がなさ
れることになる。そして、このようにして前記凹陥部の
表面に近接するまで半導体ウェーハを研摩した後、さら
にエツチングにより所定の深さにエツツチングを施こし
ていることから、その深さも均一となり結局は電極金属
２２．２８間の半導体材料層厚が均一になる。In the method for manufacturing a semiconductor device constructed in this way, polishing (mechanical) is performed from the other surface with the etched semiconductor layer surface as a reference. In other words, the chemical treatment by etching creates a concave portion with a uniform depth, and polishing is performed from the opposite side using the back surface formed with the uniform depth as a reference (while recognizing it on the monitor). Because of this, polishing is done parallel to the semiconductor wafer surface. After the semiconductor wafer is polished until it comes close to the surface of the recess in this way, etching is further performed to a predetermined depth, so that the depth becomes uniform and eventually the electrode metal 22. The thickness of the semiconductor material layer between 28 becomes uniform.
また上述した製造工程の説明から明らかなように、ダイ
サ、あるいは両面目金せ装置等の大規模な装置を必要と
することがなくなる。Furthermore, as is clear from the above description of the manufacturing process, there is no need for large-scale equipment such as a dicer or a double-sided metallization device.
以上説明したように、本発明による半導体装置の製造方
法によれば、高価な装置の導入なくして製造歩留りの良
好なＰＨ８構造を得ることができるようになる。As described above, according to the method of manufacturing a semiconductor device according to the present invention, a PH8 structure with a good manufacturing yield can be obtained without introducing expensive equipment.
−第１図は本発明による半導体装置の一実施例を示す工
程図、第２図は従来の半導体装置の製造方法の一例を示
す工程図、第３図は従来の半導体装置の他の製造方法の
他の例を示す工程図である。
２１・・・半導体ウェーハ、２２．２８・・・電極金属
、２３・・・絶縁膜、２４・・・レジスト、２５・・・
厚メッキ層、２６・・・研摩用重り、２７・・・ワック
ス。- Fig. 1 is a process diagram showing an embodiment of a semiconductor device according to the present invention, Fig. 2 is a process diagram showing an example of a conventional method for manufacturing a semiconductor device, and Fig. 3 is another conventional method for manufacturing a semiconductor device. It is a process diagram which shows another example. 21...Semiconductor wafer, 22.28...Electrode metal, 23...Insulating film, 24...Resist, 25...
Thick plating layer, 26... polishing weight, 27... wax.
Claims (1)
その電極面に厚メッキ層を形成する第１の工程と、前記
厚メッキ層の間に位置づけられる半導体領域を適当な深
さにエッチングする第２の工程と、前記エッチングによ
り形成された半導体領域の凹陥部の底面を基準とし、前
記半導体ウェーハを他の面から研摩を行う第３の工程と
、少なくとも前記電極に接続された半導体を機械的に固
定した状態にて前記研摩面をエッチングし、このエッチ
ングを前記電極に接続された各半導体が物理的に分離さ
れるまで行う第４の工程と、少なくとも前記電極に接続
された半導体のエッチング面に電極を形成する第５の工
程と、前記第４の工程にいう機械的固定状態を解除する
第６の工程とからなることを特徴とする半導体装置の製
造方法。A first step of forming a plurality of separated electrodes on one surface of a semiconductor wafer and a thick plating layer on the electrode surface, and a second step of etching a semiconductor region positioned between the thick plating layers to an appropriate depth. a third step of polishing the semiconductor wafer from the other side using the bottom surface of the recess in the semiconductor region formed by the etching as a reference, and mechanically polishing at least the semiconductor connected to the electrode. a fourth step of etching the polished surface in a fixed state and performing this etching until each semiconductor connected to the electrode is physically separated; and at least etching the etched surface of the semiconductor connected to the electrode A method for manufacturing a semiconductor device, comprising a fifth step of forming an electrode, and a sixth step of releasing the mechanically fixed state referred to in the fourth step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60071778A JPS61229328A (en) | 1985-04-04 | 1985-04-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60071778A JPS61229328A (en) | 1985-04-04 | 1985-04-04 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61229328A true JPS61229328A (en) | 1986-10-13 |
Family
ID=13470364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60071778A Pending JPS61229328A (en) | 1985-04-04 | 1985-04-04 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61229328A (en) |
-
1985
- 1985-04-04 JP JP60071778A patent/JPS61229328A/en active Pending
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