JPS61222132A - Production unit for semiconductor - Google Patents
Production unit for semiconductorInfo
- Publication number
- JPS61222132A JPS61222132A JP6473685A JP6473685A JPS61222132A JP S61222132 A JPS61222132 A JP S61222132A JP 6473685 A JP6473685 A JP 6473685A JP 6473685 A JP6473685 A JP 6473685A JP S61222132 A JPS61222132 A JP S61222132A
- Authority
- JP
- Japan
- Prior art keywords
- sample
- treatment
- negative potential
- semiconductor manufacturing
- manufacturing apparatus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000010409 thin film Substances 0.000 claims abstract description 5
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 10
- 238000010884 ion-beam technique Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 230000004075 alteration Effects 0.000 claims 1
- 238000009832 plasma treatment Methods 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000004381 surface treatment Methods 0.000 abstract description 3
- 238000005121 nitriding Methods 0.000 abstract 1
- 239000012495 reaction gas Substances 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 20
- 230000000694 effects Effects 0.000 description 8
- 208000033999 Device damage Diseases 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体製造装置に関し、さらに詳細には、半
導体素子製造工程においてイオンビームを使用して微細
加工又は薄膜形成等の表面処理を行なう装置に関するも
のである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor manufacturing device, and more particularly, to a device that performs surface treatment such as microfabrication or thin film formation using an ion beam in a semiconductor device manufacturing process. It is related to.
半導体集積回路は、ますます高集積化の要求が厳しくな
っており、パターンの微細化及びゲート絶縁膜等の薄膜
化が進んでいる。現在、パターンの微細化の要求に対応
するため、平行平板型プラズマエツチング装置による反
応性イオンエツチング（以下、ＲＩＢと略す）技術が多
用されているが、このＲＩＥでは条件により１００ｖ以
上の自己バイアス電圧が印加されることがあり、デ／Ｎ
Ｊイス損傷が今後の大きな問題となっている。一方、カ
ウフマン型イオン源を用いた反応性イオンビームエツチ
ング（以下、ＲＩＢＥと略す）装置の場合は、イオンを
加速するのにＩＫＶに近い電圧を印加している。また電
子サイクロトロン共鳴（以下、ＥＣＲと略す）現象を利
用したイオン源を用いたＲＩＢＥ装置の場合は、このよ
うなイオン加速用グリッドなしでも大電流を得られ、微
細パターンの加工だけでなく、薄膜形成等においてもＥ
ＣＲイオン源を利用した装置による方法が注目されてい
る。2. Description of the Related Art Semiconductor integrated circuits are increasingly required to be highly integrated, and patterns are becoming finer and gate insulating films and the like are becoming thinner. Currently, in order to meet the demand for finer patterns, reactive ion etching (hereinafter abbreviated as RIB) technology using parallel plate plasma etching equipment is often used. may be applied, and de/N
Damage to J-chairs is becoming a major problem in the future. On the other hand, in the case of a reactive ion beam etching (hereinafter abbreviated as RIBE) apparatus using a Kauffman type ion source, a voltage close to IKV is applied to accelerate ions. In addition, in the case of a RIBE device that uses an ion source that utilizes the electron cyclotron resonance (hereinafter abbreviated as ECR) phenomenon, a large current can be obtained without such an ion acceleration grid, and it can be used not only for processing fine patterns but also for processing thin films. E in formation etc.
A method using an apparatus using a CR ion source is attracting attention.
第２図及び第３図は従来のプラズマ処理装置を示し、図
において、１はイオン源、２はイオンビーム、３は試料
、４はこの試料の載置された試料台である。2 and 3 show a conventional plasma processing apparatus. In the figures, 1 is an ion source, 2 is an ion beam, 3 is a sample, and 4 is a sample stage on which the sample is placed.
しかし、従来のプラズマ処理装置では、第２図及び第３
図に示したように試料台４の電位を接地又は浮遊状態に
しており、このような状態ではエツチング等の処理速度
が遅い、あるいはイオン電流が不安定になる等の問題が
あった。However, in conventional plasma processing equipment,
As shown in the figure, the potential of the sample stage 4 is grounded or in a floating state, and in such a state there are problems such as slow etching processing speed or unstable ion current.
この発明の目的は、これらの問題点を解消するためにな
されたもので、処理速度が速く、安定なイオン電流を有
する半導体製造装置を得ることである。The purpose of the present invention was to solve these problems, and it is an object of the present invention to provide a semiconductor manufacturing apparatus that has a high processing speed and a stable ion current.
この発明に係る半導体製造装置は、プラズマ処理する際
に、試料を負電位にするようにしたものである。In the semiconductor manufacturing apparatus according to the present invention, a sample is brought to a negative potential during plasma processing.
この発明においては、プラズマ処理の際に試料を負電位
にしたから、プラズマ処理速度が増大し、安定な処理が
可能となった。In this invention, since the sample was brought to a negative potential during plasma treatment, the plasma treatment speed increased and stable treatment became possible.
以下、この発明の一実施例を図について説明する。第１
図は本発明の一実施例による半導体製造装置を示し、図
において、ｌは試料に照射するイオンビームを発生する
イオン源、２は該イオン源１から発生されたイオンビー
ム（プラズマ流）、３はエツチング等を行なうべき試料
、４は該試料３の設置された試料台であり、この試料台
４には電源５により負の電位が印加されている。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a semiconductor manufacturing apparatus according to an embodiment of the present invention, in which l is an ion source that generates an ion beam to irradiate a sample, 2 is an ion beam (plasma flow) generated from the ion source 1, and 3 Reference numeral 4 denotes a sample to be etched, etc., and 4 is a sample stage on which the sample 3 is placed. A negative potential is applied to this sample stage 4 by a power source 5.
このような構成になる本実施例装置において、イオン源
１より引き出されたプラズマ流２は、負の電位を印加さ
れた試料台４上に設置された試料３に照射され、プラズ
マ処理が行なわれる。In the apparatus of this embodiment having such a configuration, the plasma flow 2 extracted from the ion source 1 is irradiated onto the sample 3 placed on the sample stage 4 to which a negative potential is applied, and plasma processing is performed. .
ここで、上記装置を使用して、多結晶シリコンの微細パ
ターンをエツチング加工した場合の作用効果について以
下に説明する。Here, the effects when etching a fine pattern of polycrystalline silicon using the above-mentioned apparatus will be described below.
反応性ガスとして六フッ化イオン（ＳＦ４）をイオン源
１に導入し、２．４５Ｇ Ｈｚのマイクロ波と８７６Ｇ
の磁場を印加することによりＥＣＲ現象を起こして、高
密度プラズマ流２を発生し、−４０ｖ程度の電圧を印加
し負電位となった試料台４上の試料３をエツチング加工
した。この場合、マイクロ波電力を５００Ｗ、エツチン
グ処理室のガス圧力を０．１５Ｐａとして多結晶シリコ
ンを毎分２３Ｑｎｍ以上の高速度にてエツチング加工す
ることが可能であった。試料台４の電位を、接地又は浮
遊状態にした場合のエツチング速度は、それぞれ毎分２
００ｎｍと２１０ｎｍであり、このような従来のものに
比し明らかに高速度でエツチング可能なことがわかる。Hexafluoride ions (SF4) were introduced into the ion source 1 as a reactive gas, and 2.45 GHz microwave and 876 G
By applying a magnetic field of , an ECR phenomenon was caused to generate a high-density plasma flow 2, and a voltage of about -40 V was applied to etching the sample 3 on the sample stage 4, which had a negative potential. In this case, it was possible to etch polycrystalline silicon at a high speed of 23 Qnm per minute or more using microwave power of 500 W and gas pressure in the etching chamber of 0.15 Pa. The etching speed when the potential of the sample stage 4 is grounded or floating is 2/min.
00 nm and 210 nm, and it can be seen that etching can be performed at a clearly higher speed than the conventional method.
また浮遊状態の場合、エツチングが不安定であった。Furthermore, in the floating state, etching was unstable.
このように本発明では、試料台４に適度な負電位を印加
することによってプラズマ処理速度を増大させること、
及び安定な処理を行なうことが可能となった。ここで、
負電位としてはデバイスの損傷を考慮して−１Ｖ〜−１
００ｖが適当である。In this way, in the present invention, the plasma processing speed is increased by applying an appropriate negative potential to the sample stage 4,
And it became possible to perform stable processing. here,
The negative potential is -1V to -1 in consideration of damage to the device.
00v is appropriate.
特に、イオン源１としてイオン加速用グリッドなしのＥ
ＣＲ型イオン源を使用した場合加速電圧を低くでき、デ
バイス損傷を低減することができるが、本発明の場合、
試料を負電位にしているので、この試料に高エネルギー
の電子が照射されるのを弱める作用もあり、デバイス損
傷をさらに低減する効果がある。In particular, as the ion source 1, an E without an ion acceleration grid is used.
When using a CR type ion source, the acceleration voltage can be lowered and device damage can be reduced, but in the case of the present invention,
Since the sample is at a negative potential, it also has the effect of weakening the irradiation of high-energy electrons to the sample, which has the effect of further reducing device damage.
また、この発明による装置を使用することにより、試料
台へ印加する負電位を変えるだけで、イオンエネルギを
容易に制御することが可能であり、プラズマ処理する半
導体素子に応じてデバイス損傷を制御できることとなる
。Furthermore, by using the apparatus according to the present invention, it is possible to easily control ion energy by simply changing the negative potential applied to the sample stage, and device damage can be controlled depending on the semiconductor element to be plasma processed. becomes.
さらに以上述べた以外の効果として、イオンを試料近く
に集束し、プラズマ処理速度の均一性を向上できるとい
う効果もある。In addition to the above-mentioned effects, there is also the effect that ions can be focused near the sample and the uniformity of the plasma processing rate can be improved.
なお、以上はイオンビームを試料に照射しエツチング加
工する例について述べたが、この発明は、これに限定さ
れるものではなく、薄膜形成又は試料表面の酸化・窒化
等の表面処理等すべてのプラズマ処理装置に適用可能で
ある。Although the above has described an example of etching processing by irradiating a sample with an ion beam, this invention is not limited to this, and the present invention is applicable to all types of plasma processing such as thin film formation or surface treatment such as oxidation or nitridation of the sample surface. Applicable to processing equipment.
以上のようにこの発明に係る半導体製造装置によれば、
試料台を装置壁面に対し負電位とすることにより、プラ
ズマ処理速度を増大し、安定な処理が可能となる効果が
ある。As described above, according to the semiconductor manufacturing apparatus according to the present invention,
Setting the sample stage at a negative potential with respect to the wall surface of the apparatus has the effect of increasing the plasma processing speed and making stable processing possible.
第１図は本発明の一実施例による半導体製造装置の断面
図、第２図及び第３図は従来の半導体製造装置の断面図
である。
ｌ・・・イオン源、２・・・イオンビーム、３・・・試
料、４・・・試料台、５・・・電源。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a cross-sectional view of a semiconductor manufacturing apparatus according to an embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views of a conventional semiconductor manufacturing apparatus. l...Ion source, 2...Ion beam, 3...Sample, 4...Sample stage, 5...Power source. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (6)
試料を保持する試料台を装置壁面に対し負電位にする負
電圧印加手段とを備えたことを特徴とする半導体製造装
置。(1) A semiconductor manufacturing apparatus comprising: an ion source that irradiates a sample with an ion beam; and negative voltage application means that brings a sample stage holding the sample to a negative potential with respect to a wall surface of the apparatus.
を特徴とする特許請求の範囲第１項記載の半導体製造装
置。(2) The semiconductor manufacturing apparatus according to claim 1, wherein the negative potential is -1V to -100V.
とを特徴とする特許請求の範囲第１項又は第２項に記載
の半導体製造装置。(3) The semiconductor manufacturing apparatus according to claim 1 or 2, wherein the apparatus performs an etching process on a sample.
あることを特徴とする特許請求の範囲第１項又は第２項
に記載の半導体製造装置。(4) The semiconductor manufacturing apparatus according to claim 1 or 2, wherein the apparatus performs a thin film forming process on a sample.
を行なうものであることを特徴とする特許請求の範囲第
１項又は第２項に記載の半導体製造装置。(5) The semiconductor manufacturing apparatus according to claim 1 or 2, wherein the apparatus performs surface alteration treatment such as oxidation and nitridation on a sample.
）型イオン源であることを特徴とする特許請求の範囲第
１項ないし第５項のいずれかに記載の半導体製造装置。(6) The above ion source is equipped with electron cyclotron resonance (ECR).
6. The semiconductor manufacturing apparatus according to claim 1, wherein the semiconductor manufacturing apparatus is a type ion source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6473685A JPS61222132A (en) | 1985-03-27 | 1985-03-27 | Production unit for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6473685A JPS61222132A (en) | 1985-03-27 | 1985-03-27 | Production unit for semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61222132A true JPS61222132A (en) | 1986-10-02 |
Family
ID=13266727
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6473685A Pending JPS61222132A (en) | 1985-03-27 | 1985-03-27 | Production unit for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61222132A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02306618A (en) * | 1989-05-20 | 1990-12-20 | Sanyo Electric Co Ltd | Method of forming semiconductor thin film |
| JPH09102544A (en) * | 1995-05-09 | 1997-04-15 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
-
1985
- 1985-03-27 JP JP6473685A patent/JPS61222132A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02306618A (en) * | 1989-05-20 | 1990-12-20 | Sanyo Electric Co Ltd | Method of forming semiconductor thin film |
| JPH09102544A (en) * | 1995-05-09 | 1997-04-15 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
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