JPS61220398A - Printed multilayer interconnection board - Google Patents
Printed multilayer interconnection boardInfo
- Publication number
- JPS61220398A JPS61220398A JP6056685A JP6056685A JPS61220398A JP S61220398 A JPS61220398 A JP S61220398A JP 6056685 A JP6056685 A JP 6056685A JP 6056685 A JP6056685 A JP 6056685A JP S61220398 A JPS61220398 A JP S61220398A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- grid lines
- pattern
- intersections
- vertical
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
Ｃ＠明の利用分野〕
本発明は多渣印刷配腺板に係り、特にアース層又は電源
層の内層パターンを標準化し、信号層のパターンが変り
ても、その内層パターンは共用できるようにするだめの
設計手法に関するものである。[Detailed Description of the Invention] Field of Application of C@Ming] The present invention relates to a multi-resist printed wiring board, and in particular standardizes the inner layer pattern of the ground layer or power layer, so that even if the pattern of the signal layer changes, the inner layer Patterns are about design techniques that allow for sharing.
パターンの高蕾皮配蛾の設計手法としては。 As a design method for patterning high bud skin moths.
例えば尖公昭５７−５２９４９号公報に記載のよ５に。For example, as described in Japanese Patent No. 57-52949.
パターンの為ＶＢ匿化については有効であることが示さ
れている。しかし内層パターンの標準化あるいは共用で
きるような設計手法の点については配点されてはいなか
った。It has been shown that it is effective for VB concealment because of the pattern. However, no points were given for standardization of inner layer patterns or design methods that can be shared.
本発明の目的は、主基準格子上のランド間にバイヤホー
ルを有する多虐鴎刷配線板に於て。The object of the present invention is to provide a printed circuit board having via holes between lands on a main reference grid.
そのアース虐又は電源層の内層パターンを標準化あるい
は共用できるよ５な多層配線板を提供することにある。It is an object of the present invention to provide a multilayer wiring board that allows standardization or sharing of inner layer patterns of the ground or power layer.
生基準格子交点上のランド間に設けたバイヤールの位置
な、副格子婦の交点から一定寸法はず丁、ことによりバ
イヤホール相互間の距離を広げ、この結果、このバイヤ
ホール位置に相当するアース層又はＩＥ電源層内層位置
に、生基準格子交点上のクリアランスホールとぶつかる
箇所を除いては丸形のクリアランスホールの形成が可能
となり、アース層又は電源層の標準化あるいは共用を可
ｙＩｌｌ：とするものである。The position of the bayard between the lands on the raw standard grid intersection is a certain dimension from the intersection of the sub-grid, thereby increasing the distance between the via holes, and as a result, the ground layer corresponding to this via hole position is Or, it is possible to form a round clearance hole at the inner layer position of the IE power supply layer, except for the part where it collides with the clearance hole on the raw reference grid intersection, and it is possible to standardize or share the ground layer or power supply layer. It is.
以下１本発明の一夾に例を帛１凶及び第２図によりｌｓ
！明する。The following is an example of one aspect of the present invention according to Figure 1 and Figure 2.
! I will clarify.
縦・横両方向に設けた主基準裕子巌１，２の交点に、搭
教Ｓ品の端子が挿入される穴３及びランド４を位置させ
、そのランド４間に、主基準格子−間を５寺分し、その
匂及び乞の位ｔｉｔに縦・横各々２本の銅格子＄１５．
６を設定し、この副格子源上に一定の太さの信号層パタ
ーン７を配置する。また、秩・横両方向の副格子腺の交
点４ヶの５ち、、＃）方向に相対する２ケの交点から・
各々斜方向外１＋１１１ Ｋ一定寸法はずれた位置８．
９にバイヤホール１０を２ケだけ設げるようＫしたので
、斜方向に相対する２ケのバイヤホール相互間の短点な
広げ、このバイヤホール１゜の位置に相当するアース層
又は電飄層の内層位置１１４’Ｃ，土着準裕子交点上の
クリアランスホール１２とぶつかる箇所を除いては、丸
形のクリアランスホール１３が形成されている。At the intersection of the main reference grids 1 and 2 provided in both the vertical and horizontal directions, the hole 3 into which the terminal of the S product is inserted and the land 4 are located, and between the lands 4, the main reference grid - 5 Two copper grids each, vertically and horizontally, are placed between the temples and the smell and prayer area.$15.
6, and a signal layer pattern 7 of a constant thickness is placed on this sub-grating source. In addition, from the intersections of the four sublattice glands in both the vertical and horizontal directions, the intersections of the two opposite to the
Each diagonally outward 1+111K position 8.
Since only two via holes 10 are provided in 9, the two via holes facing each other in the diagonal direction are widened at a short point, and a ground layer or electrode corresponding to the 1° position of the via hole is formed. A round clearance hole 13 is formed except at the inner layer position 114'C of the layer, where it collides with the clearance hole 12 on the indigenous quasi-Yuko intersection.
以上述べたように一１本発明によればバイヤホールの位
置な副格子交点上から一定寸法はずすことＫより、バイ
ヤホール相互間の距離を広げ。As described above, according to the present invention, the distance between the via holes is increased by removing a certain dimension from the sub-lattice intersection point where the via holes are located.
この結果、このバイヤホール位置に相当するアース層又
は１を諒漕のＰ３層位置にクリアランスホールの設置が
可能となる。As a result, it becomes possible to install a clearance hole in the P3 layer position of the ground layer or 1 corresponding to the via hole position.
又、この手法は、生着！ＩＩ格子交点上にランドがない
場合に可能となる２不、４本混在パターンの場合や、ラ
ンド間に土着４１．格子腺間を６寺分し、その−、牝、
チの位置に銅格子味を設置し。Also, this method allows engraftment! When there is no land on the II lattice intersection, a mixed pattern of 2 or 4 patterns is possible, or if there is an indigenous 41. pattern between the lands. The space between the lattice glands is divided into 6 temples, and the -, female,
Install a copper lattice at the position.
この副格子峰上に一走の太さのパターンを配置するよう
ないわゆるランド間３本あるいは３本。There are so-called 3 or 3 lines between lands that arrange a pattern with the thickness of one run on this sub-lattice peak.
５本混在パターンの場合でも、前述したものと同僚、バ
イヤホール位置を副格子森の交点から一定寸法はず丁こ
とにＪりて、そのバイヤホールＩ／ｃ札当するアース層
又は電源層の内層位ばに。Even in the case of a 5-wire mixed pattern, as mentioned above, the via hole position must be a certain distance from the intersection of the sub-grids, and the inner layer of the ground layer or power layer that supports that via hole I/C. In the place.
丸形のクリアランスボールの設置が可能となる。It is possible to install a round clearance ball.
以上述へたよプに１本発明によれば、バイヤホールの位
置を＃ＩＪＪ格子父点から一定寸法はずすことにより、
バイヤボール布互間の距離なムげ。In addition to the above, according to the present invention, by moving the position of the via hole by a certain dimension from the #IJJ lattice father point,
The distance between the buyer ball cloths is very small.
この粕来、このバイヤホール位ｄに相当するアース層又
は電億層の円ノー位眩にクリアランスホールの設置が町
ｙεと７よるようにしたので、アース層又は１ｔｉ）ｉ
ｔ）壷を標準化したりあるいは信号層のパターンが変っ
てもその内層パターンは共用できるなどの効果がある。Since the installation of the clearance hole in the yen no daji of the earth layer or electric layer corresponding to this via hole position d was made so that it corresponds to the town yε and 7, the earth layer or 1ti) i
t) It has the effect of standardizing the pot or allowing the inner layer pattern to be shared even if the signal layer pattern changes.
＃！１図は１Ｍ考層のパターンｔｌｌ馨示す図、第２図
はアース層又は電源層のＰ’３７１パターン例を示す図
である。
１・・・主基準裕子１ｆｌＡ（縦方向）２°・・
（横方向〕
３・・・部品痛子神人穴
４・・・ｍ品層子挿入入部のランド
５・・・銅格子味（縦方向ン
６・・・銅格子味（横方向〕
７・・・信Ｊ１９埠パターン
８．９・・・祠裕子父点から一定寸法はすれた位置１０
・・・バイヤホール#! FIG. 1 is a diagram showing a pattern tll of a 1M layer, and FIG. 2 is a diagram showing an example of a P'371 pattern of a ground layer or a power layer. 1... Main reference Yuko 1flA (vertical direction) 2°...
(Horizontal direction) 3... Parts Itako Jinjin hole 4... Land of m-product layer child insertion part 5... Copper lattice taste (vertical direction 6... Copper lattice taste (horizontal direction)) 7. ...Shin J19 Bu pattern 8.9...Position 10, a certain distance away from Yuko Sato's father point
...buyer hall
Claims (1)
面層等に信号線用のパターン配線層（信号層）を有した
多層印刷配線板に於て、その信号層に縦・横方向に設け
た主基準格子線の交点上に搭載部品の端子が挿入される
穴及びランドを位置させ、そのランド間に、主基準格子
線間を５等分しその２／５及び３／５の位置に縦・横各
々２本の副格子線を設定してこの副格子線上に一定の太
さのパターンを配置し、且つ縦・横両方向の副格子線の
交点４個のうち斜方向に相対する２個の交点から各々斜
方向外側へ一定寸法はずれた位置に搭載部品の端子挿入
穴の穴径及びランド径よりも小さな穴径のパターン接続
専用のバイヤホールを２個設け、そのバイヤホール位置
に相当するアース層又は電源層の内層位置に丸形のクリ
アランスホールを形成できるようにしアース層又は電源
層の内層パターンを標準化あるいは共用できるように構
成したことを特徴とする多層印刷配線板。In a multilayer printed wiring board that has an earth layer or a power layer or both on the inner layer and a patterned wiring layer (signal layer) for signal lines on the surface layer, etc., the signal layer is provided in the vertical and horizontal directions. Position the holes and lands into which the terminals of the mounted components are inserted on the intersections of the main reference grid lines, and divide the space between the main reference grid lines into 5 equal parts between the lands at 2/5 and 3/5 positions. Two vertical and two horizontal sub-grid lines are set, a pattern of a certain thickness is placed on these sub-grid lines, and two of the four intersections of the vertical and horizontal sub-grid lines are placed opposite to each other in the diagonal direction. Two via holes dedicated to pattern connection with hole diameters smaller than the terminal insertion hole diameter and land diameter of the mounted components are provided at positions diagonally outward by a certain distance from the intersections of the two, and correspond to the via hole positions. 1. A multilayer printed wiring board characterized in that a round clearance hole can be formed in the inner layer position of the ground layer or power supply layer, and the inner layer pattern of the ground layer or power supply layer can be standardized or shared.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6056685A JPS61220398A (en) | 1985-03-27 | 1985-03-27 | Printed multilayer interconnection board |
| CA000501578A CA1237820A (en) | 1985-03-20 | 1986-02-11 | Multilayer printed circuit board |
| US06/828,717 US4636919A (en) | 1985-03-20 | 1986-02-12 | Multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6056685A JPS61220398A (en) | 1985-03-27 | 1985-03-27 | Printed multilayer interconnection board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61220398A true JPS61220398A (en) | 1986-09-30 |
| JPH0535596B2 JPH0535596B2 (en) | 1993-05-26 |
Family
ID=13145938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6056685A Granted JPS61220398A (en) | 1985-03-20 | 1985-03-27 | Printed multilayer interconnection board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61220398A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6846993B2 (en) | 2001-10-12 | 2005-01-25 | Nec Corporation | Multilayer printed wiring board and its manufacturing method |
-
1985
- 1985-03-27 JP JP6056685A patent/JPS61220398A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6846993B2 (en) | 2001-10-12 | 2005-01-25 | Nec Corporation | Multilayer printed wiring board and its manufacturing method |
| US7290333B2 (en) | 2001-10-12 | 2007-11-06 | Nec Corporation | Manufacturing method of a multilayer printed wiring board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0535596B2 (en) | 1993-05-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |