JPS61192116A - Hysteresis circuit - Google Patents
Hysteresis circuitInfo
- Publication number
- JPS61192116A JPS61192116A JP60031969A JP3196985A JPS61192116A JP S61192116 A JPS61192116 A JP S61192116A JP 60031969 A JP60031969 A JP 60031969A JP 3196985 A JP3196985 A JP 3196985A JP S61192116 A JPS61192116 A JP S61192116A
- Authority
- JP
- Japan
- Prior art keywords
- output
- potential
- input
- differential amplifier
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は入力装置等に用いられるヒステリシス回路に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hysteresis circuit used in input devices and the like.
従来、この種のヒステリシス特性をもつ入力装置にはい
ろいろなものがあシその例を第３図に示す。入力端子２
１と７リツプ・フロップ回路１２のセット入力端との間
にインバータ回路１６を挿入し、入力端子２１とクリッ
プ＠７０ツブ回路１２のリセット入力端との間ＶＣ２つ
のインバータ回路ｔ’ｙ、ｔｓを接続し、出力端子２２
から出力を取り出していた。入出力特性は第２図に示す
ように１出力が高レベルに反転する電圧はインバータ回
路１６のスレッシロールド電位ＶｔＨで決ま）。Conventionally, there are various types of input devices having this type of hysteresis characteristic, examples of which are shown in FIG. Input terminal 2
An inverter circuit 16 is inserted between the input terminal 1 and the set input terminal of the 70 flip-flop circuit 12, and two inverter circuits t'y and ts are connected between the input terminal 21 and the reset input terminal of the clip@70 flip-flop circuit 12. Connect and output terminal 22
I was getting the output from. As for the input/output characteristics, as shown in FIG. 2, the voltage at which one output is inverted to a high level is determined by the threshold voltage VtH of the inverter circuit 16).
出力が低レベルに反転する電圧はインバータ回路１７の
スレッシロールド電位ｖＬＬで決まっていた。The voltage at which the output is inverted to a low level is determined by the threshold voltage VLL of the inverter circuit 17.
しかしながら、これらスレッシロールド電圧ＶｔＨとＶ
ｔＬは次式で示される。However, these threshold voltages VtH and V
tL is expressed by the following formula.
ここでｖｔｒｔはＮチャンネルＭＯ８電解効果トランジ
スタ（以下、Ｎ−ＭＯＳＦＥＴと略す） 、 ＶＴＩＩ
はＰチャンネルＭＯ８電界効果トランジスタ（以下、Ｐ
−ＭＯＳＦＥＴと略す）、βｐｘｓはインバータ１６０
Ｐ−ＭＯＳＦＥＴのチャンネル導電係数、β８１６はイ
ンバータ１６のＮ−ＭＯＳＦＥＴのチャンネル導電係数
、βＰ１７・βＮ１７は同様にインバータ１７のＰ−・
Ｎ−ＭＯＳＦＥＴのチャンネル導電係ｔｉテロ；ｂ、コ
ｔＬうＶｙｓ、 Ｖｒｐ、 ／ｐｔｓ ” ／ＰＩＴ
。Here, vtrt is an N-channel MO8 field effect transistor (hereinafter abbreviated as N-MOSFET), VTII
is a P-channel MO8 field effect transistor (hereinafter referred to as P
- MOSFET), βpxs is the inverter 160
β816 is the channel conductivity coefficient of the P-MOSFET, β816 is the channel conductivity coefficient of the N-MOSFET of the inverter 16, and βP17 and βN17 are the P- and βN17 of the inverter 17.
Channel conductivity of N-MOSFET: b, Vys, Vrp, /pts” /PIT
.
βＮ１１ｌ・βＮｌ？は製造上それぞれ独立にバ２つき
、結果としてＶｔａ ｍ Ｖｔｔ、が製造上のバラツ
キによプ影響され、高精度なヒステリシス特性は得られ
ないという欠点がある。βN11l・βNl? have a disadvantage in that Vtam and Vtt are affected by manufacturing variations, making it impossible to obtain highly accurate hysteresis characteristics.
本発明の目的は以上の様な欠点を解決し、簡単な回路で
高精度なヒステリシス特性をもつ回路を提供することに
りる。An object of the present invention is to solve the above-mentioned drawbacks and provide a simple circuit with highly accurate hysteresis characteristics.
本発明によれば、第１の判定電圧以上の入力電圧で出力
を生じる第１の差動比較器と、８ｇｔの判定電圧よシも
低い第２の判定電圧以下の入力電圧で出力を生じる第２
の差動比較器と、ｓｇｔＯ差動比較器の出力をセット入
力端に受は第２の差動比′較器の出力をリセット入力端
に受けるフリップ会フロップ回路とを有するヒステリシ
ス回路を得る。According to the present invention, the first differential comparator generates an output at an input voltage equal to or higher than the first determination voltage, and the first differential comparator generates an output at an input voltage equal to or lower than the second determination voltage, which is lower than the determination voltage of 8gt. 2
A hysteresis circuit is obtained having a differential comparator, and a flip flop circuit whose set input terminal receives the output of the sgtO differential comparator and whose reset input terminal receives the output of the second differential comparator.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例である。電位発生源ｌからの
第１の基準電位■ｌが差動、増幅器４の非反転入力端子
５に入力され、電位発生源２からの第２の基準電位■２
が差動増幅器８０反転入力端子１Ｏ１Ｃ入力される。こ
れら差動増幅器４，８のそれぞれの出力端子７．１１は
ｆＬｓフリップ７０ツブ回路Ｌ２のセット入力端子１３
およびリセット入力端子１４に入力される。また、差動
増幅器４の反転入力端子６と差動増幅器８の非反転入力
端子９には信号入力端子３を介して入力電位ＶｒＮが入
力される。かくの如き、ヒステリシス回路においては、
入力電位■！Ｎが最低電位から第１の基準電位ＶＩＫ到
達するまでは几Ｓ ７１Ｊツブフロップ回路１２の出力
は反転せず、入力電位ＶＩＮが第１の基準電位Ｖ１を越
えると几Ｓフリップフロップ回路１２の出力は反転する
。入力電位ＶｔＳが第１の基準電位Ｖｒｐ越えてＲ８７
１Ｊツブフロップ回路１２の出力が反転した後に再度反
転するには入力電位ＶＩＮはＮ２の基準電位■２よシ小
さくならなければならない。故に第２図に示す入出力特
性となる。FIG. 1 shows an embodiment of the present invention. The first reference potential ■l from the potential generation source 1 is input to the non-inverting input terminal 5 of the differential amplifier 4, and the second reference potential ■2 from the potential generation source 2 is inputted to the non-inverting input terminal 5 of the differential amplifier 4.
is input to the inverting input terminal 1O1C of the differential amplifier 80. The output terminals 7 and 11 of these differential amplifiers 4 and 8 are the set input terminals 13 of the fLs flip 70 tube circuit L2.
and is input to the reset input terminal 14. Further, the input potential VrN is input to the inverting input terminal 6 of the differential amplifier 4 and the non-inverting input terminal 9 of the differential amplifier 8 via the signal input terminal 3. In a hysteresis circuit like this,
Input potential ■! The output of the S71J flip-flop circuit 12 is not inverted until N reaches the first reference potential VIK from the lowest potential, and when the input potential VIN exceeds the first reference potential V1, the output of the S flip-flop circuit 12 becomes Invert. When the input potential VtS exceeds the first reference potential Vrp, R87
In order to invert the output of the 1J tube flop circuit 12 again after it has been inverted, the input potential VIN must become smaller than the reference potential (2) of N2. Therefore, the input/output characteristics shown in FIG. 2 are obtained.
この時、差動増幅器４の出力反転レベルは第１の基準電
位■ｌに対し入力オフセット電圧の誤差しかなく、この
入力オフセット電圧は差動増幅器の構成上、■τＦ（も
しくはｖτＮ）、βデ（もしくはβＮ）の相対バラツキ
で決定され、従来のヒステリシス回路のスレッショール
ド電圧”ｔＨ、ＶｔＬのバラツキに比べて無視できる程
小さく、また差動増幅器８も同様である。At this time, the output inversion level of the differential amplifier 4 has only an error of the input offset voltage with respect to the first reference potential ■l, and due to the configuration of the differential amplifier, the input offset voltage is (or βN), and is negligibly small compared to the variations in threshold voltages "tH" and "VtL" of conventional hysteresis circuits, and the same applies to the differential amplifier 8.
第１および第２の基準電位Ｖｘ、Ｖｚを発生させるＫは
、−例として電源間を抵抗分割くより得る事ができるが
、この場合の誤差は分割抵抗の相対バラツキで決定され
る。K, which generates the first and second reference potentials Vx and Vz, can be obtained, for example, by resistor division between the power supplies, but the error in this case is determined by the relative variation of the divided resistors.
以上説明したように１本発明のヒステリシス回路のヒス
テリシス特性は差動増幅器の入力オ７セット電圧と第り
、第２の基準電位Ｖｌ、Ｖ２の精度で決定され、集積回
路上に入力オフセット電圧の小さな差動増幅器を作成す
る事や高い精度の電位を発生させることは容易であり、
従来のヒステリシス特性をもつ入力装置に較べて製造上
のバラツキを考慮する事なく高精度のヒステリシス特性
をもつ入力装置を作成する事ができる。更に本人力装置
では纂１．第２の基準電位Ｖｌ、Ｖ２を変える事によシ
同−回路でヒステリシス特性を変更する事がで、き、ア
ナログ信号をディジタル処理する場合のアナログ−ディ
ジタル変換装置等に非常に有用である。As explained above, the hysteresis characteristics of the hysteresis circuit of the present invention are determined by the accuracy of the second reference potentials Vl and V2, and the input offset voltage of the differential amplifier is determined by the accuracy of the second reference potentials Vl and V2. It is easy to create a small differential amplifier and generate a highly accurate potential.
Compared to conventional input devices with hysteresis characteristics, it is possible to create an input device with highly accurate hysteresis characteristics without considering manufacturing variations. Furthermore, in the case of a self-powered device, 1. By changing the second reference potentials Vl and V2, the hysteresis characteristics can be changed in the same circuit, and this is very useful for analog-to-digital converters and the like when digitally processing analog signals.
第１図は本発明によるヒステリシス回路の一実施例を示
すブロック図、第２図はヒステリシス回路の入出力関係
を示す特性図、第３図は従来のヒステリシス回路のブロ
ック図である。
１、 ２・・・・・・電位発生源、３・・・・・・信号
入力端子、４．８・・・・・・差動増幅器、５，９・・
・・・・差動増幅器の非反転入力端子、６．１０・・・
・・・差動増幅器の反転入力端子、７．１１・・・・・
・差動増幅器の出力端子、１２・・・・・・Ｒ，Ｓフリ
ップフロップ回路、１３・・・・・・几Ｓフリップ７０
ツブ回路のセット入力端子、１４・・・・・・ＲＩ８フ
リッグ７０ツブ回路のリセット入力端子、［５・・・・
・・出力端子。
緊１個
￥−２揖FIG. 1 is a block diagram showing an embodiment of the hysteresis circuit according to the present invention, FIG. 2 is a characteristic diagram showing the input/output relationship of the hysteresis circuit, and FIG. 3 is a block diagram of a conventional hysteresis circuit. 1, 2... Potential generation source, 3... Signal input terminal, 4.8... Differential amplifier, 5, 9...
...Non-inverting input terminal of differential amplifier, 6.10...
...Inverting input terminal of differential amplifier, 7.11...
・Output terminal of differential amplifier, 12...R, S flip-flop circuit, 13...S flip 70
Set input terminal of the tube circuit, 14... RI8 frig 70 reset input terminal of the tube circuit, [5...
...Output terminal. 1 piece ￥-2 yen
Claims (1)
動増幅器と、前記第１の判定電圧より低い第２の判定電
圧以下の入力信号で出力を生じる第２の差動増幅器２と
、前記第１および第２の差動増幅器の出力がそれぞれセ
ットおよびリセット入力端に入力されるＲＳフリップフ
ロップ回路とを備えたことを特徴とするヒステリシス回
路。a first differential amplifier that generates an output when an input signal is higher than a first determination voltage; and a second differential amplifier 2 that generates an output when an input signal is lower than or equal to a second determination voltage that is lower than the first determination voltage. , and an RS flip-flop circuit to which the outputs of the first and second differential amplifiers are input to set and reset input terminals, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60031969A JPS61192116A (en) | 1985-02-20 | 1985-02-20 | Hysteresis circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60031969A JPS61192116A (en) | 1985-02-20 | 1985-02-20 | Hysteresis circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61192116A true JPS61192116A (en) | 1986-08-26 |
Family
ID=12345779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60031969A Pending JPS61192116A (en) | 1985-02-20 | 1985-02-20 | Hysteresis circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61192116A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63275217A (en) * | 1987-05-06 | 1988-11-11 | Mitsubishi Electric Corp | Hysteresis comparator |
| JPH01137820A (en) * | 1987-11-25 | 1989-05-30 | Nec Corp | Clock generating circuit |
| KR100452231B1 (en) * | 2002-11-22 | 2004-10-08 | 전자부품연구원 | A comparator independent of the floating of power supply |
| EP2056083A2 (en) * | 2007-10-31 | 2009-05-06 | O2 Micro, Inc. | Auto-ranging thermistor-based temperature detection system |
| JP2012109948A (en) * | 2010-10-19 | 2012-06-07 | Yamaha Corp | Hysteresis device |
-
1985
- 1985-02-20 JP JP60031969A patent/JPS61192116A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63275217A (en) * | 1987-05-06 | 1988-11-11 | Mitsubishi Electric Corp | Hysteresis comparator |
| JPH01137820A (en) * | 1987-11-25 | 1989-05-30 | Nec Corp | Clock generating circuit |
| KR100452231B1 (en) * | 2002-11-22 | 2004-10-08 | 전자부품연구원 | A comparator independent of the floating of power supply |
| EP2056083A2 (en) * | 2007-10-31 | 2009-05-06 | O2 Micro, Inc. | Auto-ranging thermistor-based temperature detection system |
| JP2012109948A (en) * | 2010-10-19 | 2012-06-07 | Yamaha Corp | Hysteresis device |
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