JPS58218222A - Voltage comparator - Google Patents
Voltage comparatorInfo
- Publication number
- JPS58218222A JPS58218222A JP10112682A JP10112682A JPS58218222A JP S58218222 A JPS58218222 A JP S58218222A JP 10112682 A JP10112682 A JP 10112682A JP 10112682 A JP10112682 A JP 10112682A JP S58218222 A JPS58218222 A JP S58218222A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- input terminal
- capacitors
- trnt2
- trnt1
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は、感度と動作速度の向上を図った7リツブ・フ
ロップ形の電圧比較器に関するものである。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a seven-rib-flop type voltage comparator with improved sensitivity and operating speed.
技術の背景
従来、電圧比較器として、2個のトラyジスタ反転増幅
器を正帰還接続したクリップ・フロップ形のものが汎用
されている。この種電圧比較器は、第1図示のように、
pチャネル・トラてジスタpT1とnチャネル・トラン
ジスタnT1から成る第1の反転増幅器AMP1 と、
pチャネル・トランジスタpT2 トnチャネル・トラ
ンジスタnT2から成る第2の反転増幅器AMP2とが
正帰還接続されており、入力端子11に印加された入力
電圧vlと入力端子I2に印加された基準電圧VRとの
比較結果が出力端子01と02に出力される。その動作
を第2図を参照して説明すれば、時刻t1以前ではスイ
ンf51と52が共にオン状態であり、一方スイッチS
6はオフ状態となっている。従って入力端子11に供給
された信号電圧V、がコンデンサC1に充電され、これ
が出力電圧FORとして出力端子02に現われる。一方
入力端子I2に供給された基準電圧FRはコンデン−?
C2に充電され1、これが出力電圧VO1として出力
端子01に現われる。BACKGROUND OF THE INVENTION Conventionally, a clip-flop type voltage comparator in which two transistor inverting amplifiers are connected in a positive feedback manner has been widely used. This kind of voltage comparator is as shown in the first diagram.
a first inverting amplifier AMP1 consisting of a p-channel transistor pT1 and an n-channel transistor nT1;
A second inverting amplifier AMP2 consisting of a p-channel transistor pT2 and an n-channel transistor nT2 is connected in positive feedback, and the input voltage vl applied to the input terminal 11 and the reference voltage VR applied to the input terminal I2 are connected in positive feedback. The comparison results are output to output terminals 01 and 02. The operation will be explained with reference to FIG. 2. Before time t1, both the switches F51 and F52 are in the ON state, while the switch S
6 is in the off state. Therefore, the signal voltage V supplied to the input terminal 11 is charged to the capacitor C1, which appears at the output terminal 02 as the output voltage FOR. On the other hand, the reference voltage FR supplied to the input terminal I2 is capacitor -?
C2 is charged to 1, which appears at the output terminal 01 as an output voltage VO1.
その後時刻1.において、スイッチS1とS2がオフ状
態となシ、入力電圧Vxと基準電圧VRがコンデンサC
1とC2に保持される。時刻t3においてスイッチS6
がオン状態になるとノードN1の電圧VN1が直線的に
上昇し、この電圧と’Of * VO2との電圧がpチ
ャ炉ネル・トランジスタのゲート・ソース間閾値電圧F
TPを超えると、pテヤシネル・トランジスタpT1と
pT2が導通する。この結果コンデンサC1とC2がそ
れぞれpチャンネル・トランジスタpr1とpT2を介
して充電される。コンデンサC1とC2の充電電圧とバ
イアス端子B2との電圧差がnチャンネル・トランジス
タのゲート・ソース間閾値電圧FTNを超えると、nチ
ャンネル・トランジスタnT’lとnT1が導通する。Then time 1. , when switches S1 and S2 are in the off state, input voltage Vx and reference voltage VR are connected to capacitor C.
1 and C2. At time t3, switch S6
When turns on, the voltage VN1 at node N1 rises linearly, and the voltage between this voltage and 'Of*VO2 becomes the gate-source threshold voltage F of the p-channel channel transistor.
Beyond TP, p-tejacinel transistors pT1 and pT2 conduct. As a result, capacitors C1 and C2 are charged via p-channel transistors pr1 and pT2, respectively. When the voltage difference between the charging voltages of capacitors C1 and C2 and bias terminal B2 exceeds the gate-source threshold voltage FTN of the n-channel transistors, the n-channel transistors nT'l and nT1 become conductive.
この結果、コンデンサC1は、pチャンネル・トランジ
スタpT2を介して充電され右と同時にnチャンネル・
トランジスタnT2を介して放電される。同様に、コン
デンサC2は、トランジスタpT1を介して充電される
と同時にトラざジスタnT1を介して放電される。しか
しながらこれらMOS )ランジスタの電流はゲート・
ソース間電圧の2乗にほぼ比例するので、nチャンネル
・トランジスタnT1とnT’lの導通直後においては
、コンデンサの放電電流に比べて充電電流が大きく、こ
のためコンデンサC1と02の電圧はいずれも上昇し続
けるが、その上昇速度は漸次鈍化する。時刻1sにおい
てp、チャンネル・トランジスタによる充電電流とれチ
ャンネル・トランジスタによる放電電流がほぼ等しくな
ると、コンデンサC1と02の電圧はほぼnT2から成
るAMP’lの入出力特性の動作点は、第3図示のよう
に、一点鎖線との交点近傍に存在し、極めて大きな利得
を有する。従って多少の時間遅れを伴なう時刻t・6に
おいて正帰還接続の効果が顕著になυ、コンデンサC1
の充電電圧すなわち出力電圧ro!はバイアス電圧FB
Iに急激に近づき、−ヵ3.ア7td□2゜、□うわあ
、ヵ□VOIはバイアス電圧FB2に急激に近づく。こ
のようにしてディジタぶ回路への入力信号が出力される
。As a result, capacitor C1 is charged via p-channel transistor pT2 and at the same time the n-channel transistor
It is discharged through transistor nT2. Similarly, capacitor C2 is simultaneously charged via transistor pT1 and discharged via transistor nT1. However, the current of these MOS) transistors is
Since it is approximately proportional to the square of the source-to-source voltage, immediately after the n-channel transistors nT1 and nT'l conduct, the charging current is larger than the discharging current of the capacitor, and therefore the voltages of the capacitors C1 and 02 are both It continues to rise, but the rate of rise gradually slows down. At time 1s, when p, the charging current by the channel transistor and the discharging current by the channel transistor become almost equal, the voltages of capacitors C1 and 02 are approximately nT2.The operating point of the input/output characteristic of AMP'l is as shown in the third diagram. , it exists near the intersection with the dashed line and has an extremely large gain. Therefore, at time t・6 with some time delay, the effect of positive feedback connection becomes noticeable υ, capacitor C1
The charging voltage, that is, the output voltage ro! is the bias voltage FB
Rapidly approaching I, -ka3. A7td□2°, □Wow, Ka□VOI rapidly approaches the bias voltage FB2. In this way, the input signal to the digital input circuit is output.
上述の従来例においては、第6図示のように、2つの反
転増幅器AMP 1とAMP 2の特性が不揃いで両者
間にオフセット電圧V Offが存在する場合には、こ
のVOffを増幅することにエリ出力が決定されてしま
う。通常このVOff は数十tnV程度であり、これ
以下の入力電圧感度を得ることができないという問題が
ある。In the conventional example described above, when the characteristics of the two inverting amplifiers AMP 1 and AMP 2 are uneven and an offset voltage V Off exists between them, as shown in FIG. 6, there is an error in amplifying this V Off. The output will be determined. Normally, this Voff is on the order of several tens of tnV, and there is a problem that input voltage sensitivity below this cannot be obtained.
第2に、時刻ts以後のコンデンサ充電期間に、両コン
デンサに容量値にばらつきがあると入力電圧の大小関係
が正しく保持されず誤出力の原因となシ、これを防止す
る必要上感度が低下するという問題もある。Second, during the capacitor charging period after time ts, if there are variations in the capacitance values of both capacitors, the magnitude relationship between the input voltages will not be maintained correctly and this will cause erroneous output, and in order to prevent this, the sensitivity will decrease. There is also the problem of doing so.
第6に、時刻t3から時刻t6に至る応答時間が長く、
高速動作が困難であるという問題もある。Sixth, the response time from time t3 to time t6 is long;
Another problem is that high-speed operation is difficult.
発明の目的
本発明は上述した従来の問題点に鑑みてなされたもので
あり−1その目的は、素子特性のばらつきにより入力感
度が低下せず、・しかも高速動作が可能なフリップ・フ
ロップ形の電圧比較器を提供することにある。OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems.1 The purpose of the present invention is to develop a flip-flop type that does not reduce input sensitivity due to variations in element characteristics, and is capable of high-speed operation. The purpose of the present invention is to provide a voltage comparator.
発明の実施例
第4図は本発明の一実施例の回路図であシ、第5図はそ
の動作を説明するための波形図である。Embodiment of the Invention FIG. 4 is a circuit diagram of an embodiment of the present invention, and FIG. 5 is a waveform diagram for explaining its operation.
第4図において、第1図と同一の参照符号を付した要素
は、第1図に関し既に説明した要素と同一の要素である
。゛まずスイッチS4と55を閉じ、かつスイッチS6
を入力端子I2側に倒しておき、時刻t1 でスイッ
チS6を閉□じる。時刻t1において、上記4個のスイ
ッチをすべて同時に切替えても結果は同じである。ノー
ドN1の電圧FH1が直線的に増大して、時刻t!にお
いてこれと出力Jυ
コンデンサC3と04への充電が開始される。一方nチ
ャ≠ネル・トランジスタnT1とnT2には同一の値の
ゲート・ソース間電圧が印加されており、それぞれコン
デンサC6と04の放電路を形成する。In FIG. 4, elements with the same reference numerals as in FIG. 1 are the same elements as already described with respect to FIG. ``First, close switches S4 and 55, and close switch S6.
is moved to the input terminal I2 side, and the switch S6 is closed at time t1. At time t1, the result is the same even if all four switches are switched simultaneously. The voltage FH1 at the node N1 increases linearly until time t! At this point, charging of the output Jυ capacitors C3 and 04 is started. On the other hand, the same gate-source voltage is applied to n-channel transistors nT1 and nT2, which form discharge paths for capacitors C6 and 04, respectively.
この放電電流よりも充電電流が1廻るようにnチャかネ
ル・トランジスタのゲート・ソース間電圧を設定してお
くことによシ、コンデンサC3とC4の電圧すなわち出
力電圧Votと−2が上昇し始める。両者の電圧上昇速
度には、第5図示のように、両コンデンサの容量値のば
らつき、あるいはトランジスタの特性のばらつきに基づ
く差異が許容される。By setting the gate-source voltage of the n-channel transistor so that the charging current is one cycle higher than the discharging current, the voltages of capacitors C3 and C4, that is, the output voltages Vot and -2 increase. start. As shown in FIG. 5, differences in the rate of voltage rise between the two capacitors are allowed due to variations in the capacitance values of the two capacitors or variations in the characteristics of the transistors.
時刻t3において、コンデンサの充放電電流がほぼ均衡
し、出力電圧FOIとFORは一定値となる。At time t3, the charging and discharging currents of the capacitor are almost balanced, and the output voltages FOI and FOR become constant values.
このとき、トランジスタpT1とnT1から成る反転増
幅器AMP1 と、トランジスタpT2とnT2から
成る反転増幅器AMP2の動作点電圧は、それぞれ第3
図示の一点鎖線との交点に存在し、J’oi とVO2
の間には両増幅器のオフセット電圧VOffに相当する
電圧差が存在する。この電圧差はコンデンサ(?3とC
4に保持される。このときの出力電圧VO1とFOIの
大小関係は、従来例の場合と異なり、入1:′。At this time, the operating point voltages of the inverting amplifier AMP1 consisting of transistors pT1 and nT1 and the inverting amplifier AMP2 consisting of transistors pT2 and nT2 are respectively
It exists at the intersection with the dashed line shown in the figure, and J'oi and VO2
There is a voltage difference between them that corresponds to the offset voltage Voff of both amplifiers. This voltage difference is the capacitor (?3 and C
4. The magnitude relationship between the output voltage VO1 and FOI at this time is different from that of the conventional example, and is input 1:'.
力電圧の大小関係とは全く独立に両増幅器の特性のばら
つきのみに応じてm””’lqされる。m""'lq is determined depending only on the variation in the characteristics of both amplifiers, completely independent of the magnitude relationship of the input voltage.
上述のように動作点電圧が設定された後、時刻t4にお
いてスイッチS4と55を開放し、スイッチS6を入力
端子11側に切替える。この結果反転増幅器AMP 1
とAMP 2はコンデンサC3とC4を介して正帰
還接続され、同時にnチャネル・トランジスタnT1を
流れる電流が変化する。入力端子11上の信号電圧VX
が入力端子I2上の基準電圧VRよシも高いものとすれ
ば、nチャネル・トランジスタnT1を流れる放電電流
値が増加し、出力端子01上の出力電圧FOIが瞬間的
に低下する。After the operating point voltage is set as described above, the switches S4 and 55 are opened at time t4, and the switch S6 is switched to the input terminal 11 side. As a result, the inverting amplifier AMP1
and AMP2 are connected in positive feedback via capacitors C3 and C4, and at the same time the current flowing through the n-channel transistor nT1 changes. Signal voltage VX on input terminal 11
If the reference voltage VR on the input terminal I2 is higher than the reference voltage VR on the input terminal I2, the value of the discharge current flowing through the n-channel transistor nT1 increases, and the output voltage FOI on the output terminal 01 drops instantaneously.
この1つの安定状態からの変化は正帰還状態のもとで生
ずるので、他の安定状態に向かって加速的 −に変化
し、rolは急激にFB2に近づくと共にFOIは急激
にFB2に近づく。この結果出力端子01と02間にデ
ィジタル出力が発生する。Since this change from one stable state occurs under positive feedback conditions, it changes at an accelerating rate towards the other stable state, with rol rapidly approaching FB2 and FOI rapidly approaching FB2. As a result, a digital output is generated between output terminals 01 and 02.
このように、動作点電圧からの変化の方向すなわち出力
パルスの極性が信号電圧と基準電圧の差のみに基いて宏
まシ、オフセット電圧VOff は回路の動作に何科影
響を及ぼさないので、従来例に比べて入力感肇徴;大幅
に向上する。また回路の動”j
作速度は時刻t4から1sまでの時間で定まるから、従
来例に比べて動作速度が大幅に向上する。特に、周期的
なサンプリングを行なう場合には、時刻t!からta
tでのプレチャージの時間を予め確保できるという点で
本発明の応用に適している。またコンデンサC3とC4
の容量値が多少不揃いであっても、プレチャージに要す
る時間が多少ばらつくだけであり、基本的な動作特性は
何ら損なわれない。In this way, the direction of change from the operating point voltage, that is, the polarity of the output pulse, is determined based only on the difference between the signal voltage and the reference voltage, and the offset voltage Voff does not have any effect on the operation of the circuit. Compared to the example, input sensitivity is significantly improved. In addition, since the operating speed of the circuit is determined by the time from time t4 to 1 s, the operating speed is greatly improved compared to the conventional example.Especially when performing periodic sampling, the operating speed from time t!
This is suitable for application of the present invention in that the time for precharging at t can be secured in advance. Also capacitors C3 and C4
Even if the capacitance values are slightly uneven, the time required for precharging will vary slightly, and the basic operating characteristics will not be impaired in any way.
第6図は第4図示の回路を一般的なブロック図の形式で
示したものである。FIG. 6 shows the circuit shown in FIG. 4 in general block diagram form.
第7図は本発明の他の実施例のブロック図であり、動作
電圧の設定後スイッチS7を切替えて、予めコンデンサ
C5に充電しておいた信号電圧と基準電圧の差電圧を反
転増幅器AMP 1の非反転入力端子に印加するもので
ある。FIG. 7 is a block diagram of another embodiment of the present invention, in which the switch S7 is switched after setting the operating voltage, and the difference voltage between the signal voltage and the reference voltage, which has been charged in the capacitor C5, is transferred to the inverting amplifier AMP1. It is applied to the non-inverting input terminal of .
第8図は本発明の更に他の実施例のブロック図であり、
動作電圧の設定後スイッチS8と59を切替えて、予め
コンデンサC6に充電しておいた信号電圧と基準電圧の
差電圧を正帰還ループ中の適宜の箇所に挿入するもので
ある。この実施例では各増幅器の非反転入力端子は不要
であシ、各増幅器は差動、増幅器ではなくインバータに
よって構成される。FIG. 8 is a block diagram of still another embodiment of the present invention,
After setting the operating voltage, the switches S8 and 59 are switched to insert the voltage difference between the signal voltage and the reference voltage, which have been charged in the capacitor C6, into an appropriate position in the positive feedback loop. In this embodiment, there is no need for a non-inverting input terminal of each amplifier, and each amplifier is constructed by an inverter rather than a differential amplifier.
発明の効果
以上詳細に説明したように、本発明は2個の電端子間又
は正帰還ループ内に比較電圧を印加する構成であるから
、従来に比べて入力感度と動作速度が大幅に向上し、ま
たコンデンサの容量等回路定数がばらついても動作特性
に影響を及ぼさないという利点がある。Effects of the Invention As explained in detail above, since the present invention has a configuration in which a comparison voltage is applied between two electric terminals or within a positive feedback loop, the input sensitivity and operating speed are significantly improved compared to the conventional method. Another advantage is that even if circuit constants such as capacitance of capacitors vary, the operating characteristics are not affected.
第1図は従来例の構成を例示する回路図、第2図、第3
図は第1図の動作を説明するための概念図、第4図は本
発明の一実施例の構成を示す回路図、第5図は第4図の
動作を説明するだめの概念図、第6図は第4図の回路を
一般的に図示する構成ブロック図、第7図は本発明の他
の実施例の構成ブロック図、第8図は本発明め更に他の
実施例の構成ブロック図である。
AMPl、 AMP2・・・第11年2の反転増幅器、
pTl。
pT2・・・pチャネル・トランジスタ、nT1.nT
2・・・nチャネル・トランジスタ、C1乃至C4・・
・コンデンサ、Sl乃至B9・・・スイッチ、11.I
2・・・入力電圧端子、01,02・・・出力電圧端子
、B1.B2・・・バイアス電圧端子
特許出願人日本電信電話公社
代理人弁理士 玉 蟲 久 五 部(外6名)第1図
第・2 図
第3図
IN
第4図
第5図
M6図
第7図Figure 1 is a circuit diagram illustrating the configuration of a conventional example, Figures 2 and 3.
1 is a conceptual diagram for explaining the operation of FIG. 1, FIG. 4 is a circuit diagram showing the configuration of an embodiment of the present invention, FIG. 5 is a conceptual diagram for explaining the operation of FIG. 6 is a block diagram generally illustrating the circuit of FIG. 4, FIG. 7 is a block diagram of another embodiment of the present invention, and FIG. 8 is a block diagram of still another embodiment of the present invention. It is. AMPl, AMP2... 11th year 2 inverting amplifier,
pTl. pT2...p channel transistor, nT1. nT
2...n-channel transistors, C1 to C4...
・Capacitor, Sl to B9...Switch, 11. I
2...Input voltage terminal, 01,02...Output voltage terminal, B1. B2... Bias voltage terminal patent applicant Nippon Telegraph and Telephone Public Corporation Patent attorney Hisashi Tamamushi Department (6 others) Figure 1 Figure 2 Figure 3 IN Figure 4 Figure 5 M6 Figure 7
Claims (1)
続された第1.第2の反転増幅器、該第1、第2の反転
増幅器の出力端子と各々の反転入力端子とをほぼ短絡し
た状態で動作点電圧を設定−するスイッチ回路、及び該
動作点電圧の設定後前を供給するスイッチ回路を備えた
ことを特徴とする電圧比較器。The first and second channels are connected in positive feedback to each other through capacitors with approximately equal capacitance values. a second inverting amplifier, a switch circuit that sets an operating point voltage with the output terminals of the first and second inverting amplifiers and each inverting input terminal substantially short-circuited, and a switch circuit that sets the operating point voltage after setting the operating point voltage. A voltage comparator characterized by being equipped with a switch circuit that supplies.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10112682A JPS58218222A (en) | 1982-06-12 | 1982-06-12 | Voltage comparator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10112682A JPS58218222A (en) | 1982-06-12 | 1982-06-12 | Voltage comparator |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58218222A true JPS58218222A (en) | 1983-12-19 |
Family
ID=14292378
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10112682A Pending JPS58218222A (en) | 1982-06-12 | 1982-06-12 | Voltage comparator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58218222A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63117513A (en) * | 1986-11-05 | 1988-05-21 | Seiko Epson Corp | Level conversion circuit |
JPH02142214A (en) * | 1988-11-24 | 1990-05-31 | Nippon Motoroola Kk | Latching comparator to compensate offset voltage |
JP2010200302A (en) * | 2009-02-26 | 2010-09-09 | Advantest Corp | Comparator with latching function and testing device employing the same |
-
1982
- 1982-06-12 JP JP10112682A patent/JPS58218222A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63117513A (en) * | 1986-11-05 | 1988-05-21 | Seiko Epson Corp | Level conversion circuit |
JPH02142214A (en) * | 1988-11-24 | 1990-05-31 | Nippon Motoroola Kk | Latching comparator to compensate offset voltage |
JP2010200302A (en) * | 2009-02-26 | 2010-09-09 | Advantest Corp | Comparator with latching function and testing device employing the same |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US3984703A (en) | CMOS Schmitt trigger | |
US3543169A (en) | High speed clamping apparatus employing feedback from sample and hold circuit | |
US5332931A (en) | High speed differential comparator | |
US4581545A (en) | Schmitt trigger circuit | |
JP2804764B2 (en) | Amplifier device switchable between operating modes | |
JPH0223094B2 (en) | ||
US6046612A (en) | Self-resetting comparator circuit and method | |
US4320347A (en) | Switched capacitor comparator | |
US4523107A (en) | Switched capacitor comparator | |
US5017805A (en) | Offset cancel latching comparator | |
JP2857949B2 (en) | Offset voltage compensation circuit for differential amplifier | |
US5287070A (en) | Balanced voltage comparator | |
JPH07135452A (en) | Current comparator | |
JPS58218222A (en) | Voltage comparator | |
US4594560A (en) | Precision setting of the bias point of an amplifying means | |
JP2824260B2 (en) | Sequential operation differential current amplifier | |
US20210297077A1 (en) | Sampling Circuit and Sampling Method | |
JPS6251008B2 (en) | ||
KR0161321B1 (en) | Current clamping circuit | |
JPS59138121A (en) | Device for matching field effect transistor switch | |
CN111740707B (en) | Integrating amplifier circuit | |
JPS6152012A (en) | Differential amplifier circuit | |
JPS5840919A (en) | Voltage comparator | |
JPS61192116A (en) | Hysteresis circuit | |
US4123721A (en) | Bias current compensated operational amplifier circuit |