JPS61191046A - Method of isolating mos semiconductor integrated circuit - Google Patents

Method of isolating mos semiconductor integrated circuit

Info

Publication number
JPS61191046A
JPS61191046A JP3182885A JP3182885A JPS61191046A JP S61191046 A JPS61191046 A JP S61191046A JP 3182885 A JP3182885 A JP 3182885A JP 3182885 A JP3182885 A JP 3182885A JP S61191046 A JPS61191046 A JP S61191046A
Authority
JP
Japan
Prior art keywords
oxide film
region
layer
oxidation
mask layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3182885A
Other languages
Japanese (ja)
Inventor
Hiroyuki Oyabu
大薮　宏之
Koji Azuma
浩二 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP3182885A priority Critical patent/JPS61191046A/en
Publication of JPS61191046A publication Critical patent/JPS61191046A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To suppress the intrusion of a channel stopper region into an active region, by selectively making a CVD oxide film to remain at the peripheral part of an oxidation resisting mask layer. CONSTITUTION:On a semiconductor substrate 1, a silicon oxide film 3 and an oxidation resisting mask layer 2 are formed. The layer 2 is etched, and a part, which is to become an isolating region 5, is exposed. The substrate 1 is etched, and the entire region 5 is recessed. Then, a CVD film 6 is deposited on the entire surface of the layer 2 and the region 5. Thereafter, reactive ion etching of the film 6 is performed, and only the part neighboring the layer 2 is made to remain. With the layer 2 and the film 6 as masks, ions are implanted, and an ion implanted layer 7 is formed in a range narrower than the region 5. The surface of the substrate 1 is oxidized by using the layer 2, and a thick field oxide film 8 is formed in the region 5. A channel stopper region 9 is formed beneath the film 8 at the same time.

Description

【発明の詳細な説明】 （イ）産業上の利用分野 本発明はＭＯＳ半導体集積回路の分離方法、特に厚いフ
ィールド酸化膜を有し且つその直下にフィールド酸化膜
より狭いチャンネルストッパ領域を有するＭＯＳ半導体
集積回路の分離方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a method for separating MOS semiconductor integrated circuits, and particularly to a MOS semiconductor having a thick field oxide film and a channel stopper region narrower than the field oxide film immediately below the field oxide film. This invention relates to a method for separating integrated circuits.

（ロ）従来の技術 ＭＯＳ半導体集積回路では、半導体基板に形成されるＭ
ＯＳトランジスタ間の分離をするため、選択酸化法ＣＬ
ＯＣＯ３法）により形成した厚いフィールド酸化膜を設
け、このフィールド酸化膜下にチャンネルストッパ領域
を形成し、基板反転電圧を高める方法が採用されていた
（例えば特公昭４９−１７０６９号公報参照）。(b) Conventional technology In MOS semiconductor integrated circuits, M
Selective oxidation method CL is used to isolate OS transistors.
A method has been adopted in which a thick field oxide film is formed by the OCO3 method) and a channel stopper region is formed under the field oxide film to increase the substrate reversal voltage (for example, see Japanese Patent Publication No. 17069/1983).

しかしながら斯上したＬＯＣＯ８法による分離方法では
、フィールド酸化膜およびチャンネルストッパ領域の形
成がセルファラインにより行なわれるので、チャンネル
ストッパ領域はフィールド酸化膜下全面に形成され、Ｍ
ＯＳ）ランジスタを形成する能動領域までくい込んでし
ま５゜第２図は従来のＭＯＳ半導体集積回路の分離方法
による断面構造を示し、図中αＤはＰ型シリコン基板、
（１２１はゲート酸化膜、α３は多結晶シリコンゲート
電極、α机まＭＯＳトランジスタのドレイン領域となる
Ｎ　型領域、　ＣＩＳはソース領域となるＮ＋型領領域
（１６１は選択酸化法で形成したフィールド酸化膜、α
ＤはＰ　型のチャンネルストッパ領域である。However, in the isolation method using the LOCO8 method described above, since the field oxide film and the channel stopper region are formed by self-aligning, the channel stopper region is formed on the entire surface under the field oxide film, and the M
Figure 2 shows the cross-sectional structure of a conventional MOS semiconductor integrated circuit separation method, and αD in the figure is a P-type silicon substrate;
(121 is a gate oxide film, α3 is a polycrystalline silicon gate electrode, α3 is an N-type region that will become the drain region of the MOS transistor, CIS is an N+-type region that will be the source region (161 is a field oxidation film formed by selective oxidation method) membrane, α
D is a P type channel stopper region.

（ハ）発明が解決しようとする問題点 斯るＭＯＳ半導体集積回路では第２図に示すように、チ
ャンネルストッパ領域αηのくい込みによってドレイン
領域α４ならびにソース領域α９の一部分とチャンネル
ストッパ領域αηとの間に重畳部分ｕ８が形成され、こ
の部分にはＰＮ　　接合が存在するところとなり、寄生
接合容量が増加する欠点があった。またフィールド酸化
膜αｅの周辺部分にはバーズビークと呼ばれる突起が生
じ、後でのホトレジスト工程や電極形成工程での障害と
なる欠点もあった。(c) Problems to be Solved by the Invention In such a MOS semiconductor integrated circuit, as shown in FIG. An overlapping portion u8 is formed in this portion, and a PN junction exists in this portion, which has the drawback of increasing parasitic junction capacitance. In addition, a protrusion called a bird's beak occurs in the peripheral portion of the field oxide film αe, which has the disadvantage of becoming an obstacle in the subsequent photoresist process and electrode forming process.

に）問題点を解決するための手段 本発明は断点に鑑みてなされ、分離領域全体をくぼませ
る工程とＣＶＤ酸化膜（６）の反応性イオンエツチング
する工程により、チャンネルストッパ領域（９）の能動
領域ααへのくい込みをなくし且つバーズビークの発生
も抑えたＭＯＳ半導体集積回路の分離方法を提供するも
のである。B) Means for Solving the Problems The present invention was made in view of the problem, and the channel stopper region (9) is improved by recessing the entire isolation region and reactive ion etching of the CVD oxide film (6). The present invention provides a method for separating MOS semiconductor integrated circuits that eliminates encroachment into the active region αα and also suppresses the occurrence of bird's beaks.

（ホ）作用 本発明に依れば、ＣＶＤ酸化膜（６）を耐酸化マスク層
（２）の周縁部に選択的に残すことにより、チャンネル
ストッパ領域（９）となるイオン注入層（７）がフィー
ルド酸化膜（８）より狭くイオン注入できチャンネルス
トッパ領域（９）の能動領域へのくい込みを抑えること
ができ、また選択酸化時にはＣＶＤ酸化膜（６）の端面
より酸化されるのでバーズビークの発生を抑えることが
できる。(E) Function According to the present invention, by selectively leaving the CVD oxide film (6) on the periphery of the oxidation-resistant mask layer (2), the ion-implanted layer (7) becomes the channel stopper region (9). ion implantation is narrower than that of the field oxide film (8), it is possible to prevent the channel stopper region (9) from penetrating into the active region, and during selective oxidation, the end face of the CVD oxide film (6) is oxidized, resulting in bird's beaks. can be suppressed.

（へ）実施例 本発明に依るＭＯ３半導体集積回路の分離方法を第１図
げ）乃至（へ）を参照して詳述する。(f) Embodiment A method for separating MO3 semiconductor integrated circuits according to the present invention will be described in detail with reference to FIGS.

本発明の第１の工程は第１図げ）に示す如＜、一導電型
の半導体基板＋１１上に耐酸化マスク層（２）を形成す
ることにある。本工程ではＰ型のシリコン基板（１）の
表面を熱酸化して、厚さ約１００　ＯＡの酸化シリコン
膜（３）を形成した後、周知のＣＶＤ法により耐酸化マ
スク層（２）として働く窒化シリコン膜を約３００ＯＡ
の厚さに形成する。The first step of the present invention is to form an oxidation-resistant mask layer (2) on a semiconductor substrate +11 of one conductivity type, as shown in Fig. 1). In this step, the surface of a P-type silicon substrate (1) is thermally oxidized to form a silicon oxide film (3) with a thickness of approximately 100 OA, which then acts as an oxidation-resistant mask layer (2) using the well-known CVD method. Silicon nitride film approximately 300OA
Form to a thickness of .

本発明の第２の工程は第１図（ロ）に示す如く、耐酸化
マスク層（２）上に所望のパターンのホトレジスト層（
４）を付着し、耐酸化マスク層（２Ｊをエツチングして
分離領域（５）となる部分を露出し、更に半導体基板（
１）をエツチングして分離領域＋５１全体をくぼませる
ことにある。本工程ではホトレジスト層（４）を耐酸化
マスク層（２）全面に塗布した後所望のパターンに露光
感光した後、所望のパターンのホトレジスト層（４）を
残存させる。続いてホトレジスト層（４）をマスクとし
て窒化シリコン膜（２）を熱リン酸でエツチングしてホ
トレジスト層（４）と同形状の窒化シリコン膜（２）を
残す。更に続いて混酸により酸化シリコン膜（３）およ
び半導体基板（ＩＩをエツチングして。The second step of the present invention is to form a photoresist layer (with a desired pattern) on the oxidation-resistant mask layer (2), as shown in FIG.
4) is deposited, the oxidation-resistant mask layer (2J) is etched to expose the part that will become the isolation region (5), and the semiconductor substrate (2J) is etched to expose the part that will become the isolation region (5).
1) to make the entire separation region +51 concave by etching. In this step, a photoresist layer (4) is coated on the entire surface of the oxidation-resistant mask layer (2) and then exposed to light in a desired pattern, and then the photoresist layer (4) in the desired pattern is left. Subsequently, using the photoresist layer (4) as a mask, the silicon nitride film (2) is etched with hot phosphoric acid to leave the silicon nitride film (2) having the same shape as the photoresist layer (4). Furthermore, the silicon oxide film (3) and the semiconductor substrate (II) were etched using a mixed acid.

分離領域（５１全体の半導体基板（１）を約０．３μの
深さにくぼませている。The entire isolation region (51) of the semiconductor substrate (1) is recessed to a depth of about 0.3 μm.

本発明の第３の工程は第１図（ハ）に示す如く、耐酸化
マスク層（２）および分離領域（５）上全面にＣＶＤ酸
化膜（６）を付着することにある。本工程では周知のＣ
ＶＤ法によって全表面に約７０００〜１００００Ａの厚
みにＣＶＤ酸化膜（６）を積層する。The third step of the present invention is to deposit a CVD oxide film (6) on the entire surface of the oxidation-resistant mask layer (2) and isolation region (5), as shown in FIG. 1(C). In this process, the well-known C
A CVD oxide film (6) is laminated to a thickness of approximately 7,000 to 10,000 Å over the entire surface by the VD method.

本発明の第４の工程は第１図に）に示す如く、ＣＶＤ酸
化膜（６）を反応性イオンエツチングして分離領域（５
）上の耐酸化マスク層＋２７に隣接する部分に残存させ
、分離領域（５）の中央部分は半導体基板＋１１を露出
させることにある。反応性イオンエツチングによりＣＶ
Ｄ酸化膜（６１を異方性エツチングすると。The fourth step of the present invention is to perform reactive ion etching on the CVD oxide film (6) as shown in FIG.
) is left in a portion adjacent to the oxidation-resistant mask layer +27 on top of the mask layer +27, and the central portion of the isolation region (5) is to expose the semiconductor substrate +11. CV by reactive ion etching
D oxide film (61) is anisotropically etched.

耐酸化マスク層（２）および分離領域（５）の中央部分
上のＣＶＤ酸化膜（６（は完全に除去されるが、分離領
域（５）周辺の耐酸化マスク層（２）に隣接する部分の
ＣＶＤ酸化膜（６）は垂直方向に厚いのでエツチングさ
れずに残存する。具体的には耐酸化マスク層（２）間の
分離領域（５１の巾を１．３μｍに設定し、ＣＶＤ酸化
膜（６）は耐酸化マスク層（２）から０．３〜０．５μ
ｍの巾で残存する。The CVD oxide film (6) on the oxidation-resistant mask layer (2) and the central part of the isolation region (5) is completely removed, but the portions adjacent to the oxidation-resistant mask layer (2) around the isolation region (5) are completely removed. Since the CVD oxide film (6) is thick in the vertical direction, it remains without being etched.Specifically, the width of the isolation region (51) between the oxidation-resistant mask layers (2) is set to 1.3 μm, and the CVD oxide film (6) is 0.3 to 0.5μ from the oxidation-resistant mask layer (2)
It remains with a width of m.

本発明の第５の工程は第１図（ホ）に示す如く、耐酸化
マスク層（２１および残存するＣＶＤ酸化膜（６）をマ
スクにイオン注入し、分離領域（５１より狭い範囲にイ
オン注入層（７）を形成することＫある。本工程では前
工程で残存させたＣＶＤ酸化ａｌｌ（６１もイオン注入
のマスクとして働くので、セルファライン効果によって
分離領域（５）の中央部分にＰ　型のイオン注入層（７
）を形成できる。なおイオン注入はボロンイオンを用い
、加速電圧３０ＫｅＶでドーズ量３×１０　個／ｄで行
い、耐酸化マスク層（２）であるシリコン窒化膜をマス
クとして働く範囲内を選定する。In the fifth step of the present invention, as shown in FIG. 1(e), ions are implanted using the oxidation-resistant mask layer (21 and the remaining CVD oxide film (6) as a mask, and the ions are implanted into an area narrower than the isolation region (51). A layer (7) is formed.In this step, the CVD oxidized all (61) left in the previous step also acts as a mask for ion implantation, so a P-type layer is formed in the center of the isolation region (5) by the self-line effect. Ion implantation layer (7
) can be formed. The ion implantation is performed using boron ions at an acceleration voltage of 30 KeV and a dose of 3×10 6 /d, and the range is selected so that the silicon nitride film serving as the oxidation-resistant mask layer (2) functions as a mask.

本発明の第６の工程は第１図（へ）に示す如（、耐酸化
マスク層（２；を用いて半導体基板（１）表面を選択酸
化して分離領域（５）に厚いフィールド酸化膜（ａｔを
形成し、フィールド酸化膜（８）下に同時にチャンネル
ストッパ領域（９）を形成すること忙ある。本工程では
耐酸化マスク層（２）および残存したＣＶＤ酸化膜（６
）を残したままで、周知の方法で選択酸化を行い、分離
領域（５）に埋め込み屋の厚いフィールド酸化膜（８）
を形成する。このときフィールド酸化膜（８）下にはイ
オン注入層（７）がドライブインされてチャンネルスト
ッパ領域（９）が形成される。このチャンネルストッパ
領域（９）はイオン注入層（７）を選択的に分離領域（
５１の中央部に形成しているので、能動領域（ＩＧへの
くい込みは完全忙防止できる。また選択酸化はＣＶＤ酸
化膜（６）の存在によりＣＶＤ酸化膜（６）の周端より
始まるので、耐酸化マスク層（２）下までくい込んでフ
ィールド酸化膜（８）は形成されない。The sixth step of the present invention is to selectively oxidize the surface of the semiconductor substrate (1) using an oxidation-resistant mask layer (2) as shown in FIG. At the same time, a channel stopper region (9) is formed under the field oxide film (8). In this step, the oxidation-resistant mask layer (2) and the remaining CVD oxide film (6) are formed.
), selective oxidation is performed using a well-known method to form a thick field oxide film (8) buried in the isolation region (5).
form. At this time, an ion implantation layer (7) is driven in under the field oxide film (8) to form a channel stopper region (9). This channel stopper region (9) selectively separates the ion-implanted layer (7) into a region (
Since it is formed in the center of the CVD oxide film (6), it is possible to completely prevent it from penetrating into the active region (IG).Also, selective oxidation starts from the peripheral edge of the CVD oxide film (6) due to the presence of the CVD oxide film (6). The field oxide film (8) is not formed by penetrating below the oxidation-resistant mask layer (2).

このため通常の選択酸化により生ずるバーズビークは発
生しないのである。耐酸化マスク層（２；の周辺に残存
するＣＶＤ酸化膜（６１は耐酸化マスク層（２）のエツ
チング除去時に同時に除去すると良い。For this reason, bird's beaks, which occur with normal selective oxidation, do not occur. The CVD oxide film (61) remaining around the oxidation-resistant mask layer (2) is preferably removed at the same time as the oxidation-resistant mask layer (2) is etched.

本発明の最終工程では能動領域ａ〔に所定のＭ０Ｓトラ
ンジスタを形成している。In the final step of the present invention, a predetermined MOS transistor is formed in the active region a.

（ト）発明の効果 本発明の分離方法では、チャンネルストッパ領域（９）
となるイオン注入層（７）の形成を耐酸化マスク層（２
）およびＣＶＤ酸化膜（６）を用いてセル７アラインに
より実現でき、しかもイオン注入層（７）を分離領域（
５）内にこれより狭い面積でセル７アラインにより形成
できる。このためチャンネルストッパ領域（９）をフィ
ールド酸化膜（８）下に容易忙形成でき、しかも能動領
域αＱへのチャンネルストッパ領域（９）のくい込みを
防止でき寄生接合容量の増加を有効に抑えられる。(g) Effects of the invention In the separation method of the invention, the channel stopper region (9)
The ion implantation layer (7) is formed using an oxidation-resistant mask layer (2).
) and CVD oxide film (6) can be realized by cell 7 alignment.
5) can be formed by cell 7 alignment in a smaller area than this. Therefore, the channel stopper region (9) can be easily formed under the field oxide film (8), and furthermore, the channel stopper region (9) can be prevented from digging into the active region αQ, and an increase in parasitic junction capacitance can be effectively suppressed.

また本発明の分離方法では、ＣＶＤ酸化膜（６）をイオ
ン注入のマスクの他に選択酸化のマスクとして共用する
ので１選択酸化はＣＶＤ酸化膜（６）の周端より始まり
、フィールド酸化膜（８）の耐酸化マスク層（２）下へ
のくい込みがなくバーズビークの発生を抑えることがで
きる。Furthermore, in the isolation method of the present invention, the CVD oxide film (6) is used not only as a mask for ion implantation but also as a mask for selective oxidation. There is no penetration under the oxidation-resistant mask layer (2) of 8), and the occurrence of bird's beaks can be suppressed.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（イ）乃至（へ）は不発明によるＭＯ５半導体集
積回路の分離方法を説明する断面図、第２図は従来の分
離方法を説明する断面図である。 主な図番の説明 （１）は半導体基板、（２）は耐酸化マスク層、（５Ｉ
は分離領域、（６１はＣＶＤ酸化膜、（８）はフィール
ド酸化膜、（９；はチャンネルストッパ領域である。FIGS. 1(A) to 1(F) are cross-sectional views for explaining a method of separating MO5 semiconductor integrated circuits according to the invention, and FIG. 2 is a cross-sectional view for explaining a conventional separating method. Explanation of the main figure numbers (1) is the semiconductor substrate, (2) is the oxidation-resistant mask layer, (5I
(61 is a CVD oxide film, (8) is a field oxide film, and (9) is a channel stopper region.

Claims (1)

【特許請求の範囲】[Claims] （１）一導電型の半導体基板上に耐酸化マスク層を形成
する工程、 該耐酸化マスク層上に所望のパターンのホトレジスト層
を付着して前記耐酸化マスク層をエッチングして分離領
域となる部分を露出し更に前記半導体基板をエッチング
して前記分離領域全体をくぼませる工程、 前記耐酸化マスク層および分離領域上にＣＶＤ酸化膜を
付着する工程、 該ＣＶＤ酸化膜全面を反応性イオンエッチングして分離
領域上の前記耐酸化マスク層に隣接する周辺部分に前記
ＣＶＤ酸化膜を残存させ、前記分離領域の中央部分を露
出する工程、 前記耐酸化マスク層と残存するＣＶＤ酸化膜をマスクと
してイオン注入し前記分離領域より狭い範囲にイオン注
入層を形成する工程、 前記耐酸化マスク層および残存するＣＶＤ酸化膜を用い
て前記半導体基板表面を選択的に酸化して前記分離領域
にフィールド酸化膜を形成し且つ該フィールド酸化膜下
にチャンネルストッパ領域を形成する工程とを具備する
ことを特徴とするＭＯＳ半導体集積回路の分離方法。(1) Forming an oxidation-resistant mask layer on a semiconductor substrate of one conductivity type, depositing a photoresist layer in a desired pattern on the oxidation-resistant mask layer, and etching the oxidation-resistant mask layer to form an isolation region. exposing a portion of the semiconductor substrate and further etching the semiconductor substrate to recess the entire isolation region; depositing a CVD oxide film on the oxidation-resistant mask layer and the isolation region; and performing reactive ion etching on the entire surface of the CVD oxide film. leaving the CVD oxide film in a peripheral portion adjacent to the oxidation-resistant mask layer on the isolation region and exposing a central portion of the isolation region; forming an ion implantation layer in a narrower area than the isolation region; selectively oxidizing the surface of the semiconductor substrate using the oxidation-resistant mask layer and the remaining CVD oxide film to form a field oxide film in the isolation region; and forming a channel stopper region under the field oxide film.
JP3182885A 1985-02-20 1985-02-20 Method of isolating mos semiconductor integrated circuit Pending JPS61191046A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3182885A JPS61191046A (en) 1985-02-20 1985-02-20 Method of isolating mos semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3182885A JPS61191046A (en) 1985-02-20 1985-02-20 Method of isolating mos semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS61191046A true JPS61191046A (en) 1986-08-25

Family

ID=12341933

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3182885A Pending JPS61191046A (en) 1985-02-20 1985-02-20 Method of isolating mos semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS61191046A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01179431A (en) * 1988-01-06 1989-07-17 Toshiba Corp Manufacture of semiconductor device
US4965221A (en) * 1989-03-15 1990-10-23 Micron Technology, Inc. Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS587839A (en) * 1981-07-07 1983-01-17 Toshiba Corp Manufacture of semiconductor device
JPS59165434A (en) * 1983-03-11 1984-09-18 Toshiba Corp Manufacture of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS587839A (en) * 1981-07-07 1983-01-17 Toshiba Corp Manufacture of semiconductor device
JPS59165434A (en) * 1983-03-11 1984-09-18 Toshiba Corp Manufacture of semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01179431A (en) * 1988-01-06 1989-07-17 Toshiba Corp Manufacture of semiconductor device
US4965221A (en) * 1989-03-15 1990-10-23 Micron Technology, Inc. Spacer isolation method for minimizing parasitic sidewall capacitance and creating fully recessed field oxide regions

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