JPS61189656A - Resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device

Info

Publication number
JPS61189656A
JPS61189656A JP60029313A JP2931385A JPS61189656A JP S61189656 A JPS61189656 A JP S61189656A JP 60029313 A JP60029313 A JP 60029313A JP 2931385 A JP2931385 A JP 2931385A JP S61189656 A JPS61189656 A JP S61189656A
Authority
JP
Japan
Prior art keywords
resin
lead frame
recess
sealed
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60029313A
Other languages
Japanese (ja)
Inventor
Masaaki Sato
正昭 佐藤
Fusaji Shoji
房次 庄子
Takeshi Komaru
小丸　健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60029313A priority Critical patent/JPS61189656A/en
Publication of JPS61189656A publication Critical patent/JPS61189656A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain the titled device excellent in moisture resistance and simple in production by a method wherein an inner package with a semiconductor element, bonding wires, and at least part of a lead frame sealed with resin is formed in the recess of a recess member partly made of ultraviolet-permeable material, and the whole package is then sealed with resin. CONSTITUTION:An element 1 is fixed on the island 3 of a lead frame with a mount member 2 made of an epoxy series paste. Next, the element 1 is bonded to the lead parts 5 of the lead frame with Au bonding wires 4. The lead frame finished in bonding is turned upside down and installed on a recess member 8 made of clear alumina and secured with an adhesive layer 12 made of an epoxy series adhesive. Then, a clear sealing resin 13, clear silicone resin, is cast in the recess and cured by heating, thus forming an inner package 14. Further, this package 14 is installed in a transfer mold metal die 15, and an epoxy resin is cast through a casting port 16 into the cavity and cured by heating, resulting in the formation of a resin-sealed body 11.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体装置にかかわり、特にＥＰＲＯＭ（Ｂｒ
ａｓａｂｌｅ　ａｎａ　Ｐｒｏｇｒａｍｍａｂｌｅ　Ｒ
ｅａｄ　０ｎｌｙ　Ｍｅｍｏｒｙ）等のようなパッケー
ジに窓を有する半導体装置の構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to semiconductor devices, particularly EPROM (Br
asable ana Programmable R
The present invention relates to the structure of a semiconductor device having a window in a package, such as a semiconductor device (ead only memory) or the like.

〔発明の背景〕[Background of the invention]

一般にＥＦＲＯＭ装置は、外部から紫外線照射を受ける
ことができるように、サファイア、透明アルミナまたは
石英ガラスなどの透光部材が取り付けられたセラミック
パッケージにより半導体装置が封止されている。ところ
が、この従来構造においては、封止材料が高価であり、
かつ遮光部材の貼付けや埋込みのために特別の工程が必
要であり、他の半導体装置で行われている樹脂モールド
に比べて高価となるという問題がある。このセラミック
パッケージの問題点を解決するため、例えば、特開昭５
８−４９５１号公報、特開昭５８−４９５２号公報でみ
られるように、プラスチックを用いて封止する装置がい
くつか知られている。その代表的な構造を第３図に示す
。図において、半導体素子１ａはマウント部材２を介し
てアイランド３に装着されている。また、半導体素子１
ａはボンディング線４を介してリード部５に接続されて
いる。リードフレ−ム６上には、アイランド３上の半導
体素子１ａおよびこれにボンディング線４で接続された
リード部５の先端部分を収容する中空部７を有するキ″
ヤソブ８ａが固着されている。キャップ８ａは、半導体
素子１ａに対向する上部の領域を露出しかつＩＪ−ドフ
レーム６の外部リード部の領域を露出するようにして、
絶縁基体ＩＯを含めて一体に形成された樹脂封止体１１
で封止されている。また、キャンプ８ａとリード部５と
の間、絶縁基体１０とリード部５との間は、エポキシ系
などの有機物の接着層１２テ固着されている。Generally, in an EFROM device, the semiconductor device is sealed in a ceramic package to which a light-transmitting member such as sapphire, transparent alumina, or quartz glass is attached so that it can receive ultraviolet irradiation from the outside. However, in this conventional structure, the sealing material is expensive;
Further, a special process is required for attaching and embedding the light shielding member, and there is a problem that it is more expensive than resin molding that is used for other semiconductor devices. In order to solve the problems of this ceramic package, for example,
As seen in Japanese Patent Laid-Open No. 8-4951 and Japanese Unexamined Patent Application Publication No. 58-4952, several sealing devices using plastic are known. A typical structure thereof is shown in FIG. In the figure, a semiconductor element 1a is mounted on an island 3 via a mounting member 2. In addition, the semiconductor element 1
a is connected to a lead portion 5 via a bonding wire 4. On the lead frame 6, there is a key having a hollow part 7 for accommodating the semiconductor element 1a on the island 3 and the tip part of the lead part 5 connected to the semiconductor element 1a by the bonding wire 4.
Yasob 8a is fixed. The cap 8a exposes the upper region facing the semiconductor element 1a and exposes the region of the external lead portion of the IJ-deframe 6.
Resin sealing body 11 integrally formed including insulating base IO
is sealed with. Moreover, between the camp 8a and the lead part 5, and between the insulating base 10 and the lead part 5, an adhesive layer 12 of an organic material such as epoxy is fixed.

しかしながら、このように構成された半導体装置では、
゛中空部７は有機の樹脂封止体１１と接着層１２とで外
部雰囲気を遮へいしているため、外部雰囲気中の水分は
、それら樹脂体や接着層を通して中空部７に到達してし
まう。そのため、外部雰囲気が高湿度の場合、中空部７
も高湿度となり、その中空部７に設置された半導体素子
１ａ、ボンディング線４、リード部５に水分が凝結する
ので、高湿度雰囲気での信頼性に問題があった・〔発明
の目的〕 本発明の目的は、上記した従来技術の問題点を解決し、
耐湿性に擾れ、かつ製造工程が簡略な半導体装置を提供
することにある。However, in a semiconductor device configured in this way,
``Since the hollow part 7 is shielded from the external atmosphere by the organic resin sealing body 11 and the adhesive layer 12, moisture in the external atmosphere reaches the hollow part 7 through the resin body and the adhesive layer. Therefore, if the external atmosphere is high humidity, the hollow part 7
The semiconductor element 1a installed in the hollow part 7, the bonding wire 4, and the lead part 5 are also subject to high humidity, and moisture condenses on the semiconductor element 1a, the bonding wire 4, and the lead part 5, resulting in a reliability problem in a high humidity atmosphere. The purpose of the invention is to solve the problems of the prior art described above,
It is an object of the present invention to provide a semiconductor device which has excellent moisture resistance and whose manufacturing process is simple.

〔発明の概要〕[Summary of the invention]

本発明の基本的な考えは、まず素子表面を第１の封止樹
脂でコートして内部パッケージを形成し次に、第２の封
止樹脂で全体を封止することである。The basic idea of the present invention is to first coat the element surface with a first sealing resin to form an internal package, and then seal the entire device with a second sealing resin.

上記の考えを具体的に実現するため、本発明では、少な
くとも一部が紫外線を透過する材料で凹状部材を形成し
、その凹部内に、リードフレームのアイランド上に受光
面を上にして装着された半導体素子とボンディング線を
介して接続されたリードフレームのリード部を設置し、
紫外線を透過する第１の封止樹脂によって上記凹部内の
半導体素子、ボンディング線およびリードフレームの少
なくとも一部を封止して内部パッケージを形成し次に、
第２の封止樹脂によって凹部の一部とリードフレームの
端部を外部に露出している上記内部パッケージを封止す
る。In order to concretely realize the above idea, in the present invention, a concave member is formed, at least a part of which is made of a material that transmits ultraviolet rays, and a concave member is mounted in the concave portion on the island of the lead frame with the light-receiving surface facing upward. The lead part of the lead frame is connected to the semiconductor element through the bonding wire.
sealing at least a portion of the semiconductor element, bonding wire, and lead frame in the recess with a first sealing resin that transmits ultraviolet rays to form an internal package;
The internal package, in which a part of the recess and the end of the lead frame are exposed to the outside, is sealed with a second sealing resin.

凹状部材には、アルミナ、サファイア、石英ガラス等の
無機材料およびポリプロピレン系樹脂、ポリエステル系
樹脂、シリコーン系樹脂などの有機材料が用いられる。For the concave member, inorganic materials such as alumina, sapphire, and quartz glass, and organic materials such as polypropylene resin, polyester resin, and silicone resin are used.

また、紫外線が照射される部分だけを上記紫外線透過材
料で形成してもよい半導体素子が接続されたリードフレ
ームの凹部への設置は、エポキシ系接着剤などで固着す
るか、治具なとで固定して行い、第１の封止樹脂で一体
化する。In addition, only the part that is irradiated with ultraviolet rays may be made of the above-mentioned ultraviolet transmitting material.Installation in the recessed part of the lead frame to which the semiconductor element is connected may be done by fixing it with an epoxy adhesive or by using a jig. It is fixed and integrated with the first sealing resin.

第１の封止樹脂としては、紫外線を通過させ、°　接着
性がよく、不純物の少ないものが用いられる。As the first sealing resin, one that allows ultraviolet rays to pass through, has good adhesive properties, and contains few impurities is used.

具体的には、無機充填剤を含まな℃・シリコーン系廚脂
、エポキシ系樹脂などが用いられ、特にフヱニル基含有
が少な（・２液温合型シリコーン樹脂が好ましく、２液
温合後、凹部内に注入して、加熱硬化する。また、第２
の封止樹脂としては、無機充填剤を含むエポキシ系樹脂
、ポリフェニレンサルファイド系樹脂などが用いられる
。Specifically, silicone resins, epoxy resins, etc. that do not contain inorganic fillers are used, and in particular, they contain little phenyl groups (two-component heating type silicone resins are preferred; after the two-component heating, Inject into the recess and heat cure.Also, the second
As the sealing resin, epoxy resin containing an inorganic filler, polyphenylene sulfide resin, etc. are used.

〔発明の実施例〕[Embodiments of the invention]

以下、図面を参照しながら本発明の実施例を詳説する。 Embodiments of the present invention will be described in detail below with reference to the drawings.

第１図は、半導体素子がＥＰＲＯＭ素子である半導体装
置に本発明を実施した一実施例の製造工程を示したもの
である。まず、ＥＰＲＯＭ素子１をエポキシ系ペースト
からなるマウント部材２でリードフレームのアイランド
３上に固着する（同図ａ）。FIG. 1 shows the manufacturing process of an embodiment in which the present invention is applied to a semiconductor device whose semiconductor element is an EPROM element. First, an EPROM element 1 is fixed onto an island 3 of a lead frame using a mounting member 2 made of epoxy paste (FIG. 1A).

次に、金線によるボンディングｆｓ４を用いてＥＰＲＯ
Ｍ素子１とリードフレームのリード部５とをワイヤボン
ディングする（同図ｂ）。ボンディングしたリードフレ
ームを裏返して、これを透明アルミナからなる凹状部材
８の上に設置し、エポキシ系接着剤からなる接着層１２
で固着する（同図Ｃ）。Next, use EPRO bonding fs4 with gold wire.
Wire bonding is performed between the M element 1 and the lead portion 5 of the lead frame (FIG. 3(b)). The bonded lead frame is turned over and placed on a concave member 8 made of transparent alumina, and an adhesive layer 12 made of epoxy adhesive is placed on top of the concave member 8 made of transparent alumina.
(Figure C).

次に、凹部の内部に透明シリコーン樹脂である透明封止
樹脂１３を注入し、加熱硬化して、内部パッケージ１４
を形成する（同図ｄ）。さらに、内部パッケージ１４を
トランスファ・モールド金型１５内に設置し、注入口１
６からキャビティにエポキシ樹脂を注入し加熱硬化して
、樹脂封止体１１を形成する（同図ｅ）。最後に、金型
１５から中身を取り出し、リードフレームを切断し曲げ
て、半導体装置が形成される（同図ｆ）。Next, a transparent sealing resin 13, which is a transparent silicone resin, is injected into the recessed part and cured by heating.
(d). Further, the inner package 14 is placed in the transfer mold die 15, and the injection port 1 is placed inside the transfer mold die 15.
Epoxy resin is injected into the cavity from step 6 and cured by heating to form a resin sealing body 11 (see e in the same figure). Finally, the contents are taken out from the mold 15, and the lead frame is cut and bent to form a semiconductor device (f in the same figure).

第２図に、本発明による半導体装置の他の実施例を示す
。本実施例では、凹状部材は、透明アルミナからなる光
透過板１７と、不透明アルミナからなる中枠１８とで構
成されている。ＥＰＲＯＭ素子１、ボンディング線４、
リードフレームのアイランド３とリード部５は、透明シ
リコーン樹脂である透明制止樹脂１３によって封止され
ている。なお、本実施例の製造工程は、第１図とほぼ同
じである。FIG. 2 shows another embodiment of the semiconductor device according to the present invention. In this embodiment, the concave member is composed of a light transmitting plate 17 made of transparent alumina and an inner frame 18 made of opaque alumina. EPROM element 1, bonding line 4,
The island 3 and lead portion 5 of the lead frame are sealed with a transparent sealing resin 13 that is a transparent silicone resin. Note that the manufacturing process of this example is almost the same as that shown in FIG.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、耐湿性が向上し、かつ簡略化した製造
工程により低価格化された樹脂封止型半導体装置を得る
ことができる。According to the present invention, it is possible to obtain a resin-sealed semiconductor device with improved moisture resistance and a reduced price through a simplified manufacturing process.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例であるプラスチックパッケー
ジに収容されたＥＦＲＯＭ装置の製造工程図、第２図は
本発明の他の実施例であるＥＦＲＯＭ装置の断面図、第
３図は従来のプラスチックに収容された半導体装置の断
面図である。 符号の説明 １・・・ＥＰＲＯＭ素子　　　　　２・・・マウント部
材３・−・アイランド　　　　　４・・・ボンディング
線５・・・リード部　　　　　　８・・・凹状部材１２
・・・接着層　　　　　　　１３・・・透明封止樹脂１
４・・・内部パッケージ　　　１７・・〜光透過板１８
・・・中枠Fig. 1 is a manufacturing process diagram of an EFROM device housed in a plastic package which is an embodiment of the present invention, Fig. 2 is a cross-sectional view of an EFROM device which is another embodiment of the invention, and Fig. 3 is a diagram of a conventional FIG. 2 is a cross-sectional view of a semiconductor device housed in plastic. Explanation of symbols 1...EPROM element 2...Mount member 3...Island 4...Bonding wire 5...Lead portion 8...Concave member 12
... Adhesive layer 13 ... Transparent sealing resin 1
4... Internal package 17... ~ Light transmission plate 18
・・・Middle frame

Claims (1)

【特許請求の範囲】[Claims] 少なくとも一部が紫外線を透過する材料で形成された凹
状部材の該凹部内に、リードフレームのアイランド上に
受光面を上にして装着された半導体素子と、ボンディン
グ線を介して接続されたリードフレームのリード部とを
配置し、前記半導体素子と、ボンディング線と、リード
フレームのアイランドおよびリード部の少なくとも一部
とを、紫外線を透過する第１の封止樹脂で封止して内部
パッケージを形成し、次に、該内部パッケージを、前記
凹部の一部とリードフレームの端部とを外部に露出せし
めて第２の封止樹脂で封止形成してなることを特徴とす
る樹脂封止型半導体装置。A semiconductor element is mounted with its light-receiving surface facing up on an island of a lead frame in the recess of a recessed member, at least a portion of which is made of a material that transmits ultraviolet rays, and the lead frame is connected via a bonding wire. the semiconductor element, the bonding wire, the island of the lead frame, and at least a portion of the lead portion are sealed with a first sealing resin that transmits ultraviolet rays to form an internal package. and then, the internal package is sealed with a second sealing resin with a part of the recess and an end of the lead frame exposed to the outside. Semiconductor equipment.
JP60029313A 1985-02-19 1985-02-19 Resin-sealed semiconductor device Pending JPS61189656A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60029313A JPS61189656A (en) 1985-02-19 1985-02-19 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60029313A JPS61189656A (en) 1985-02-19 1985-02-19 Resin-sealed semiconductor device

Publications (1)

Publication Number Publication Date
JPS61189656A true JPS61189656A (en) 1986-08-23

Family

ID=12272726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60029313A Pending JPS61189656A (en) 1985-02-19 1985-02-19 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JPS61189656A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5406699A (en) * 1992-09-18 1995-04-18 Matsushita Electric Industrial Co., Ltd. Method of manufacturing an electronics package
EP0774162A4 (en) * 1994-06-28 1997-07-30 Intel Corp Manufacturing dual sided wire bonded integrated circuit chip packages using offset wire bonds and support block cavities
WO2011000597A1 (en) * 2009-06-30 2011-01-06 Robert Bosch Gmbh Method for producing an electronic component

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5406699A (en) * 1992-09-18 1995-04-18 Matsushita Electric Industrial Co., Ltd. Method of manufacturing an electronics package
EP0774162A4 (en) * 1994-06-28 1997-07-30 Intel Corp Manufacturing dual sided wire bonded integrated circuit chip packages using offset wire bonds and support block cavities
WO2011000597A1 (en) * 2009-06-30 2011-01-06 Robert Bosch Gmbh Method for producing an electronic component
US8916079B2 (en) 2009-06-30 2014-12-23 Robert Bosch Gmbh Method for producing an electronic component

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